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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/i386/pc.h"
28#include "hw/char/serial.h"
29#include "hw/char/parallel.h"
30#include "hw/i386/apic.h"
31#include "hw/i386/topology.h"
32#include "sysemu/cpus.h"
33#include "hw/block/fdc.h"
34#include "hw/ide.h"
35#include "hw/pci/pci.h"
36#include "hw/pci/pci_bus.h"
37#include "hw/nvram/fw_cfg.h"
38#include "hw/timer/hpet.h"
39#include "hw/smbios/smbios.h"
40#include "hw/loader.h"
41#include "elf.h"
42#include "multiboot.h"
43#include "hw/timer/mc146818rtc.h"
44#include "hw/dma/i8257.h"
45#include "hw/timer/i8254.h"
46#include "hw/input/i8042.h"
47#include "hw/audio/pcspk.h"
48#include "hw/pci/msi.h"
49#include "hw/sysbus.h"
50#include "sysemu/sysemu.h"
51#include "sysemu/numa.h"
52#include "sysemu/kvm.h"
53#include "sysemu/qtest.h"
54#include "kvm_i386.h"
55#include "hw/xen/xen.h"
56#include "ui/qemu-spice.h"
57#include "exec/memory.h"
58#include "exec/address-spaces.h"
59#include "sysemu/arch_init.h"
60#include "qemu/bitmap.h"
61#include "qemu/config-file.h"
62#include "qemu/error-report.h"
63#include "qemu/option.h"
64#include "hw/acpi/acpi.h"
65#include "hw/acpi/cpu_hotplug.h"
66#include "hw/boards.h"
67#include "hw/pci/pci_host.h"
68#include "acpi-build.h"
69#include "hw/mem/pc-dimm.h"
70#include "qapi/error.h"
71#include "qapi/qapi-visit-common.h"
72#include "qapi/visitor.h"
73#include "qom/cpu.h"
74#include "hw/nmi.h"
75#include "hw/i386/intel_iommu.h"
76#include "hw/net/ne2000-isa.h"
77
78
79
80
81#ifdef DEBUG_IRQ
82#define DPRINTF(fmt, ...) \
83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
84#else
85#define DPRINTF(fmt, ...)
86#endif
87
88#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
89#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
90#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
91#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
92#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
93
94#define E820_NR_ENTRIES 16
95
96struct e820_entry {
97 uint64_t address;
98 uint64_t length;
99 uint32_t type;
100} QEMU_PACKED __attribute((__aligned__(4)));
101
102struct e820_table {
103 uint32_t count;
104 struct e820_entry entry[E820_NR_ENTRIES];
105} QEMU_PACKED __attribute((__aligned__(4)));
106
107static struct e820_table e820_reserve;
108static struct e820_entry *e820_table;
109static unsigned e820_entries;
110struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
111
112void gsi_handler(void *opaque, int n, int level)
113{
114 GSIState *s = opaque;
115
116 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
117 if (n < ISA_NUM_IRQS) {
118 qemu_set_irq(s->i8259_irq[n], level);
119 }
120 qemu_set_irq(s->ioapic_irq[n], level);
121}
122
123static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
124 unsigned size)
125{
126}
127
128static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
129{
130 return 0xffffffffffffffffULL;
131}
132
133
134static qemu_irq ferr_irq;
135
136void pc_register_ferr_irq(qemu_irq irq)
137{
138 ferr_irq = irq;
139}
140
141
142void cpu_set_ferr(CPUX86State *s)
143{
144 qemu_irq_raise(ferr_irq);
145}
146
147static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
148 unsigned size)
149{
150 qemu_irq_lower(ferr_irq);
151}
152
153static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
154{
155 return 0xffffffffffffffffULL;
156}
157
158
159uint64_t cpu_get_tsc(CPUX86State *env)
160{
161 return cpu_get_ticks();
162}
163
164
165int cpu_get_pic_interrupt(CPUX86State *env)
166{
167 X86CPU *cpu = x86_env_get_cpu(env);
168 int intno;
169
170 if (!kvm_irqchip_in_kernel()) {
171 intno = apic_get_interrupt(cpu->apic_state);
172 if (intno >= 0) {
173 return intno;
174 }
175
176 if (!apic_accept_pic_intr(cpu->apic_state)) {
177 return -1;
178 }
179 }
180
181 intno = pic_read_irq(isa_pic);
182 return intno;
183}
184
185static void pic_irq_request(void *opaque, int irq, int level)
186{
187 CPUState *cs = first_cpu;
188 X86CPU *cpu = X86_CPU(cs);
189
190 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
191 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
192 CPU_FOREACH(cs) {
193 cpu = X86_CPU(cs);
194 if (apic_accept_pic_intr(cpu->apic_state)) {
195 apic_deliver_pic_intr(cpu->apic_state, level);
196 }
197 }
198 } else {
199 if (level) {
200 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
201 } else {
202 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
203 }
204 }
205}
206
207
208
209#define REG_EQUIPMENT_BYTE 0x14
210
211int cmos_get_fd_drive_type(FloppyDriveType fd0)
212{
213 int val;
214
215 switch (fd0) {
216 case FLOPPY_DRIVE_TYPE_144:
217
218 val = 4;
219 break;
220 case FLOPPY_DRIVE_TYPE_288:
221
222 val = 5;
223 break;
224 case FLOPPY_DRIVE_TYPE_120:
225
226 val = 2;
227 break;
228 case FLOPPY_DRIVE_TYPE_NONE:
229 default:
230 val = 0;
231 break;
232 }
233 return val;
234}
235
236static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
237 int16_t cylinders, int8_t heads, int8_t sectors)
238{
239 rtc_set_memory(s, type_ofs, 47);
240 rtc_set_memory(s, info_ofs, cylinders);
241 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
242 rtc_set_memory(s, info_ofs + 2, heads);
243 rtc_set_memory(s, info_ofs + 3, 0xff);
244 rtc_set_memory(s, info_ofs + 4, 0xff);
245 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
246 rtc_set_memory(s, info_ofs + 6, cylinders);
247 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
248 rtc_set_memory(s, info_ofs + 8, sectors);
249}
250
251
252static int boot_device2nibble(char boot_device)
253{
254 switch(boot_device) {
255 case 'a':
256 case 'b':
257 return 0x01;
258 case 'c':
259 return 0x02;
260 case 'd':
261 return 0x03;
262 case 'n':
263 return 0x04;
264 }
265 return 0;
266}
267
268static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
269{
270#define PC_MAX_BOOT_DEVICES 3
271 int nbds, bds[3] = { 0, };
272 int i;
273
274 nbds = strlen(boot_device);
275 if (nbds > PC_MAX_BOOT_DEVICES) {
276 error_setg(errp, "Too many boot devices for PC");
277 return;
278 }
279 for (i = 0; i < nbds; i++) {
280 bds[i] = boot_device2nibble(boot_device[i]);
281 if (bds[i] == 0) {
282 error_setg(errp, "Invalid boot device for PC: '%c'",
283 boot_device[i]);
284 return;
285 }
286 }
287 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
288 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
289}
290
291static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
292{
293 set_boot_dev(opaque, boot_device, errp);
294}
295
296static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
297{
298 int val, nb, i;
299 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
300 FLOPPY_DRIVE_TYPE_NONE };
301
302
303 if (floppy) {
304 for (i = 0; i < 2; i++) {
305 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
306 }
307 }
308 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
309 cmos_get_fd_drive_type(fd_type[1]);
310 rtc_set_memory(rtc_state, 0x10, val);
311
312 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
313 nb = 0;
314 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
315 nb++;
316 }
317 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
318 nb++;
319 }
320 switch (nb) {
321 case 0:
322 break;
323 case 1:
324 val |= 0x01;
325 break;
326 case 2:
327 val |= 0x41;
328 break;
329 }
330 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
331}
332
333typedef struct pc_cmos_init_late_arg {
334 ISADevice *rtc_state;
335 BusState *idebus[2];
336} pc_cmos_init_late_arg;
337
338typedef struct check_fdc_state {
339 ISADevice *floppy;
340 bool multiple;
341} CheckFdcState;
342
343static int check_fdc(Object *obj, void *opaque)
344{
345 CheckFdcState *state = opaque;
346 Object *fdc;
347 uint32_t iobase;
348 Error *local_err = NULL;
349
350 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
351 if (!fdc) {
352 return 0;
353 }
354
355 iobase = object_property_get_uint(obj, "iobase", &local_err);
356 if (local_err || iobase != 0x3f0) {
357 error_free(local_err);
358 return 0;
359 }
360
361 if (state->floppy) {
362 state->multiple = true;
363 } else {
364 state->floppy = ISA_DEVICE(obj);
365 }
366 return 0;
367}
368
369static const char * const fdc_container_path[] = {
370 "/unattached", "/peripheral", "/peripheral-anon"
371};
372
373
374
375
376
377ISADevice *pc_find_fdc0(void)
378{
379 int i;
380 Object *container;
381 CheckFdcState state = { 0 };
382
383 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
384 container = container_get(qdev_get_machine(), fdc_container_path[i]);
385 object_child_foreach(container, check_fdc, &state);
386 }
387
388 if (state.multiple) {
389 warn_report("multiple floppy disk controllers with "
390 "iobase=0x3f0 have been found");
391 error_printf("the one being picked for CMOS setup might not reflect "
392 "your intent");
393 }
394
395 return state.floppy;
396}
397
398static void pc_cmos_init_late(void *opaque)
399{
400 pc_cmos_init_late_arg *arg = opaque;
401 ISADevice *s = arg->rtc_state;
402 int16_t cylinders;
403 int8_t heads, sectors;
404 int val;
405 int i, trans;
406
407 val = 0;
408 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
409 &cylinders, &heads, §ors) >= 0) {
410 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
411 val |= 0xf0;
412 }
413 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
414 &cylinders, &heads, §ors) >= 0) {
415 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
416 val |= 0x0f;
417 }
418 rtc_set_memory(s, 0x12, val);
419
420 val = 0;
421 for (i = 0; i < 4; i++) {
422
423
424
425
426 if (arg->idebus[i / 2] &&
427 ide_get_geometry(arg->idebus[i / 2], i % 2,
428 &cylinders, &heads, §ors) >= 0) {
429 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
430 assert((trans & ~3) == 0);
431 val |= trans << (i * 2);
432 }
433 }
434 rtc_set_memory(s, 0x39, val);
435
436 pc_cmos_init_floppy(s, pc_find_fdc0());
437
438 qemu_unregister_reset(pc_cmos_init_late, opaque);
439}
440
441void pc_cmos_init(PCMachineState *pcms,
442 BusState *idebus0, BusState *idebus1,
443 ISADevice *s)
444{
445 int val;
446 static pc_cmos_init_late_arg arg;
447
448
449
450
451
452 val = MIN(pcms->below_4g_mem_size / 1024, 640);
453 rtc_set_memory(s, 0x15, val);
454 rtc_set_memory(s, 0x16, val >> 8);
455
456 if (pcms->below_4g_mem_size > 1024 * 1024) {
457 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
458 } else {
459 val = 0;
460 }
461 if (val > 65535)
462 val = 65535;
463 rtc_set_memory(s, 0x17, val);
464 rtc_set_memory(s, 0x18, val >> 8);
465 rtc_set_memory(s, 0x30, val);
466 rtc_set_memory(s, 0x31, val >> 8);
467
468 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
469 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
470 } else {
471 val = 0;
472 }
473 if (val > 65535)
474 val = 65535;
475 rtc_set_memory(s, 0x34, val);
476 rtc_set_memory(s, 0x35, val >> 8);
477
478 val = pcms->above_4g_mem_size / 65536;
479 rtc_set_memory(s, 0x5b, val);
480 rtc_set_memory(s, 0x5c, val >> 8);
481 rtc_set_memory(s, 0x5d, val >> 16);
482
483 object_property_add_link(OBJECT(pcms), "rtc_state",
484 TYPE_ISA_DEVICE,
485 (Object **)&pcms->rtc,
486 object_property_allow_set_link,
487 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
488 object_property_set_link(OBJECT(pcms), OBJECT(s),
489 "rtc_state", &error_abort);
490
491 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
492
493 val = 0;
494 val |= 0x02;
495 val |= 0x04;
496 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
497
498
499 arg.rtc_state = s;
500 arg.idebus[0] = idebus0;
501 arg.idebus[1] = idebus1;
502 qemu_register_reset(pc_cmos_init_late, &arg);
503}
504
505#define TYPE_PORT92 "port92"
506#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
507
508
509typedef struct Port92State {
510 ISADevice parent_obj;
511
512 MemoryRegion io;
513 uint8_t outport;
514 qemu_irq a20_out;
515} Port92State;
516
517static void port92_write(void *opaque, hwaddr addr, uint64_t val,
518 unsigned size)
519{
520 Port92State *s = opaque;
521 int oldval = s->outport;
522
523 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
524 s->outport = val;
525 qemu_set_irq(s->a20_out, (val >> 1) & 1);
526 if ((val & 1) && !(oldval & 1)) {
527 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
528 }
529}
530
531static uint64_t port92_read(void *opaque, hwaddr addr,
532 unsigned size)
533{
534 Port92State *s = opaque;
535 uint32_t ret;
536
537 ret = s->outport;
538 DPRINTF("port92: read 0x%02x\n", ret);
539 return ret;
540}
541
542static void port92_init(ISADevice *dev, qemu_irq a20_out)
543{
544 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
545}
546
547static const VMStateDescription vmstate_port92_isa = {
548 .name = "port92",
549 .version_id = 1,
550 .minimum_version_id = 1,
551 .fields = (VMStateField[]) {
552 VMSTATE_UINT8(outport, Port92State),
553 VMSTATE_END_OF_LIST()
554 }
555};
556
557static void port92_reset(DeviceState *d)
558{
559 Port92State *s = PORT92(d);
560
561 s->outport &= ~1;
562}
563
564static const MemoryRegionOps port92_ops = {
565 .read = port92_read,
566 .write = port92_write,
567 .impl = {
568 .min_access_size = 1,
569 .max_access_size = 1,
570 },
571 .endianness = DEVICE_LITTLE_ENDIAN,
572};
573
574static void port92_initfn(Object *obj)
575{
576 Port92State *s = PORT92(obj);
577
578 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
579
580 s->outport = 0;
581
582 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
583}
584
585static void port92_realizefn(DeviceState *dev, Error **errp)
586{
587 ISADevice *isadev = ISA_DEVICE(dev);
588 Port92State *s = PORT92(dev);
589
590 isa_register_ioport(isadev, &s->io, 0x92);
591}
592
593static void port92_class_initfn(ObjectClass *klass, void *data)
594{
595 DeviceClass *dc = DEVICE_CLASS(klass);
596
597 dc->realize = port92_realizefn;
598 dc->reset = port92_reset;
599 dc->vmsd = &vmstate_port92_isa;
600
601
602
603
604
605 dc->user_creatable = false;
606}
607
608static const TypeInfo port92_info = {
609 .name = TYPE_PORT92,
610 .parent = TYPE_ISA_DEVICE,
611 .instance_size = sizeof(Port92State),
612 .instance_init = port92_initfn,
613 .class_init = port92_class_initfn,
614};
615
616static void port92_register_types(void)
617{
618 type_register_static(&port92_info);
619}
620
621type_init(port92_register_types)
622
623static void handle_a20_line_change(void *opaque, int irq, int level)
624{
625 X86CPU *cpu = opaque;
626
627
628
629 x86_cpu_set_a20(cpu, level);
630}
631
632int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
633{
634 int index = le32_to_cpu(e820_reserve.count);
635 struct e820_entry *entry;
636
637 if (type != E820_RAM) {
638
639 if (index >= E820_NR_ENTRIES) {
640 return -EBUSY;
641 }
642 entry = &e820_reserve.entry[index++];
643
644 entry->address = cpu_to_le64(address);
645 entry->length = cpu_to_le64(length);
646 entry->type = cpu_to_le32(type);
647
648 e820_reserve.count = cpu_to_le32(index);
649 }
650
651
652 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
653 e820_table[e820_entries].address = cpu_to_le64(address);
654 e820_table[e820_entries].length = cpu_to_le64(length);
655 e820_table[e820_entries].type = cpu_to_le32(type);
656 e820_entries++;
657
658 return e820_entries;
659}
660
661int e820_get_num_entries(void)
662{
663 return e820_entries;
664}
665
666bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
667{
668 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
669 *address = le64_to_cpu(e820_table[idx].address);
670 *length = le64_to_cpu(e820_table[idx].length);
671 return true;
672 }
673 return false;
674}
675
676
677static bool compat_apic_id_mode;
678
679void enable_compat_apic_id_mode(void)
680{
681 compat_apic_id_mode = true;
682}
683
684
685
686
687
688
689
690
691static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
692{
693 uint32_t correct_id;
694 static bool warned;
695
696 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
697 if (compat_apic_id_mode) {
698 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
699 error_report("APIC IDs set in compatibility mode, "
700 "CPU topology won't match the configuration");
701 warned = true;
702 }
703 return cpu_index;
704 } else {
705 return correct_id;
706 }
707}
708
709static void pc_build_smbios(PCMachineState *pcms)
710{
711 uint8_t *smbios_tables, *smbios_anchor;
712 size_t smbios_tables_len, smbios_anchor_len;
713 struct smbios_phys_mem_area *mem_array;
714 unsigned i, array_count;
715 MachineState *ms = MACHINE(pcms);
716 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
717
718
719 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
720
721 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
722 if (smbios_tables) {
723 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
724 smbios_tables, smbios_tables_len);
725 }
726
727
728 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
729 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
730 uint64_t addr, len;
731
732 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
733 mem_array[array_count].address = addr;
734 mem_array[array_count].length = len;
735 array_count++;
736 }
737 }
738 smbios_get_tables(mem_array, array_count,
739 &smbios_tables, &smbios_tables_len,
740 &smbios_anchor, &smbios_anchor_len);
741 g_free(mem_array);
742
743 if (smbios_anchor) {
744 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
745 smbios_tables, smbios_tables_len);
746 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
747 smbios_anchor, smbios_anchor_len);
748 }
749}
750
751static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
752{
753 FWCfgState *fw_cfg;
754 uint64_t *numa_fw_cfg;
755 int i;
756 const CPUArchIdList *cpus;
757 MachineClass *mc = MACHINE_GET_CLASS(pcms);
758
759 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
760 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
761
762
763
764
765
766
767
768
769
770
771
772
773
774 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
775 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
776 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
777 acpi_tables, acpi_tables_len);
778 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
779
780 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
781 &e820_reserve, sizeof(e820_reserve));
782 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
783 sizeof(struct e820_entry) * e820_entries);
784
785 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
786
787
788
789
790 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
791 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
792 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
793 for (i = 0; i < cpus->len; i++) {
794 unsigned int apic_id = cpus->cpus[i].arch_id;
795 assert(apic_id < pcms->apic_id_limit);
796 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
797 }
798 for (i = 0; i < nb_numa_nodes; i++) {
799 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
800 cpu_to_le64(numa_info[i].node_mem);
801 }
802 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
803 (1 + pcms->apic_id_limit + nb_numa_nodes) *
804 sizeof(*numa_fw_cfg));
805
806 return fw_cfg;
807}
808
809static long get_file_size(FILE *f)
810{
811 long where, size;
812
813
814
815 where = ftell(f);
816 fseek(f, 0, SEEK_END);
817 size = ftell(f);
818 fseek(f, where, SEEK_SET);
819
820 return size;
821}
822
823
824#define SETUP_NONE 0
825#define SETUP_E820_EXT 1
826#define SETUP_DTB 2
827#define SETUP_PCI 3
828#define SETUP_EFI 4
829
830struct setup_data {
831 uint64_t next;
832 uint32_t type;
833 uint32_t len;
834 uint8_t data[0];
835} __attribute__((packed));
836
837static void load_linux(PCMachineState *pcms,
838 FWCfgState *fw_cfg)
839{
840 uint16_t protocol;
841 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
842 int dtb_size, setup_data_offset;
843 uint32_t initrd_max;
844 uint8_t header[8192], *setup, *kernel, *initrd_data;
845 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
846 FILE *f;
847 char *vmode;
848 MachineState *machine = MACHINE(pcms);
849 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
850 struct setup_data *setup_data;
851 const char *kernel_filename = machine->kernel_filename;
852 const char *initrd_filename = machine->initrd_filename;
853 const char *dtb_filename = machine->dtb;
854 const char *kernel_cmdline = machine->kernel_cmdline;
855
856
857 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
858
859
860 f = fopen(kernel_filename, "rb");
861 if (!f || !(kernel_size = get_file_size(f)) ||
862 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
863 MIN(ARRAY_SIZE(header), kernel_size)) {
864 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
865 kernel_filename, strerror(errno));
866 exit(1);
867 }
868
869
870#if 0
871 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
872#endif
873 if (ldl_p(header+0x202) == 0x53726448) {
874 protocol = lduw_p(header+0x206);
875 } else {
876
877
878 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
879 kernel_cmdline, kernel_size, header)) {
880 return;
881 }
882 protocol = 0;
883 }
884
885 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
886
887 real_addr = 0x90000;
888 cmdline_addr = 0x9a000 - cmdline_size;
889 prot_addr = 0x10000;
890 } else if (protocol < 0x202) {
891
892 real_addr = 0x90000;
893 cmdline_addr = 0x9a000 - cmdline_size;
894 prot_addr = 0x100000;
895 } else {
896
897 real_addr = 0x10000;
898 cmdline_addr = 0x20000;
899 prot_addr = 0x100000;
900 }
901
902#if 0
903 fprintf(stderr,
904 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
905 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
906 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
907 real_addr,
908 cmdline_addr,
909 prot_addr);
910#endif
911
912
913 if (protocol >= 0x203) {
914 initrd_max = ldl_p(header+0x22c);
915 } else {
916 initrd_max = 0x37ffffff;
917 }
918
919 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
920 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
921 }
922
923 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
924 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
925 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
926
927 if (protocol >= 0x202) {
928 stl_p(header+0x228, cmdline_addr);
929 } else {
930 stw_p(header+0x20, 0xA33F);
931 stw_p(header+0x22, cmdline_addr-real_addr);
932 }
933
934
935 vmode = strstr(kernel_cmdline, "vga=");
936 if (vmode) {
937 unsigned int video_mode;
938
939 vmode += 4;
940 if (!strncmp(vmode, "normal", 6)) {
941 video_mode = 0xffff;
942 } else if (!strncmp(vmode, "ext", 3)) {
943 video_mode = 0xfffe;
944 } else if (!strncmp(vmode, "ask", 3)) {
945 video_mode = 0xfffd;
946 } else {
947 video_mode = strtol(vmode, NULL, 0);
948 }
949 stw_p(header+0x1fa, video_mode);
950 }
951
952
953
954
955
956 if (protocol >= 0x200) {
957 header[0x210] = 0xB0;
958 }
959
960 if (protocol >= 0x201) {
961 header[0x211] |= 0x80;
962 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
963 }
964
965
966 if (initrd_filename) {
967 if (protocol < 0x200) {
968 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
969 exit(1);
970 }
971
972 initrd_size = get_image_size(initrd_filename);
973 if (initrd_size < 0) {
974 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
975 initrd_filename, strerror(errno));
976 exit(1);
977 }
978
979 initrd_addr = (initrd_max-initrd_size) & ~4095;
980
981 initrd_data = g_malloc(initrd_size);
982 load_image(initrd_filename, initrd_data);
983
984 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
985 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
986 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
987
988 stl_p(header+0x218, initrd_addr);
989 stl_p(header+0x21c, initrd_size);
990 }
991
992
993 setup_size = header[0x1f1];
994 if (setup_size == 0) {
995 setup_size = 4;
996 }
997 setup_size = (setup_size+1)*512;
998 if (setup_size > kernel_size) {
999 fprintf(stderr, "qemu: invalid kernel header\n");
1000 exit(1);
1001 }
1002 kernel_size -= setup_size;
1003
1004 setup = g_malloc(setup_size);
1005 kernel = g_malloc(kernel_size);
1006 fseek(f, 0, SEEK_SET);
1007 if (fread(setup, 1, setup_size, f) != setup_size) {
1008 fprintf(stderr, "fread() failed\n");
1009 exit(1);
1010 }
1011 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1012 fprintf(stderr, "fread() failed\n");
1013 exit(1);
1014 }
1015 fclose(f);
1016
1017
1018 if (dtb_filename) {
1019 if (protocol < 0x209) {
1020 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1021 exit(1);
1022 }
1023
1024 dtb_size = get_image_size(dtb_filename);
1025 if (dtb_size <= 0) {
1026 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1027 dtb_filename, strerror(errno));
1028 exit(1);
1029 }
1030
1031 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1032 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1033 kernel = g_realloc(kernel, kernel_size);
1034
1035 stq_p(header+0x250, prot_addr + setup_data_offset);
1036
1037 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1038 setup_data->next = 0;
1039 setup_data->type = cpu_to_le32(SETUP_DTB);
1040 setup_data->len = cpu_to_le32(dtb_size);
1041
1042 load_image_size(dtb_filename, setup_data->data, dtb_size);
1043 }
1044
1045 memcpy(setup, header, MIN(sizeof(header), setup_size));
1046
1047 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1048 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1049 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1050
1051 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1052 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1053 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1054
1055 option_rom[nb_option_roms].bootindex = 0;
1056 option_rom[nb_option_roms].name = "linuxboot.bin";
1057 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1058 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1059 }
1060 nb_option_roms++;
1061}
1062
1063#define NE2000_NB_MAX 6
1064
1065static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1066 0x280, 0x380 };
1067static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1068
1069void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1070{
1071 static int nb_ne2k = 0;
1072
1073 if (nb_ne2k == NE2000_NB_MAX)
1074 return;
1075 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1076 ne2000_irq[nb_ne2k], nd);
1077 nb_ne2k++;
1078}
1079
1080DeviceState *cpu_get_current_apic(void)
1081{
1082 if (current_cpu) {
1083 X86CPU *cpu = X86_CPU(current_cpu);
1084 return cpu->apic_state;
1085 } else {
1086 return NULL;
1087 }
1088}
1089
1090void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1091{
1092 X86CPU *cpu = opaque;
1093
1094 if (level) {
1095 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1096 }
1097}
1098
1099static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1100{
1101 Object *cpu = NULL;
1102 Error *local_err = NULL;
1103
1104 cpu = object_new(typename);
1105
1106 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1107 object_property_set_bool(cpu, true, "realized", &local_err);
1108
1109 object_unref(cpu);
1110 error_propagate(errp, local_err);
1111}
1112
1113void pc_hot_add_cpu(const int64_t id, Error **errp)
1114{
1115 MachineState *ms = MACHINE(qdev_get_machine());
1116 int64_t apic_id = x86_cpu_apic_id_from_index(id);
1117 Error *local_err = NULL;
1118
1119 if (id < 0) {
1120 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1121 return;
1122 }
1123
1124 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1125 error_setg(errp, "Unable to add CPU: %" PRIi64
1126 ", resulting APIC ID (%" PRIi64 ") is too large",
1127 id, apic_id);
1128 return;
1129 }
1130
1131 pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1132 if (local_err) {
1133 error_propagate(errp, local_err);
1134 return;
1135 }
1136}
1137
1138void pc_cpus_init(PCMachineState *pcms)
1139{
1140 int i;
1141 const CPUArchIdList *possible_cpus;
1142 MachineState *ms = MACHINE(pcms);
1143 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1144
1145
1146
1147
1148
1149
1150
1151
1152 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1153 possible_cpus = mc->possible_cpu_arch_ids(ms);
1154 for (i = 0; i < smp_cpus; i++) {
1155 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1156 &error_fatal);
1157 }
1158}
1159
1160static void pc_build_feature_control_file(PCMachineState *pcms)
1161{
1162 MachineState *ms = MACHINE(pcms);
1163 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1164 CPUX86State *env = &cpu->env;
1165 uint32_t unused, ecx, edx;
1166 uint64_t feature_control_bits = 0;
1167 uint64_t *val;
1168
1169 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1170 if (ecx & CPUID_EXT_VMX) {
1171 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1172 }
1173
1174 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1175 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1176 (env->mcg_cap & MCG_LMCE_P)) {
1177 feature_control_bits |= FEATURE_CONTROL_LMCE;
1178 }
1179
1180 if (!feature_control_bits) {
1181 return;
1182 }
1183
1184 val = g_malloc(sizeof(*val));
1185 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1186 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1187}
1188
1189static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1190{
1191 if (cpus_count > 0xff) {
1192
1193
1194
1195
1196 rtc_set_memory(rtc, 0x5f, 0);
1197 } else {
1198 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1199 }
1200}
1201
1202static
1203void pc_machine_done(Notifier *notifier, void *data)
1204{
1205 PCMachineState *pcms = container_of(notifier,
1206 PCMachineState, machine_done);
1207 PCIBus *bus = pcms->bus;
1208
1209
1210 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1211
1212 if (bus) {
1213 int extra_hosts = 0;
1214
1215 QLIST_FOREACH(bus, &bus->child, sibling) {
1216
1217 if (pci_bus_is_root(bus)) {
1218 extra_hosts++;
1219 }
1220 }
1221 if (extra_hosts && pcms->fw_cfg) {
1222 uint64_t *val = g_malloc(sizeof(*val));
1223 *val = cpu_to_le64(extra_hosts);
1224 fw_cfg_add_file(pcms->fw_cfg,
1225 "etc/extra-pci-roots", val, sizeof(*val));
1226 }
1227 }
1228
1229 acpi_setup();
1230 if (pcms->fw_cfg) {
1231 pc_build_smbios(pcms);
1232 pc_build_feature_control_file(pcms);
1233
1234 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1235 }
1236
1237 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1238 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1239
1240 if (!iommu || !iommu->x86_iommu.intr_supported ||
1241 iommu->intr_eim != ON_OFF_AUTO_ON) {
1242 error_report("current -smp configuration requires "
1243 "Extended Interrupt Mode enabled. "
1244 "You can add an IOMMU using: "
1245 "-device intel-iommu,intremap=on,eim=on");
1246 exit(EXIT_FAILURE);
1247 }
1248 }
1249}
1250
1251void pc_guest_info_init(PCMachineState *pcms)
1252{
1253 int i;
1254
1255 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1256 pcms->numa_nodes = nb_numa_nodes;
1257 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1258 sizeof *pcms->node_mem);
1259 for (i = 0; i < nb_numa_nodes; i++) {
1260 pcms->node_mem[i] = numa_info[i].node_mem;
1261 }
1262
1263 pcms->machine_done.notify = pc_machine_done;
1264 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1265}
1266
1267
1268void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1269 MemoryRegion *pci_address_space)
1270{
1271
1272 memory_region_add_subregion_overlap(system_memory, 0x0,
1273 pci_address_space, -1);
1274}
1275
1276void pc_acpi_init(const char *default_dsdt)
1277{
1278 char *filename;
1279
1280 if (acpi_tables != NULL) {
1281
1282 return;
1283 }
1284
1285 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1286 if (filename == NULL) {
1287 warn_report("failed to find %s", default_dsdt);
1288 } else {
1289 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1290 &error_abort);
1291 Error *err = NULL;
1292
1293 qemu_opt_set(opts, "file", filename, &error_abort);
1294
1295 acpi_table_add_builtin(opts, &err);
1296 if (err) {
1297 warn_reportf_err(err, "failed to load %s: ", filename);
1298 }
1299 g_free(filename);
1300 }
1301}
1302
1303void xen_load_linux(PCMachineState *pcms)
1304{
1305 int i;
1306 FWCfgState *fw_cfg;
1307
1308 assert(MACHINE(pcms)->kernel_filename != NULL);
1309
1310 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1311 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1312 rom_set_fw(fw_cfg);
1313
1314 load_linux(pcms, fw_cfg);
1315 for (i = 0; i < nb_option_roms; i++) {
1316 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1317 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1318 !strcmp(option_rom[i].name, "multiboot.bin"));
1319 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1320 }
1321 pcms->fw_cfg = fw_cfg;
1322}
1323
1324void pc_memory_init(PCMachineState *pcms,
1325 MemoryRegion *system_memory,
1326 MemoryRegion *rom_memory,
1327 MemoryRegion **ram_memory)
1328{
1329 int linux_boot, i;
1330 MemoryRegion *ram, *option_rom_mr;
1331 MemoryRegion *ram_below_4g, *ram_above_4g;
1332 FWCfgState *fw_cfg;
1333 MachineState *machine = MACHINE(pcms);
1334 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1335
1336 assert(machine->ram_size == pcms->below_4g_mem_size +
1337 pcms->above_4g_mem_size);
1338
1339 linux_boot = (machine->kernel_filename != NULL);
1340
1341
1342
1343
1344
1345 ram = g_malloc(sizeof(*ram));
1346 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1347 machine->ram_size);
1348 *ram_memory = ram;
1349 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1350 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1351 0, pcms->below_4g_mem_size);
1352 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1353 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1354 if (pcms->above_4g_mem_size > 0) {
1355 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1356 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1357 pcms->below_4g_mem_size,
1358 pcms->above_4g_mem_size);
1359 memory_region_add_subregion(system_memory, 0x100000000ULL,
1360 ram_above_4g);
1361 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1362 }
1363
1364 if (!pcmc->has_reserved_memory &&
1365 (machine->ram_slots ||
1366 (machine->maxram_size > machine->ram_size))) {
1367 MachineClass *mc = MACHINE_GET_CLASS(machine);
1368
1369 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1370 mc->name);
1371 exit(EXIT_FAILURE);
1372 }
1373
1374
1375 if (pcmc->has_reserved_memory &&
1376 (machine->ram_size < machine->maxram_size)) {
1377 ram_addr_t hotplug_mem_size =
1378 machine->maxram_size - machine->ram_size;
1379
1380 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1381 error_report("unsupported amount of memory slots: %"PRIu64,
1382 machine->ram_slots);
1383 exit(EXIT_FAILURE);
1384 }
1385
1386 if (QEMU_ALIGN_UP(machine->maxram_size,
1387 TARGET_PAGE_SIZE) != machine->maxram_size) {
1388 error_report("maximum memory size must by aligned to multiple of "
1389 "%d bytes", TARGET_PAGE_SIZE);
1390 exit(EXIT_FAILURE);
1391 }
1392
1393 pcms->hotplug_memory.base =
1394 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
1395
1396 if (pcmc->enforce_aligned_dimm) {
1397
1398 hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
1399 }
1400
1401 if ((pcms->hotplug_memory.base + hotplug_mem_size) <
1402 hotplug_mem_size) {
1403 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1404 machine->maxram_size);
1405 exit(EXIT_FAILURE);
1406 }
1407
1408 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms),
1409 "hotplug-memory", hotplug_mem_size);
1410 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base,
1411 &pcms->hotplug_memory.mr);
1412 }
1413
1414
1415 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1416
1417 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1418 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1419 &error_fatal);
1420 if (pcmc->pci_enabled) {
1421 memory_region_set_readonly(option_rom_mr, true);
1422 }
1423 memory_region_add_subregion_overlap(rom_memory,
1424 PC_ROM_MIN_VGA,
1425 option_rom_mr,
1426 1);
1427
1428 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1429
1430 rom_set_fw(fw_cfg);
1431
1432 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) {
1433 uint64_t *val = g_malloc(sizeof(*val));
1434 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1435 uint64_t res_mem_end = pcms->hotplug_memory.base;
1436
1437 if (!pcmc->broken_reserved_end) {
1438 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
1439 }
1440 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
1441 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1442 }
1443
1444 if (linux_boot) {
1445 load_linux(pcms, fw_cfg);
1446 }
1447
1448 for (i = 0; i < nb_option_roms; i++) {
1449 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1450 }
1451 pcms->fw_cfg = fw_cfg;
1452
1453
1454 pcms->ioapic_as = &address_space_memory;
1455}
1456
1457
1458
1459
1460
1461uint64_t pc_pci_hole64_start(void)
1462{
1463 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1464 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1465 uint64_t hole64_start = 0;
1466
1467 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) {
1468 hole64_start = pcms->hotplug_memory.base;
1469 if (!pcmc->broken_reserved_end) {
1470 hole64_start += memory_region_size(&pcms->hotplug_memory.mr);
1471 }
1472 } else {
1473 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1474 }
1475
1476 return ROUND_UP(hole64_start, 1ULL << 30);
1477}
1478
1479qemu_irq pc_allocate_cpu_irq(void)
1480{
1481 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1482}
1483
1484DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1485{
1486 DeviceState *dev = NULL;
1487
1488 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1489 if (pci_bus) {
1490 PCIDevice *pcidev = pci_vga_init(pci_bus);
1491 dev = pcidev ? &pcidev->qdev : NULL;
1492 } else if (isa_bus) {
1493 ISADevice *isadev = isa_vga_init(isa_bus);
1494 dev = isadev ? DEVICE(isadev) : NULL;
1495 }
1496 rom_reset_order_override();
1497 return dev;
1498}
1499
1500static const MemoryRegionOps ioport80_io_ops = {
1501 .write = ioport80_write,
1502 .read = ioport80_read,
1503 .endianness = DEVICE_NATIVE_ENDIAN,
1504 .impl = {
1505 .min_access_size = 1,
1506 .max_access_size = 1,
1507 },
1508};
1509
1510static const MemoryRegionOps ioportF0_io_ops = {
1511 .write = ioportF0_write,
1512 .read = ioportF0_read,
1513 .endianness = DEVICE_NATIVE_ENDIAN,
1514 .impl = {
1515 .min_access_size = 1,
1516 .max_access_size = 1,
1517 },
1518};
1519
1520static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1521{
1522 int i;
1523 DriveInfo *fd[MAX_FD];
1524 qemu_irq *a20_line;
1525 ISADevice *i8042, *port92, *vmmouse;
1526
1527 serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS);
1528 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1529
1530 for (i = 0; i < MAX_FD; i++) {
1531 fd[i] = drive_get(IF_FLOPPY, 0, i);
1532 create_fdctrl |= !!fd[i];
1533 }
1534 if (create_fdctrl) {
1535 fdctrl_init_isa(isa_bus, fd);
1536 }
1537
1538 i8042 = isa_create_simple(isa_bus, "i8042");
1539 if (!no_vmport) {
1540 vmport_init(isa_bus);
1541 vmmouse = isa_try_create(isa_bus, "vmmouse");
1542 } else {
1543 vmmouse = NULL;
1544 }
1545 if (vmmouse) {
1546 DeviceState *dev = DEVICE(vmmouse);
1547 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1548 qdev_init_nofail(dev);
1549 }
1550 port92 = isa_create_simple(isa_bus, "port92");
1551
1552 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1553 i8042_setup_a20_line(i8042, a20_line[0]);
1554 port92_init(port92, a20_line[1]);
1555 g_free(a20_line);
1556}
1557
1558void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1559 ISADevice **rtc_state,
1560 bool create_fdctrl,
1561 bool no_vmport,
1562 bool has_pit,
1563 uint32_t hpet_irqs)
1564{
1565 int i;
1566 DeviceState *hpet = NULL;
1567 int pit_isa_irq = 0;
1568 qemu_irq pit_alt_irq = NULL;
1569 qemu_irq rtc_irq = NULL;
1570 ISADevice *pit = NULL;
1571 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1572 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1573
1574 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1575 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1576
1577 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1578 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1579
1580
1581
1582
1583
1584
1585
1586 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1587
1588 hpet = qdev_try_create(NULL, TYPE_HPET);
1589 if (hpet) {
1590
1591
1592
1593
1594 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1595 HPET_INTCAP, NULL);
1596 if (!compat) {
1597 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1598 }
1599 qdev_init_nofail(hpet);
1600 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1601
1602 for (i = 0; i < GSI_NUM_PINS; i++) {
1603 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1604 }
1605 pit_isa_irq = -1;
1606 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1607 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1608 }
1609 }
1610 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1611
1612 qemu_register_boot_set(pc_boot_set, *rtc_state);
1613
1614 if (!xen_enabled() && has_pit) {
1615 if (kvm_pit_in_kernel()) {
1616 pit = kvm_pit_init(isa_bus, 0x40);
1617 } else {
1618 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1619 }
1620 if (hpet) {
1621
1622 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1623 }
1624 pcspk_init(isa_bus, pit);
1625 }
1626
1627 i8257_dma_init(isa_bus, 0);
1628
1629
1630 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1631}
1632
1633void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1634{
1635 int i;
1636
1637 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1638 for (i = 0; i < nb_nics; i++) {
1639 NICInfo *nd = &nd_table[i];
1640 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1641
1642 if (g_str_equal(model, "ne2k_isa")) {
1643 pc_init_ne2k_isa(isa_bus, nd);
1644 } else {
1645 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1646 }
1647 }
1648 rom_reset_order_override();
1649}
1650
1651void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1652{
1653 DeviceState *dev;
1654 SysBusDevice *d;
1655 unsigned int i;
1656
1657 if (kvm_ioapic_in_kernel()) {
1658 dev = qdev_create(NULL, "kvm-ioapic");
1659 } else {
1660 dev = qdev_create(NULL, "ioapic");
1661 }
1662 if (parent_name) {
1663 object_property_add_child(object_resolve_path(parent_name, NULL),
1664 "ioapic", OBJECT(dev), NULL);
1665 }
1666 qdev_init_nofail(dev);
1667 d = SYS_BUS_DEVICE(dev);
1668 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1669
1670 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1671 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1672 }
1673}
1674
1675static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1676 DeviceState *dev, Error **errp)
1677{
1678 HotplugHandlerClass *hhc;
1679 Error *local_err = NULL;
1680 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1681 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1682 PCDIMMDevice *dimm = PC_DIMM(dev);
1683 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1684 MemoryRegion *mr;
1685 uint64_t align = TARGET_PAGE_SIZE;
1686 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1687
1688 mr = ddc->get_memory_region(dimm, &local_err);
1689 if (local_err) {
1690 goto out;
1691 }
1692
1693 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) {
1694 align = memory_region_get_alignment(mr);
1695 }
1696
1697
1698
1699
1700
1701
1702 if (!pcms->acpi_dev || !acpi_enabled) {
1703 error_setg(&local_err,
1704 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1705 goto out;
1706 }
1707
1708 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
1709 error_setg(&local_err,
1710 "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1711 goto out;
1712 }
1713
1714 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err);
1715 if (local_err) {
1716 goto out;
1717 }
1718
1719 if (is_nvdimm) {
1720 nvdimm_plug(&pcms->acpi_nvdimm_state);
1721 }
1722
1723 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1724 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1725out:
1726 error_propagate(errp, local_err);
1727}
1728
1729static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev,
1730 DeviceState *dev, Error **errp)
1731{
1732 HotplugHandlerClass *hhc;
1733 Error *local_err = NULL;
1734 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1735
1736
1737
1738
1739
1740
1741 if (!pcms->acpi_dev || !acpi_enabled) {
1742 error_setg(&local_err,
1743 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1744 goto out;
1745 }
1746
1747 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1748 error_setg(&local_err,
1749 "nvdimm device hot unplug is not supported yet.");
1750 goto out;
1751 }
1752
1753 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1754 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1755
1756out:
1757 error_propagate(errp, local_err);
1758}
1759
1760static void pc_dimm_unplug(HotplugHandler *hotplug_dev,
1761 DeviceState *dev, Error **errp)
1762{
1763 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1764 PCDIMMDevice *dimm = PC_DIMM(dev);
1765 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1766 MemoryRegion *mr;
1767 HotplugHandlerClass *hhc;
1768 Error *local_err = NULL;
1769
1770 mr = ddc->get_memory_region(dimm, &local_err);
1771 if (local_err) {
1772 goto out;
1773 }
1774
1775 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1776 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1777
1778 if (local_err) {
1779 goto out;
1780 }
1781
1782 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr);
1783 object_unparent(OBJECT(dev));
1784
1785 out:
1786 error_propagate(errp, local_err);
1787}
1788
1789static int pc_apic_cmp(const void *a, const void *b)
1790{
1791 CPUArchId *apic_a = (CPUArchId *)a;
1792 CPUArchId *apic_b = (CPUArchId *)b;
1793
1794 return apic_a->arch_id - apic_b->arch_id;
1795}
1796
1797
1798
1799
1800
1801static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1802{
1803 CPUArchId apic_id, *found_cpu;
1804
1805 apic_id.arch_id = id;
1806 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1807 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1808 pc_apic_cmp);
1809 if (found_cpu && idx) {
1810 *idx = found_cpu - ms->possible_cpus->cpus;
1811 }
1812 return found_cpu;
1813}
1814
1815static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1816 DeviceState *dev, Error **errp)
1817{
1818 CPUArchId *found_cpu;
1819 HotplugHandlerClass *hhc;
1820 Error *local_err = NULL;
1821 X86CPU *cpu = X86_CPU(dev);
1822 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1823
1824 if (pcms->acpi_dev) {
1825 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1826 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1827 if (local_err) {
1828 goto out;
1829 }
1830 }
1831
1832
1833 pcms->boot_cpus++;
1834 if (pcms->rtc) {
1835 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1836 }
1837 if (pcms->fw_cfg) {
1838 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1839 }
1840
1841 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1842 found_cpu->cpu = OBJECT(dev);
1843out:
1844 error_propagate(errp, local_err);
1845}
1846static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1847 DeviceState *dev, Error **errp)
1848{
1849 int idx = -1;
1850 HotplugHandlerClass *hhc;
1851 Error *local_err = NULL;
1852 X86CPU *cpu = X86_CPU(dev);
1853 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1854
1855 if (!pcms->acpi_dev) {
1856 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1857 goto out;
1858 }
1859
1860 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1861 assert(idx != -1);
1862 if (idx == 0) {
1863 error_setg(&local_err, "Boot CPU is unpluggable");
1864 goto out;
1865 }
1866
1867 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1868 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1869
1870 if (local_err) {
1871 goto out;
1872 }
1873
1874 out:
1875 error_propagate(errp, local_err);
1876
1877}
1878
1879static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1880 DeviceState *dev, Error **errp)
1881{
1882 CPUArchId *found_cpu;
1883 HotplugHandlerClass *hhc;
1884 Error *local_err = NULL;
1885 X86CPU *cpu = X86_CPU(dev);
1886 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1887
1888 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1889 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1890
1891 if (local_err) {
1892 goto out;
1893 }
1894
1895 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1896 found_cpu->cpu = NULL;
1897 object_unparent(OBJECT(dev));
1898
1899
1900 pcms->boot_cpus--;
1901
1902 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1903 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1904 out:
1905 error_propagate(errp, local_err);
1906}
1907
1908static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1909 DeviceState *dev, Error **errp)
1910{
1911 int idx;
1912 CPUState *cs;
1913 CPUArchId *cpu_slot;
1914 X86CPUTopoInfo topo;
1915 X86CPU *cpu = X86_CPU(dev);
1916 MachineState *ms = MACHINE(hotplug_dev);
1917 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1918
1919 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1920 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1921 ms->cpu_type);
1922 return;
1923 }
1924
1925
1926 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1927 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1928
1929 if (cpu->socket_id < 0) {
1930 error_setg(errp, "CPU socket-id is not set");
1931 return;
1932 } else if (cpu->socket_id > max_socket) {
1933 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1934 cpu->socket_id, max_socket);
1935 return;
1936 }
1937 if (cpu->core_id < 0) {
1938 error_setg(errp, "CPU core-id is not set");
1939 return;
1940 } else if (cpu->core_id > (smp_cores - 1)) {
1941 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1942 cpu->core_id, smp_cores - 1);
1943 return;
1944 }
1945 if (cpu->thread_id < 0) {
1946 error_setg(errp, "CPU thread-id is not set");
1947 return;
1948 } else if (cpu->thread_id > (smp_threads - 1)) {
1949 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1950 cpu->thread_id, smp_threads - 1);
1951 return;
1952 }
1953
1954 topo.pkg_id = cpu->socket_id;
1955 topo.core_id = cpu->core_id;
1956 topo.smt_id = cpu->thread_id;
1957 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
1958 }
1959
1960 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1961 if (!cpu_slot) {
1962 MachineState *ms = MACHINE(pcms);
1963
1964 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1965 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1966 " APIC ID %" PRIu32 ", valid index range 0:%d",
1967 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
1968 ms->possible_cpus->len - 1);
1969 return;
1970 }
1971
1972 if (cpu_slot->cpu) {
1973 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1974 idx, cpu->apic_id);
1975 return;
1976 }
1977
1978
1979
1980
1981
1982
1983
1984 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1985 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1986 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1987 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1988 return;
1989 }
1990 cpu->socket_id = topo.pkg_id;
1991
1992 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1993 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1994 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1995 return;
1996 }
1997 cpu->core_id = topo.core_id;
1998
1999 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2000 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2001 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2002 return;
2003 }
2004 cpu->thread_id = topo.smt_id;
2005
2006 cs = CPU(cpu);
2007 cs->cpu_index = idx;
2008
2009 numa_cpu_pre_plug(cpu_slot, dev, errp);
2010}
2011
2012static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2013 DeviceState *dev, Error **errp)
2014{
2015 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2016 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2017 }
2018}
2019
2020static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2021 DeviceState *dev, Error **errp)
2022{
2023 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2024 pc_dimm_plug(hotplug_dev, dev, errp);
2025 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2026 pc_cpu_plug(hotplug_dev, dev, errp);
2027 }
2028}
2029
2030static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2031 DeviceState *dev, Error **errp)
2032{
2033 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2034 pc_dimm_unplug_request(hotplug_dev, dev, errp);
2035 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2036 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2037 } else {
2038 error_setg(errp, "acpi: device unplug request for not supported device"
2039 " type: %s", object_get_typename(OBJECT(dev)));
2040 }
2041}
2042
2043static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2044 DeviceState *dev, Error **errp)
2045{
2046 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2047 pc_dimm_unplug(hotplug_dev, dev, errp);
2048 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2049 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2050 } else {
2051 error_setg(errp, "acpi: device unplug for not supported device"
2052 " type: %s", object_get_typename(OBJECT(dev)));
2053 }
2054}
2055
2056static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2057 DeviceState *dev)
2058{
2059 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
2060
2061 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2062 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2063 return HOTPLUG_HANDLER(machine);
2064 }
2065
2066 return pcmc->get_hotplug_handler ?
2067 pcmc->get_hotplug_handler(machine, dev) : NULL;
2068}
2069
2070static void
2071pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v,
2072 const char *name, void *opaque,
2073 Error **errp)
2074{
2075 PCMachineState *pcms = PC_MACHINE(obj);
2076 int64_t value = memory_region_size(&pcms->hotplug_memory.mr);
2077
2078 visit_type_int(v, name, &value, errp);
2079}
2080
2081static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2082 const char *name, void *opaque,
2083 Error **errp)
2084{
2085 PCMachineState *pcms = PC_MACHINE(obj);
2086 uint64_t value = pcms->max_ram_below_4g;
2087
2088 visit_type_size(v, name, &value, errp);
2089}
2090
2091static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2092 const char *name, void *opaque,
2093 Error **errp)
2094{
2095 PCMachineState *pcms = PC_MACHINE(obj);
2096 Error *error = NULL;
2097 uint64_t value;
2098
2099 visit_type_size(v, name, &value, &error);
2100 if (error) {
2101 error_propagate(errp, error);
2102 return;
2103 }
2104 if (value > (1ULL << 32)) {
2105 error_setg(&error,
2106 "Machine option 'max-ram-below-4g=%"PRIu64
2107 "' expects size less than or equal to 4G", value);
2108 error_propagate(errp, error);
2109 return;
2110 }
2111
2112 if (value < (1ULL << 20)) {
2113 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2114 "BIOS may not work with less than 1MiB", value);
2115 }
2116
2117 pcms->max_ram_below_4g = value;
2118}
2119
2120static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2121 void *opaque, Error **errp)
2122{
2123 PCMachineState *pcms = PC_MACHINE(obj);
2124 OnOffAuto vmport = pcms->vmport;
2125
2126 visit_type_OnOffAuto(v, name, &vmport, errp);
2127}
2128
2129static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2130 void *opaque, Error **errp)
2131{
2132 PCMachineState *pcms = PC_MACHINE(obj);
2133
2134 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2135}
2136
2137bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2138{
2139 bool smm_available = false;
2140
2141 if (pcms->smm == ON_OFF_AUTO_OFF) {
2142 return false;
2143 }
2144
2145 if (tcg_enabled() || qtest_enabled()) {
2146 smm_available = true;
2147 } else if (kvm_enabled()) {
2148 smm_available = kvm_has_smm();
2149 }
2150
2151 if (smm_available) {
2152 return true;
2153 }
2154
2155 if (pcms->smm == ON_OFF_AUTO_ON) {
2156 error_report("System Management Mode not supported by this hypervisor.");
2157 exit(1);
2158 }
2159 return false;
2160}
2161
2162static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2163 void *opaque, Error **errp)
2164{
2165 PCMachineState *pcms = PC_MACHINE(obj);
2166 OnOffAuto smm = pcms->smm;
2167
2168 visit_type_OnOffAuto(v, name, &smm, errp);
2169}
2170
2171static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2172 void *opaque, Error **errp)
2173{
2174 PCMachineState *pcms = PC_MACHINE(obj);
2175
2176 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2177}
2178
2179static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2180{
2181 PCMachineState *pcms = PC_MACHINE(obj);
2182
2183 return pcms->acpi_nvdimm_state.is_enabled;
2184}
2185
2186static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2187{
2188 PCMachineState *pcms = PC_MACHINE(obj);
2189
2190 pcms->acpi_nvdimm_state.is_enabled = value;
2191}
2192
2193static bool pc_machine_get_smbus(Object *obj, Error **errp)
2194{
2195 PCMachineState *pcms = PC_MACHINE(obj);
2196
2197 return pcms->smbus;
2198}
2199
2200static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2201{
2202 PCMachineState *pcms = PC_MACHINE(obj);
2203
2204 pcms->smbus = value;
2205}
2206
2207static bool pc_machine_get_sata(Object *obj, Error **errp)
2208{
2209 PCMachineState *pcms = PC_MACHINE(obj);
2210
2211 return pcms->sata;
2212}
2213
2214static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2215{
2216 PCMachineState *pcms = PC_MACHINE(obj);
2217
2218 pcms->sata = value;
2219}
2220
2221static bool pc_machine_get_pit(Object *obj, Error **errp)
2222{
2223 PCMachineState *pcms = PC_MACHINE(obj);
2224
2225 return pcms->pit;
2226}
2227
2228static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2229{
2230 PCMachineState *pcms = PC_MACHINE(obj);
2231
2232 pcms->pit = value;
2233}
2234
2235static void pc_machine_initfn(Object *obj)
2236{
2237 PCMachineState *pcms = PC_MACHINE(obj);
2238
2239 pcms->max_ram_below_4g = 0;
2240 pcms->smm = ON_OFF_AUTO_AUTO;
2241 pcms->vmport = ON_OFF_AUTO_AUTO;
2242
2243 pcms->acpi_nvdimm_state.is_enabled = false;
2244
2245 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2246 pcms->smbus = true;
2247 pcms->sata = true;
2248 pcms->pit = true;
2249}
2250
2251static void pc_machine_reset(void)
2252{
2253 CPUState *cs;
2254 X86CPU *cpu;
2255
2256 qemu_devices_reset();
2257
2258
2259
2260
2261 CPU_FOREACH(cs) {
2262 cpu = X86_CPU(cs);
2263
2264 if (cpu->apic_state) {
2265 device_reset(cpu->apic_state);
2266 }
2267 }
2268}
2269
2270static CpuInstanceProperties
2271pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2272{
2273 MachineClass *mc = MACHINE_GET_CLASS(ms);
2274 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2275
2276 assert(cpu_index < possible_cpus->len);
2277 return possible_cpus->cpus[cpu_index].props;
2278}
2279
2280static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2281{
2282 X86CPUTopoInfo topo;
2283
2284 assert(idx < ms->possible_cpus->len);
2285 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2286 smp_cores, smp_threads, &topo);
2287 return topo.pkg_id % nb_numa_nodes;
2288}
2289
2290static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2291{
2292 int i;
2293
2294 if (ms->possible_cpus) {
2295
2296
2297
2298
2299 assert(ms->possible_cpus->len == max_cpus);
2300 return ms->possible_cpus;
2301 }
2302
2303 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2304 sizeof(CPUArchId) * max_cpus);
2305 ms->possible_cpus->len = max_cpus;
2306 for (i = 0; i < ms->possible_cpus->len; i++) {
2307 X86CPUTopoInfo topo;
2308
2309 ms->possible_cpus->cpus[i].type = ms->cpu_type;
2310 ms->possible_cpus->cpus[i].vcpus_count = 1;
2311 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2312 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2313 smp_cores, smp_threads, &topo);
2314 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2315 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2316 ms->possible_cpus->cpus[i].props.has_core_id = true;
2317 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2318 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2319 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2320 }
2321 return ms->possible_cpus;
2322}
2323
2324static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2325{
2326
2327 CPUState *cs;
2328
2329 CPU_FOREACH(cs) {
2330 X86CPU *cpu = X86_CPU(cs);
2331
2332 if (!cpu->apic_state) {
2333 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2334 } else {
2335 apic_deliver_nmi(cpu->apic_state);
2336 }
2337 }
2338}
2339
2340static void pc_machine_class_init(ObjectClass *oc, void *data)
2341{
2342 MachineClass *mc = MACHINE_CLASS(oc);
2343 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2344 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2345 NMIClass *nc = NMI_CLASS(oc);
2346
2347 pcmc->get_hotplug_handler = mc->get_hotplug_handler;
2348 pcmc->pci_enabled = true;
2349 pcmc->has_acpi_build = true;
2350 pcmc->rsdp_in_ram = true;
2351 pcmc->smbios_defaults = true;
2352 pcmc->smbios_uuid_encoded = true;
2353 pcmc->gigabyte_align = true;
2354 pcmc->has_reserved_memory = true;
2355 pcmc->kvmclock_enabled = true;
2356 pcmc->enforce_aligned_dimm = true;
2357
2358
2359 pcmc->acpi_data_size = 0x20000 + 0x8000;
2360 pcmc->save_tsc_khz = true;
2361 pcmc->linuxboot_dma_enabled = true;
2362 mc->get_hotplug_handler = pc_get_hotpug_handler;
2363 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2364 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2365 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2366 mc->auto_enable_numa_with_memhp = true;
2367 mc->has_hotpluggable_cpus = true;
2368 mc->default_boot_order = "cad";
2369 mc->hot_add_cpu = pc_hot_add_cpu;
2370 mc->block_default_type = IF_IDE;
2371 mc->max_cpus = 255;
2372 mc->reset = pc_machine_reset;
2373 hc->pre_plug = pc_machine_device_pre_plug_cb;
2374 hc->plug = pc_machine_device_plug_cb;
2375 hc->unplug_request = pc_machine_device_unplug_request_cb;
2376 hc->unplug = pc_machine_device_unplug_cb;
2377 nc->nmi_monitor_handler = x86_nmi;
2378 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2379
2380 object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int",
2381 pc_machine_get_hotplug_memory_region_size, NULL,
2382 NULL, NULL, &error_abort);
2383
2384 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2385 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2386 NULL, NULL, &error_abort);
2387
2388 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2389 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2390
2391 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2392 pc_machine_get_smm, pc_machine_set_smm,
2393 NULL, NULL, &error_abort);
2394 object_class_property_set_description(oc, PC_MACHINE_SMM,
2395 "Enable SMM (pc & q35)", &error_abort);
2396
2397 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2398 pc_machine_get_vmport, pc_machine_set_vmport,
2399 NULL, NULL, &error_abort);
2400 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2401 "Enable vmport (pc & q35)", &error_abort);
2402
2403 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2404 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2405
2406 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2407 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2408
2409 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2410 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2411
2412 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2413 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2414}
2415
2416static const TypeInfo pc_machine_info = {
2417 .name = TYPE_PC_MACHINE,
2418 .parent = TYPE_MACHINE,
2419 .abstract = true,
2420 .instance_size = sizeof(PCMachineState),
2421 .instance_init = pc_machine_initfn,
2422 .class_size = sizeof(PCMachineClass),
2423 .class_init = pc_machine_class_init,
2424 .interfaces = (InterfaceInfo[]) {
2425 { TYPE_HOTPLUG_HANDLER },
2426 { TYPE_NMI },
2427 { }
2428 },
2429};
2430
2431static void pc_machine_register_types(void)
2432{
2433 type_register_static(&pc_machine_info);
2434}
2435
2436type_init(pc_machine_register_types)
2437