1
2
3
4
5
6
7
8
9
10
11
12#include "qemu/osdep.h"
13#include "qemu/error-report.h"
14#include "qapi/error.h"
15#include "sysemu/sysemu.h"
16#include "sysemu/block-backend.h"
17#include "sysemu/blockdev.h"
18#include "chardev/char.h"
19#include "hw/isa/superio.h"
20#include "hw/input/i8042.h"
21#include "hw/char/serial.h"
22#include "trace.h"
23
24static void isa_superio_realize(DeviceState *dev, Error **errp)
25{
26 ISASuperIODevice *sio = ISA_SUPERIO(dev);
27 ISASuperIOClass *k = ISA_SUPERIO_GET_CLASS(sio);
28 ISABus *bus = isa_bus_from_device(ISA_DEVICE(dev));
29 ISADevice *isa;
30 DeviceState *d;
31 Chardev *chr;
32 DriveInfo *drive;
33 char *name;
34 int i;
35
36
37 for (i = 0; i < k->parallel.count; i++) {
38 if (i >= ARRAY_SIZE(sio->parallel)) {
39 warn_report("superio: ignoring %td parallel controllers",
40 k->parallel.count - ARRAY_SIZE(sio->parallel));
41 break;
42 }
43 if (!k->parallel.is_enabled || k->parallel.is_enabled(sio, i)) {
44
45 chr = parallel_hds[i];
46 if (chr == NULL) {
47 name = g_strdup_printf("discarding-parallel%d", i);
48 chr = qemu_chr_new(name, "null");
49 } else {
50 name = g_strdup_printf("parallel%d", i);
51 }
52 isa = isa_create(bus, "isa-parallel");
53 d = DEVICE(isa);
54 qdev_prop_set_uint32(d, "index", i);
55 if (k->parallel.get_iobase) {
56 qdev_prop_set_uint32(d, "iobase",
57 k->parallel.get_iobase(sio, i));
58 }
59 if (k->parallel.get_irq) {
60 qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i));
61 }
62 qdev_prop_set_chr(d, "chardev", chr);
63 qdev_init_nofail(d);
64 sio->parallel[i] = isa;
65 trace_superio_create_parallel(i,
66 k->parallel.get_iobase ?
67 k->parallel.get_iobase(sio, i) : -1,
68 k->parallel.get_irq ?
69 k->parallel.get_irq(sio, i) : -1);
70 object_property_add_child(OBJECT(dev), name,
71 OBJECT(sio->parallel[i]), NULL);
72 g_free(name);
73 }
74 }
75
76
77 for (i = 0; i < k->serial.count; i++) {
78 if (i >= ARRAY_SIZE(sio->serial)) {
79 warn_report("superio: ignoring %td serial controllers",
80 k->serial.count - ARRAY_SIZE(sio->serial));
81 break;
82 }
83 if (!k->serial.is_enabled || k->serial.is_enabled(sio, i)) {
84
85 chr = serial_hds[i];
86 if (chr == NULL) {
87 name = g_strdup_printf("discarding-serial%d", i);
88 chr = qemu_chr_new(name, "null");
89 } else {
90 name = g_strdup_printf("serial%d", i);
91 }
92 isa = isa_create(bus, TYPE_ISA_SERIAL);
93 d = DEVICE(isa);
94 qdev_prop_set_uint32(d, "index", i);
95 if (k->serial.get_iobase) {
96 qdev_prop_set_uint32(d, "iobase",
97 k->serial.get_iobase(sio, i));
98 }
99 if (k->serial.get_irq) {
100 qdev_prop_set_uint32(d, "irq", k->serial.get_irq(sio, i));
101 }
102 qdev_prop_set_chr(d, "chardev", chr);
103 qdev_init_nofail(d);
104 sio->serial[i] = isa;
105 trace_superio_create_serial(i,
106 k->serial.get_iobase ?
107 k->serial.get_iobase(sio, i) : -1,
108 k->serial.get_irq ?
109 k->serial.get_irq(sio, i) : -1);
110 object_property_add_child(OBJECT(dev), name,
111 OBJECT(sio->serial[0]), NULL);
112 g_free(name);
113 }
114 }
115
116
117 if (!k->floppy.is_enabled || k->floppy.is_enabled(sio, 0)) {
118 isa = isa_create(bus, "isa-fdc");
119 d = DEVICE(isa);
120 if (k->floppy.get_iobase) {
121 qdev_prop_set_uint32(d, "iobase", k->floppy.get_iobase(sio, 0));
122 }
123 if (k->floppy.get_irq) {
124 qdev_prop_set_uint32(d, "irq", k->floppy.get_irq(sio, 0));
125 }
126
127 drive = drive_get(IF_FLOPPY, 0, 0);
128 if (drive != NULL) {
129 qdev_prop_set_drive(d, "driveA", blk_by_legacy_dinfo(drive),
130 &error_fatal);
131 }
132
133 drive = drive_get(IF_FLOPPY, 0, 1);
134 if (drive != NULL) {
135 qdev_prop_set_drive(d, "driveB", blk_by_legacy_dinfo(drive),
136 &error_fatal);
137 }
138 qdev_init_nofail(d);
139 sio->floppy = isa;
140 trace_superio_create_floppy(0,
141 k->floppy.get_iobase ?
142 k->floppy.get_iobase(sio, 0) : -1,
143 k->floppy.get_irq ?
144 k->floppy.get_irq(sio, 0) : -1);
145 }
146
147
148 sio->kbc = isa_create_simple(bus, TYPE_I8042);
149
150
151 if (k->ide.count && (!k->ide.is_enabled || k->ide.is_enabled(sio, 0))) {
152 isa = isa_create(bus, "isa-ide");
153 d = DEVICE(isa);
154 if (k->ide.get_iobase) {
155 qdev_prop_set_uint32(d, "iobase", k->ide.get_iobase(sio, 0));
156 }
157 if (k->ide.get_iobase) {
158 qdev_prop_set_uint32(d, "iobase2", k->ide.get_iobase(sio, 1));
159 }
160 if (k->ide.get_irq) {
161 qdev_prop_set_uint32(d, "irq", k->ide.get_irq(sio, 0));
162 }
163 qdev_init_nofail(d);
164 sio->ide = isa;
165 trace_superio_create_ide(0,
166 k->ide.get_iobase ?
167 k->ide.get_iobase(sio, 0) : -1,
168 k->ide.get_irq ?
169 k->ide.get_irq(sio, 0) : -1);
170 }
171}
172
173static void isa_superio_class_init(ObjectClass *oc, void *data)
174{
175 DeviceClass *dc = DEVICE_CLASS(oc);
176
177 dc->realize = isa_superio_realize;
178
179 dc->user_creatable = false;
180}
181
182static const TypeInfo isa_superio_type_info = {
183 .name = TYPE_ISA_SUPERIO,
184 .parent = TYPE_ISA_DEVICE,
185 .abstract = true,
186 .class_size = sizeof(ISASuperIOClass),
187 .class_init = isa_superio_class_init,
188};
189
190
191static void fdc37m81x_class_init(ObjectClass *klass, void *data)
192{
193 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
194
195 sc->serial.count = 2;
196 sc->parallel.count = 1;
197 sc->floppy.count = 1;
198 sc->ide.count = 0;
199}
200
201static const TypeInfo fdc37m81x_type_info = {
202 .name = TYPE_FDC37M81X_SUPERIO,
203 .parent = TYPE_ISA_SUPERIO,
204 .instance_size = sizeof(ISASuperIODevice),
205 .class_init = fdc37m81x_class_init,
206};
207
208static void isa_superio_register_types(void)
209{
210 type_register_static(&isa_superio_type_info);
211 type_register_static(&fdc37m81x_type_info);
212}
213
214type_init(isa_superio_register_types)
215
