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25#include "qemu/osdep.h"
26#include "qemu-common.h"
27#include "cpu.h"
28#include "hw/hw.h"
29#include "hw/i386/pc.h"
30#include "hw/isa/superio.h"
31#include "hw/dma/i8257.h"
32#include "hw/char/serial.h"
33#include "net/net.h"
34#include "hw/boards.h"
35#include "hw/i2c/smbus.h"
36#include "hw/block/flash.h"
37#include "hw/mips/mips.h"
38#include "hw/mips/cpudevs.h"
39#include "hw/pci/pci.h"
40#include "sysemu/sysemu.h"
41#include "sysemu/arch_init.h"
42#include "qemu/log.h"
43#include "hw/mips/bios.h"
44#include "hw/ide.h"
45#include "hw/loader.h"
46#include "elf.h"
47#include "hw/timer/mc146818rtc.h"
48#include "hw/timer/i8254.h"
49#include "sysemu/blockdev.h"
50#include "exec/address-spaces.h"
51#include "hw/sysbus.h"
52#include "qemu/host-utils.h"
53#include "sysemu/qtest.h"
54#include "qapi/error.h"
55#include "qemu/error-report.h"
56#include "hw/empty_slot.h"
57#include "sysemu/kvm.h"
58#include "exec/semihost.h"
59#include "hw/mips/cps.h"
60
61
62
63#define ENVP_ADDR 0x80002000l
64#define ENVP_NB_ENTRIES 16
65#define ENVP_ENTRY_SIZE 256
66
67
68#define FLASH_ADDRESS 0x1e000000ULL
69#define FPGA_ADDRESS 0x1f000000ULL
70#define RESET_ADDRESS 0x1fc00000ULL
71
72#define FLASH_SIZE 0x400000
73
74#define MAX_IDE_BUS 2
75
76typedef struct {
77 MemoryRegion iomem;
78 MemoryRegion iomem_lo;
79 MemoryRegion iomem_hi;
80 uint32_t leds;
81 uint32_t brk;
82 uint32_t gpout;
83 uint32_t i2cin;
84 uint32_t i2coe;
85 uint32_t i2cout;
86 uint32_t i2csel;
87 CharBackend display;
88 char display_text[9];
89 SerialState *uart;
90 bool display_inited;
91} MaltaFPGAState;
92
93#define TYPE_MIPS_MALTA "mips-malta"
94#define MIPS_MALTA(obj) OBJECT_CHECK(MaltaState, (obj), TYPE_MIPS_MALTA)
95
96typedef struct {
97 SysBusDevice parent_obj;
98
99 MIPSCPSState *cps;
100 qemu_irq *i8259;
101} MaltaState;
102
103static ISADevice *pit;
104
105static struct _loaderparams {
106 int ram_size, ram_low_size;
107 const char *kernel_filename;
108 const char *kernel_cmdline;
109 const char *initrd_filename;
110} loaderparams;
111
112
113static void malta_fpga_update_display(void *opaque)
114{
115 char leds_text[9];
116 int i;
117 MaltaFPGAState *s = opaque;
118
119 for (i = 7 ; i >= 0 ; i--) {
120 if (s->leds & (1 << i))
121 leds_text[i] = '#';
122 else
123 leds_text[i] = ' ';
124 }
125 leds_text[8] = '\0';
126
127 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
128 leds_text);
129 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
130 s->display_text);
131}
132
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142
143
144
145#if defined(DEBUG)
146# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
147#else
148# define logout(fmt, ...) ((void)0)
149#endif
150
151struct _eeprom24c0x_t {
152 uint8_t tick;
153 uint8_t address;
154 uint8_t command;
155 uint8_t ack;
156 uint8_t scl;
157 uint8_t sda;
158 uint8_t data;
159
160 uint8_t contents[256];
161};
162
163typedef struct _eeprom24c0x_t eeprom24c0x_t;
164
165static eeprom24c0x_t spd_eeprom = {
166 .contents = {
167 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
168 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
169 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
170 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
171 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
172 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
173 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
174 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
175 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
176 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
177 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
178 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
179 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
180 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
181 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
182 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
183 },
184};
185
186static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
187{
188 enum { SDR = 0x4, DDR2 = 0x8 } type;
189 uint8_t *spd = spd_eeprom.contents;
190 uint8_t nbanks = 0;
191 uint16_t density = 0;
192 int i;
193
194
195 ram_size >>= 20;
196
197 while ((ram_size >= 4) && (nbanks <= 2)) {
198 int sz_log2 = MIN(31 - clz32(ram_size), 14);
199 nbanks++;
200 density |= 1 << (sz_log2 - 2);
201 ram_size -= 1 << sz_log2;
202 }
203
204
205 if ((nbanks == 1) && (density > 1)) {
206 nbanks++;
207 density >>= 1;
208 }
209
210 if (density & 0xff00) {
211 density = (density & 0xe0) | ((density >> 8) & 0x1f);
212 type = DDR2;
213 } else if (!(density & 0x1f)) {
214 type = DDR2;
215 } else {
216 type = SDR;
217 }
218
219 if (ram_size) {
220 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
221 " of SDRAM", ram_size);
222 }
223
224
225 spd[2] = type;
226 spd[5] = nbanks;
227 spd[31] = density;
228
229
230 spd[63] = 0;
231 for (i = 0; i < 63; i++) {
232 spd[63] += spd[i];
233 }
234
235
236 memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
237}
238
239static void generate_eeprom_serial(uint8_t *eeprom)
240{
241 int i, pos = 0;
242 uint8_t mac[6] = { 0x00 };
243 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
244
245
246 eeprom[pos++] = 0x01;
247
248
249 eeprom[pos++] = 0x02;
250
251
252 eeprom[pos++] = 0x01;
253 eeprom[pos++] = 0x06;
254 memcpy(&eeprom[pos], mac, sizeof(mac));
255 pos += sizeof(mac);
256
257
258 eeprom[pos++] = 0x02;
259 eeprom[pos++] = 0x05;
260 memcpy(&eeprom[pos], sn, sizeof(sn));
261 pos += sizeof(sn);
262
263
264 eeprom[pos] = 0;
265 for (i = 0; i < pos; i++) {
266 eeprom[pos] += eeprom[i];
267 }
268}
269
270static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
271{
272 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
273 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
274 return eeprom->sda;
275}
276
277static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
278{
279 if (eeprom->scl && scl && (eeprom->sda != sda)) {
280 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
281 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
282 sda ? "stop" : "start");
283 if (!sda) {
284 eeprom->tick = 1;
285 eeprom->command = 0;
286 }
287 } else if (eeprom->tick == 0 && !eeprom->ack) {
288
289 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
290 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
291 } else if (!eeprom->scl && scl) {
292 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
293 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
294 if (eeprom->ack) {
295 logout("\ti2c ack bit = 0\n");
296 sda = 0;
297 eeprom->ack = 0;
298 } else if (eeprom->sda == sda) {
299 uint8_t bit = (sda != 0);
300 logout("\ti2c bit = %d\n", bit);
301 if (eeprom->tick < 9) {
302 eeprom->command <<= 1;
303 eeprom->command += bit;
304 eeprom->tick++;
305 if (eeprom->tick == 9) {
306 logout("\tcommand 0x%04x, %s\n", eeprom->command,
307 bit ? "read" : "write");
308 eeprom->ack = 1;
309 }
310 } else if (eeprom->tick < 17) {
311 if (eeprom->command & 1) {
312 sda = ((eeprom->data & 0x80) != 0);
313 }
314 eeprom->address <<= 1;
315 eeprom->address += bit;
316 eeprom->tick++;
317 eeprom->data <<= 1;
318 if (eeprom->tick == 17) {
319 eeprom->data = eeprom->contents[eeprom->address];
320 logout("\taddress 0x%04x, data 0x%02x\n",
321 eeprom->address, eeprom->data);
322 eeprom->ack = 1;
323 eeprom->tick = 0;
324 }
325 } else if (eeprom->tick >= 17) {
326 sda = 0;
327 }
328 } else {
329 logout("\tsda changed with raising scl\n");
330 }
331 } else {
332 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
333 scl, eeprom->sda, sda);
334 }
335 eeprom->scl = scl;
336 eeprom->sda = sda;
337}
338
339static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
340 unsigned size)
341{
342 MaltaFPGAState *s = opaque;
343 uint32_t val = 0;
344 uint32_t saddr;
345
346 saddr = (addr & 0xfffff);
347
348 switch (saddr) {
349
350
351 case 0x00200:
352 val = 0x00000000;
353 break;
354
355
356 case 0x00208:
357#ifdef TARGET_WORDS_BIGENDIAN
358 val = 0x00000012;
359#else
360 val = 0x00000010;
361#endif
362 break;
363
364
365 case 0x00210:
366 val = 0x00;
367 break;
368
369
370 case 0x00408:
371 val = s->leds;
372 break;
373
374
375 case 0x00508:
376 val = s->brk;
377 break;
378
379
380
381
382 case 0x00a00:
383 val = s->gpout;
384 break;
385
386
387
388
389 case 0x00a08:
390
391 if (s->i2csel)
392 val = s->i2cout;
393 else
394 val = 0x00;
395 break;
396
397
398 case 0x00b00:
399 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
400 break;
401
402
403 case 0x00b08:
404 val = s->i2coe;
405 break;
406
407
408 case 0x00b10:
409 val = s->i2cout;
410 break;
411
412
413 case 0x00b18:
414 val = s->i2csel;
415 break;
416
417 default:
418#if 0
419 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
420 addr);
421#endif
422 break;
423 }
424 return val;
425}
426
427static void malta_fpga_write(void *opaque, hwaddr addr,
428 uint64_t val, unsigned size)
429{
430 MaltaFPGAState *s = opaque;
431 uint32_t saddr;
432
433 saddr = (addr & 0xfffff);
434
435 switch (saddr) {
436
437
438 case 0x00200:
439 break;
440
441
442 case 0x00210:
443 break;
444
445
446 case 0x00408:
447 s->leds = val & 0xff;
448 malta_fpga_update_display(s);
449 break;
450
451
452 case 0x00410:
453 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
454 malta_fpga_update_display(s);
455 break;
456
457
458 case 0x00418:
459 case 0x00420:
460 case 0x00428:
461 case 0x00430:
462 case 0x00438:
463 case 0x00440:
464 case 0x00448:
465 case 0x00450:
466 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
467 malta_fpga_update_display(s);
468 break;
469
470
471 case 0x00500:
472 if (val == 0x42)
473 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
474 break;
475
476
477 case 0x00508:
478 s->brk = val & 0xff;
479 break;
480
481
482
483
484 case 0x00a00:
485 s->gpout = val & 0xff;
486 break;
487
488
489 case 0x00b08:
490 s->i2coe = val & 0x03;
491 break;
492
493
494 case 0x00b10:
495 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
496 s->i2cout = val;
497 break;
498
499
500 case 0x00b18:
501 s->i2csel = val & 0x01;
502 break;
503
504 default:
505#if 0
506 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
507 addr);
508#endif
509 break;
510 }
511}
512
513static const MemoryRegionOps malta_fpga_ops = {
514 .read = malta_fpga_read,
515 .write = malta_fpga_write,
516 .endianness = DEVICE_NATIVE_ENDIAN,
517};
518
519static void malta_fpga_reset(void *opaque)
520{
521 MaltaFPGAState *s = opaque;
522
523 s->leds = 0x00;
524 s->brk = 0x0a;
525 s->gpout = 0x00;
526 s->i2cin = 0x3;
527 s->i2coe = 0x0;
528 s->i2cout = 0x3;
529 s->i2csel = 0x1;
530
531 s->display_text[8] = '\0';
532 snprintf(s->display_text, 9, " ");
533}
534
535static void malta_fgpa_display_event(void *opaque, int event)
536{
537 MaltaFPGAState *s = opaque;
538
539 if (event == CHR_EVENT_OPENED && !s->display_inited) {
540 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
541 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
542 qemu_chr_fe_printf(&s->display, "+ +\r\n");
543 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
544 qemu_chr_fe_printf(&s->display, "\n");
545 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
546 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
547 qemu_chr_fe_printf(&s->display, "+ +\r\n");
548 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
549 s->display_inited = true;
550 }
551}
552
553static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
554 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
555{
556 MaltaFPGAState *s;
557 Chardev *chr;
558
559 s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
560
561 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
562 "malta-fpga", 0x100000);
563 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
564 &s->iomem, 0, 0x900);
565 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
566 &s->iomem, 0xa00, 0x10000-0xa00);
567
568 memory_region_add_subregion(address_space, base, &s->iomem_lo);
569 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
570
571 chr = qemu_chr_new("fpga", "vc:320x200");
572 qemu_chr_fe_init(&s->display, chr, NULL);
573 qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
574 malta_fgpa_display_event, NULL, s, NULL, true);
575
576 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
577 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
578
579 malta_fpga_reset(s);
580 qemu_register_reset(malta_fpga_reset, s);
581
582 return s;
583}
584
585
586static void network_init(PCIBus *pci_bus)
587{
588 int i;
589
590 for(i = 0; i < nb_nics; i++) {
591 NICInfo *nd = &nd_table[i];
592 const char *default_devaddr = NULL;
593
594 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
595
596 default_devaddr = "0b";
597
598 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
599 }
600}
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623
624static void write_bootloader(uint8_t *base, int64_t run_addr,
625 int64_t kernel_entry)
626{
627 uint32_t *p;
628
629
630 p = (uint32_t *)base;
631
632 stl_p(p++, 0x08000000 |
633 ((run_addr + 0x580) & 0x0fffffff) >> 2);
634 stl_p(p++, 0x00000000);
635
636
637 stl_p(base + 0x500, run_addr + 0x0580);
638 stl_p(base + 0x504, run_addr + 0x083c);
639 stl_p(base + 0x520, run_addr + 0x0580);
640 stl_p(base + 0x52c, run_addr + 0x0800);
641 stl_p(base + 0x534, run_addr + 0x0808);
642 stl_p(base + 0x538, run_addr + 0x0800);
643 stl_p(base + 0x53c, run_addr + 0x0800);
644 stl_p(base + 0x540, run_addr + 0x0800);
645 stl_p(base + 0x544, run_addr + 0x0800);
646 stl_p(base + 0x548, run_addr + 0x0800);
647 stl_p(base + 0x54c, run_addr + 0x0800);
648 stl_p(base + 0x550, run_addr + 0x0800);
649 stl_p(base + 0x554, run_addr + 0x0800);
650
651
652
653 p = (uint32_t *) (base + 0x580);
654
655 if (semihosting_get_argc()) {
656
657 stl_p(p++, 0x00000000);
658 } else {
659 stl_p(p++, 0x24040002);
660 }
661 stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
662 stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
663 stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
664 stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
665 stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
666 stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
667 stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
668 stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
669
670
671 stl_p(p++, 0x3c09b400);
672
673#ifdef TARGET_WORDS_BIGENDIAN
674 stl_p(p++, 0x3c08df00);
675#else
676 stl_p(p++, 0x340800df);
677#endif
678 stl_p(p++, 0xad280068);
679
680 stl_p(p++, 0x3c09bbe0);
681
682#ifdef TARGET_WORDS_BIGENDIAN
683 stl_p(p++, 0x3c08c000);
684#else
685 stl_p(p++, 0x340800c0);
686#endif
687 stl_p(p++, 0xad280048);
688#ifdef TARGET_WORDS_BIGENDIAN
689 stl_p(p++, 0x3c084000);
690#else
691 stl_p(p++, 0x34080040);
692#endif
693 stl_p(p++, 0xad280050);
694
695#ifdef TARGET_WORDS_BIGENDIAN
696 stl_p(p++, 0x3c088000);
697#else
698 stl_p(p++, 0x34080080);
699#endif
700 stl_p(p++, 0xad280058);
701#ifdef TARGET_WORDS_BIGENDIAN
702 stl_p(p++, 0x3c083f00);
703#else
704 stl_p(p++, 0x3408003f);
705#endif
706 stl_p(p++, 0xad280060);
707
708#ifdef TARGET_WORDS_BIGENDIAN
709 stl_p(p++, 0x3c08c100);
710#else
711 stl_p(p++, 0x340800c1);
712#endif
713 stl_p(p++, 0xad280080);
714#ifdef TARGET_WORDS_BIGENDIAN
715 stl_p(p++, 0x3c085e00);
716#else
717 stl_p(p++, 0x3408005e);
718#endif
719 stl_p(p++, 0xad280088);
720
721
722 stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff));
723 stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff));
724 stl_p(p++, 0x03e00009);
725 stl_p(p++, 0x00000000);
726
727
728 p = (uint32_t *) (base + 0x800);
729 stl_p(p++, 0x03e00009);
730 stl_p(p++, 0x24020000);
731
732 stl_p(p++, 0x03e06821);
733 stl_p(p++, 0x00805821);
734 stl_p(p++, 0x00a05021);
735 stl_p(p++, 0x91440000);
736 stl_p(p++, 0x254a0001);
737 stl_p(p++, 0x10800005);
738 stl_p(p++, 0x00000000);
739 stl_p(p++, 0x0ff0021c);
740 stl_p(p++, 0x00000000);
741 stl_p(p++, 0x1000fff9);
742 stl_p(p++, 0x00000000);
743 stl_p(p++, 0x01a00009);
744 stl_p(p++, 0x01602021);
745
746 stl_p(p++, 0x03e06821);
747 stl_p(p++, 0x00805821);
748 stl_p(p++, 0x00a05021);
749 stl_p(p++, 0x00c06021);
750 stl_p(p++, 0x91440000);
751 stl_p(p++, 0x0ff0021c);
752 stl_p(p++, 0x00000000);
753 stl_p(p++, 0x254a0001);
754 stl_p(p++, 0x258cffff);
755 stl_p(p++, 0x1580fffa);
756 stl_p(p++, 0x00000000);
757 stl_p(p++, 0x01a00009);
758 stl_p(p++, 0x01602021);
759
760 stl_p(p++, 0x3c08b800);
761 stl_p(p++, 0x350803f8);
762 stl_p(p++, 0x91090005);
763 stl_p(p++, 0x00000000);
764 stl_p(p++, 0x31290040);
765 stl_p(p++, 0x1120fffc);
766 stl_p(p++, 0x00000000);
767 stl_p(p++, 0x03e00009);
768 stl_p(p++, 0xa1040000);
769
770}
771
772static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
773 const char *string, ...)
774{
775 va_list ap;
776 int32_t table_addr;
777
778 if (index >= ENVP_NB_ENTRIES)
779 return;
780
781 if (string == NULL) {
782 prom_buf[index] = 0;
783 return;
784 }
785
786 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
787 prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
788
789 va_start(ap, string);
790 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
791 va_end(ap);
792}
793
794
795static int64_t load_kernel (void)
796{
797 int64_t kernel_entry, kernel_high;
798 long kernel_size, initrd_size;
799 ram_addr_t initrd_offset;
800 int big_endian;
801 uint32_t *prom_buf;
802 long prom_size;
803 int prom_index = 0;
804 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
805
806#ifdef TARGET_WORDS_BIGENDIAN
807 big_endian = 1;
808#else
809 big_endian = 0;
810#endif
811
812 kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
813 NULL, (uint64_t *)&kernel_entry, NULL,
814 (uint64_t *)&kernel_high, big_endian, EM_MIPS, 1, 0);
815 if (kernel_size < 0) {
816 error_report("could not load kernel '%s': %s",
817 loaderparams.kernel_filename,
818 load_elf_strerror(kernel_size));
819 exit(1);
820 }
821
822
823 if (kernel_entry & 0x80000000ll) {
824 if (kvm_enabled()) {
825 error_report("KVM guest kernels must be linked in useg. "
826 "Did you forget to enable CONFIG_KVM_GUEST?");
827 exit(1);
828 }
829
830 xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
831 } else {
832
833 mips_um_ksegs_enable();
834
835 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
836 }
837
838
839 initrd_size = 0;
840 initrd_offset = 0;
841 if (loaderparams.initrd_filename) {
842 initrd_size = get_image_size (loaderparams.initrd_filename);
843 if (initrd_size > 0) {
844
845
846
847 initrd_offset = (loaderparams.ram_low_size - initrd_size - 131072
848 - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
849 if (kernel_high >= initrd_offset) {
850 error_report("memory too small for initial ram disk '%s'",
851 loaderparams.initrd_filename);
852 exit(1);
853 }
854 initrd_size = load_image_targphys(loaderparams.initrd_filename,
855 initrd_offset,
856 ram_size - initrd_offset);
857 }
858 if (initrd_size == (target_ulong) -1) {
859 error_report("could not load initial ram disk '%s'",
860 loaderparams.initrd_filename);
861 exit(1);
862 }
863 }
864
865
866 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
867 prom_buf = g_malloc(prom_size);
868
869 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
870 if (initrd_size > 0) {
871 prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
872 xlate_to_kseg0(NULL, initrd_offset), initrd_size,
873 loaderparams.kernel_cmdline);
874 } else {
875 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
876 }
877
878 prom_set(prom_buf, prom_index++, "memsize");
879 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
880
881 prom_set(prom_buf, prom_index++, "ememsize");
882 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
883
884 prom_set(prom_buf, prom_index++, "modetty0");
885 prom_set(prom_buf, prom_index++, "38400n8r");
886 prom_set(prom_buf, prom_index++, NULL);
887
888 rom_add_blob_fixed("prom", prom_buf, prom_size,
889 cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
890
891 g_free(prom_buf);
892 return kernel_entry;
893}
894
895static void malta_mips_config(MIPSCPU *cpu)
896{
897 CPUMIPSState *env = &cpu->env;
898 CPUState *cs = CPU(cpu);
899
900 env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
901 ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC);
902}
903
904static void main_cpu_reset(void *opaque)
905{
906 MIPSCPU *cpu = opaque;
907 CPUMIPSState *env = &cpu->env;
908
909 cpu_reset(CPU(cpu));
910
911
912
913
914 if (loaderparams.kernel_filename) {
915 env->CP0_Status &= ~(1 << CP0St_ERL);
916 }
917
918 malta_mips_config(cpu);
919
920 if (kvm_enabled()) {
921
922 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size;
923 }
924}
925
926static void create_cpu_without_cps(const char *cpu_type,
927 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
928{
929 CPUMIPSState *env;
930 MIPSCPU *cpu;
931 int i;
932
933 for (i = 0; i < smp_cpus; i++) {
934 cpu = MIPS_CPU(cpu_create(cpu_type));
935
936
937 cpu_mips_irq_init_cpu(cpu);
938 cpu_mips_clock_init(cpu);
939 qemu_register_reset(main_cpu_reset, cpu);
940 }
941
942 cpu = MIPS_CPU(first_cpu);
943 env = &cpu->env;
944 *i8259_irq = env->irq[2];
945 *cbus_irq = env->irq[4];
946}
947
948static void create_cps(MaltaState *s, const char *cpu_type,
949 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
950{
951 Error *err = NULL;
952
953 s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
954 qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
955
956 object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
957 object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
958 object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
959 if (err != NULL) {
960 error_report("%s", error_get_pretty(err));
961 exit(1);
962 }
963
964 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
965
966 *i8259_irq = get_cps_irq(s->cps, 3);
967 *cbus_irq = NULL;
968}
969
970static void mips_create_cpu(MaltaState *s, const char *cpu_type,
971 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
972{
973 if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_type)) {
974 create_cps(s, cpu_type, cbus_irq, i8259_irq);
975 } else {
976 create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
977 }
978}
979
980static
981void mips_malta_init(MachineState *machine)
982{
983 ram_addr_t ram_size = machine->ram_size;
984 ram_addr_t ram_low_size;
985 const char *kernel_filename = machine->kernel_filename;
986 const char *kernel_cmdline = machine->kernel_cmdline;
987 const char *initrd_filename = machine->initrd_filename;
988 char *filename;
989 pflash_t *fl;
990 MemoryRegion *system_memory = get_system_memory();
991 MemoryRegion *ram_high = g_new(MemoryRegion, 1);
992 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
993 MemoryRegion *ram_low_postio;
994 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
995 target_long bios_size = FLASH_SIZE;
996 const size_t smbus_eeprom_size = 8 * 256;
997 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
998 int64_t kernel_entry, bootloader_run_addr;
999 PCIBus *pci_bus;
1000 ISABus *isa_bus;
1001 qemu_irq *isa_irq;
1002 qemu_irq cbus_irq, i8259_irq;
1003 int piix4_devfn;
1004 I2CBus *smbus;
1005 DriveInfo *dinfo;
1006 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1007 int fl_idx = 0;
1008 int fl_sectors = bios_size >> 16;
1009 int be;
1010
1011 DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
1012 MaltaState *s = MIPS_MALTA(dev);
1013
1014
1015
1016
1017 empty_slot_init(0, 0x20000000);
1018
1019 qdev_init_nofail(dev);
1020
1021
1022 mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
1023
1024
1025 if (ram_size > (2048u << 20)) {
1026 error_report("Too much memory for this machine: %dMB, maximum 2048MB",
1027 ((unsigned int)ram_size / (1 << 20)));
1028 exit(1);
1029 }
1030
1031
1032 memory_region_allocate_system_memory(ram_high, NULL, "mips_malta.ram",
1033 ram_size);
1034 memory_region_add_subregion(system_memory, 0x80000000, ram_high);
1035
1036
1037 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1038 ram_high, 0, MIN(ram_size, (256 << 20)));
1039 memory_region_add_subregion(system_memory, 0, ram_low_preio);
1040
1041
1042 if (ram_size > (512 << 20)) {
1043 ram_low_postio = g_new(MemoryRegion, 1);
1044 memory_region_init_alias(ram_low_postio, NULL,
1045 "mips_malta_low_postio.ram",
1046 ram_high, 512 << 20,
1047 ram_size - (512 << 20));
1048 memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio);
1049 }
1050
1051#ifdef TARGET_WORDS_BIGENDIAN
1052 be = 1;
1053#else
1054 be = 0;
1055#endif
1056
1057
1058
1059
1060 if (!serial_hds[2]) {
1061 serial_hds[2] = qemu_chr_new("fpga-uart", "null");
1062 }
1063
1064
1065 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]);
1066
1067
1068 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1069#ifdef DEBUG_BOARD_INIT
1070 if (dinfo) {
1071 printf("Register parallel flash %d size " TARGET_FMT_lx " at "
1072 "addr %08llx '%s' %x\n",
1073 fl_idx, bios_size, FLASH_ADDRESS,
1074 blk_name(dinfo->bdrv), fl_sectors);
1075 }
1076#endif
1077 fl = pflash_cfi01_register(FLASH_ADDRESS, NULL, "mips_malta.bios",
1078 BIOS_SIZE,
1079 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1080 65536, fl_sectors,
1081 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
1082 bios = pflash_cfi01_get_memory(fl);
1083 fl_idx++;
1084 if (kernel_filename) {
1085 ram_low_size = MIN(ram_size, 256 << 20);
1086
1087 if (kvm_enabled()) {
1088 ram_low_size -= 0x100000;
1089 bootloader_run_addr = 0x40000000 + ram_low_size;
1090 } else {
1091 bootloader_run_addr = 0xbfc00000;
1092 }
1093
1094
1095 loaderparams.ram_size = ram_size;
1096 loaderparams.ram_low_size = ram_low_size;
1097 loaderparams.kernel_filename = kernel_filename;
1098 loaderparams.kernel_cmdline = kernel_cmdline;
1099 loaderparams.initrd_filename = initrd_filename;
1100 kernel_entry = load_kernel();
1101
1102 write_bootloader(memory_region_get_ram_ptr(bios),
1103 bootloader_run_addr, kernel_entry);
1104 if (kvm_enabled()) {
1105
1106 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
1107 ram_low_size,
1108 bootloader_run_addr, kernel_entry);
1109 }
1110 } else {
1111
1112 if (kvm_enabled()) {
1113 error_report("KVM enabled but no -kernel argument was specified. "
1114 "Booting from flash is not supported with KVM.");
1115 exit(1);
1116 }
1117
1118 if (!dinfo) {
1119
1120 if (bios_name == NULL) {
1121 bios_name = BIOS_FILENAME;
1122 }
1123 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1124 if (filename) {
1125 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1126 BIOS_SIZE);
1127 g_free(filename);
1128 } else {
1129 bios_size = -1;
1130 }
1131 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1132 !kernel_filename && !qtest_enabled()) {
1133 error_report("Could not load MIPS bios '%s', and no "
1134 "-kernel argument was specified", bios_name);
1135 exit(1);
1136 }
1137 }
1138
1139
1140#ifndef TARGET_WORDS_BIGENDIAN
1141 {
1142 uint32_t *end, *addr = rom_ptr(FLASH_ADDRESS);
1143 if (!addr) {
1144 addr = memory_region_get_ram_ptr(bios);
1145 }
1146 end = (void *)addr + MIN(bios_size, 0x3e0000);
1147 while (addr < end) {
1148 bswap32s(addr);
1149 addr++;
1150 }
1151 }
1152#endif
1153 }
1154
1155
1156
1157
1158
1159
1160
1161 memory_region_init_ram_nomigrate(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1162 &error_fatal);
1163 if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1164 FLASH_ADDRESS, BIOS_SIZE)) {
1165 memcpy(memory_region_get_ram_ptr(bios_copy),
1166 memory_region_get_ram_ptr(bios), BIOS_SIZE);
1167 }
1168 memory_region_set_readonly(bios_copy, true);
1169 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1170
1171
1172 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1173
1174
1175
1176
1177
1178
1179
1180
1181 isa_irq = qemu_irq_proxy(&s->i8259, 16);
1182
1183
1184 pci_bus = gt64120_register(isa_irq);
1185
1186
1187 ide_drive_get(hd, ARRAY_SIZE(hd));
1188
1189 piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
1190
1191
1192
1193 s->i8259 = i8259_init(isa_bus, i8259_irq);
1194
1195 isa_bus_irqs(isa_bus, s->i8259);
1196 pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
1197 pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
1198 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
1199 isa_get_irq(NULL, 9), NULL, 0, NULL);
1200 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
1201 i8257_dma_init(isa_bus, 0);
1202 mc146818_rtc_init(isa_bus, 2000, NULL);
1203
1204
1205 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1206 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1207 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1208 g_free(smbus_eeprom_buf);
1209
1210
1211 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
1212
1213
1214 network_init(pci_bus);
1215
1216
1217 pci_vga_init(pci_bus);
1218}
1219
1220static int mips_malta_sysbus_device_init(SysBusDevice *sysbusdev)
1221{
1222 return 0;
1223}
1224
1225static void mips_malta_class_init(ObjectClass *klass, void *data)
1226{
1227 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1228
1229 k->init = mips_malta_sysbus_device_init;
1230}
1231
1232static const TypeInfo mips_malta_device = {
1233 .name = TYPE_MIPS_MALTA,
1234 .parent = TYPE_SYS_BUS_DEVICE,
1235 .instance_size = sizeof(MaltaState),
1236 .class_init = mips_malta_class_init,
1237};
1238
1239static void mips_malta_machine_init(MachineClass *mc)
1240{
1241 mc->desc = "MIPS Malta Core LV";
1242 mc->init = mips_malta_init;
1243 mc->block_default_type = IF_IDE;
1244 mc->max_cpus = 16;
1245 mc->is_default = 1;
1246#ifdef TARGET_MIPS64
1247 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
1248#else
1249 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
1250#endif
1251}
1252
1253DEFINE_MACHINE("malta", mips_malta_machine_init)
1254
1255static void mips_malta_register_types(void)
1256{
1257 type_register_static(&mips_malta_device);
1258}
1259
1260type_init(mips_malta_register_types)
1261