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12#include "qemu/osdep.h"
13#include "qemu/log.h"
14#include "qapi/error.h"
15#include "trace.h"
16#include "hw/sysbus.h"
17#include "hw/registerfields.h"
18#include "hw/misc/tz-ppc.h"
19
20static void tz_ppc_update_irq(TZPPC *s)
21{
22 bool level = s->irq_status && s->irq_enable;
23
24 trace_tz_ppc_update_irq(level);
25 qemu_set_irq(s->irq, level);
26}
27
28static void tz_ppc_cfg_nonsec(void *opaque, int n, int level)
29{
30 TZPPC *s = TZ_PPC(opaque);
31
32 assert(n < TZ_NUM_PORTS);
33 trace_tz_ppc_cfg_nonsec(n, level);
34 s->cfg_nonsec[n] = level;
35}
36
37static void tz_ppc_cfg_ap(void *opaque, int n, int level)
38{
39 TZPPC *s = TZ_PPC(opaque);
40
41 assert(n < TZ_NUM_PORTS);
42 trace_tz_ppc_cfg_ap(n, level);
43 s->cfg_ap[n] = level;
44}
45
46static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level)
47{
48 TZPPC *s = TZ_PPC(opaque);
49
50 trace_tz_ppc_cfg_sec_resp(level);
51 s->cfg_sec_resp = level;
52}
53
54static void tz_ppc_irq_enable(void *opaque, int n, int level)
55{
56 TZPPC *s = TZ_PPC(opaque);
57
58 trace_tz_ppc_irq_enable(level);
59 s->irq_enable = level;
60 tz_ppc_update_irq(s);
61}
62
63static void tz_ppc_irq_clear(void *opaque, int n, int level)
64{
65 TZPPC *s = TZ_PPC(opaque);
66
67 trace_tz_ppc_irq_clear(level);
68
69 s->irq_clear = level;
70 if (level) {
71 s->irq_status = false;
72 tz_ppc_update_irq(s);
73 }
74}
75
76static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs)
77{
78
79
80
81
82
83
84
85
86
87
88 if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) ||
89 (attrs.user && !s->cfg_ap[n])) {
90
91 if (!s->irq_clear) {
92
93 s->irq_status = true;
94 tz_ppc_update_irq(s);
95 }
96 return false;
97 }
98 return true;
99}
100
101static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata,
102 unsigned size, MemTxAttrs attrs)
103{
104 TZPPCPort *p = opaque;
105 TZPPC *s = p->ppc;
106 int n = p - s->port;
107 AddressSpace *as = &p->downstream_as;
108 uint64_t data;
109 MemTxResult res;
110
111 if (!tz_ppc_check(s, n, attrs)) {
112 trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user);
113 if (s->cfg_sec_resp) {
114 return MEMTX_ERROR;
115 } else {
116 *pdata = 0;
117 return MEMTX_OK;
118 }
119 }
120
121 switch (size) {
122 case 1:
123 data = address_space_ldub(as, addr, attrs, &res);
124 break;
125 case 2:
126 data = address_space_lduw_le(as, addr, attrs, &res);
127 break;
128 case 4:
129 data = address_space_ldl_le(as, addr, attrs, &res);
130 break;
131 case 8:
132 data = address_space_ldq_le(as, addr, attrs, &res);
133 break;
134 default:
135 g_assert_not_reached();
136 }
137 *pdata = data;
138 return res;
139}
140
141static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val,
142 unsigned size, MemTxAttrs attrs)
143{
144 TZPPCPort *p = opaque;
145 TZPPC *s = p->ppc;
146 AddressSpace *as = &p->downstream_as;
147 int n = p - s->port;
148 MemTxResult res;
149
150 if (!tz_ppc_check(s, n, attrs)) {
151 trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user);
152 if (s->cfg_sec_resp) {
153 return MEMTX_ERROR;
154 } else {
155 return MEMTX_OK;
156 }
157 }
158
159 switch (size) {
160 case 1:
161 address_space_stb(as, addr, val, attrs, &res);
162 break;
163 case 2:
164 address_space_stw_le(as, addr, val, attrs, &res);
165 break;
166 case 4:
167 address_space_stl_le(as, addr, val, attrs, &res);
168 break;
169 case 8:
170 address_space_stq_le(as, addr, val, attrs, &res);
171 break;
172 default:
173 g_assert_not_reached();
174 }
175 return res;
176}
177
178static const MemoryRegionOps tz_ppc_ops = {
179 .read_with_attrs = tz_ppc_read,
180 .write_with_attrs = tz_ppc_write,
181 .endianness = DEVICE_LITTLE_ENDIAN,
182};
183
184static void tz_ppc_reset(DeviceState *dev)
185{
186 TZPPC *s = TZ_PPC(dev);
187
188 trace_tz_ppc_reset();
189 s->cfg_sec_resp = false;
190 memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec));
191 memset(s->cfg_ap, 0, sizeof(s->cfg_ap));
192}
193
194static void tz_ppc_init(Object *obj)
195{
196 DeviceState *dev = DEVICE(obj);
197 TZPPC *s = TZ_PPC(obj);
198
199 qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS);
200 qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS);
201 qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1);
202 qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1);
203 qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1);
204 qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
205}
206
207static void tz_ppc_realize(DeviceState *dev, Error **errp)
208{
209 Object *obj = OBJECT(dev);
210 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
211 TZPPC *s = TZ_PPC(dev);
212 int i;
213
214
215
216
217 for (i = 0; i < TZ_NUM_PORTS; i++) {
218 TZPPCPort *port = &s->port[i];
219 char *name;
220 uint64_t size;
221
222 if (!port->downstream) {
223 continue;
224 }
225
226 name = g_strdup_printf("tz-ppc-port[%d]", i);
227
228 port->ppc = s;
229 address_space_init(&port->downstream_as, port->downstream, name);
230
231 size = memory_region_size(port->downstream);
232 memory_region_init_io(&port->upstream, obj, &tz_ppc_ops,
233 port, name, size);
234 sysbus_init_mmio(sbd, &port->upstream);
235 g_free(name);
236 }
237}
238
239static const VMStateDescription tz_ppc_vmstate = {
240 .name = "tz-ppc",
241 .version_id = 1,
242 .minimum_version_id = 1,
243 .fields = (VMStateField[]) {
244 VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16),
245 VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16),
246 VMSTATE_BOOL(cfg_sec_resp, TZPPC),
247 VMSTATE_BOOL(irq_enable, TZPPC),
248 VMSTATE_BOOL(irq_clear, TZPPC),
249 VMSTATE_BOOL(irq_status, TZPPC),
250 VMSTATE_END_OF_LIST()
251 }
252};
253
254#define DEFINE_PORT(N) \
255 DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \
256 TYPE_MEMORY_REGION, MemoryRegion *)
257
258static Property tz_ppc_properties[] = {
259 DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0),
260 DEFINE_PORT(0),
261 DEFINE_PORT(1),
262 DEFINE_PORT(2),
263 DEFINE_PORT(3),
264 DEFINE_PORT(4),
265 DEFINE_PORT(5),
266 DEFINE_PORT(6),
267 DEFINE_PORT(7),
268 DEFINE_PORT(8),
269 DEFINE_PORT(9),
270 DEFINE_PORT(10),
271 DEFINE_PORT(11),
272 DEFINE_PORT(12),
273 DEFINE_PORT(13),
274 DEFINE_PORT(14),
275 DEFINE_PORT(15),
276 DEFINE_PROP_END_OF_LIST(),
277};
278
279static void tz_ppc_class_init(ObjectClass *klass, void *data)
280{
281 DeviceClass *dc = DEVICE_CLASS(klass);
282
283 dc->realize = tz_ppc_realize;
284 dc->vmsd = &tz_ppc_vmstate;
285 dc->reset = tz_ppc_reset;
286 dc->props = tz_ppc_properties;
287}
288
289static const TypeInfo tz_ppc_info = {
290 .name = TYPE_TZ_PPC,
291 .parent = TYPE_SYS_BUS_DEVICE,
292 .instance_size = sizeof(TZPPC),
293 .instance_init = tz_ppc_init,
294 .class_init = tz_ppc_class_init,
295};
296
297static void tz_ppc_register_types(void)
298{
299 type_register_static(&tz_ppc_info);
300}
301
302type_init(tz_ppc_register_types);
303
