LXR qemu/hw/net/e1000e

   1/*
   2* Core code for QEMU e1000e emulation
   3*
   4* Software developer's manuals:
   5* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
   6*
   7* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   8* Developed by Daynix Computing LTD (http://www.daynix.com)
   9*
  10* Authors:
  11* Dmitry Fleytman <dmitry@daynix.com>
  12* Leonid Bloch <leonid@daynix.com>
  13* Yan Vugenfirer <yan@daynix.com>
  14*
  15* Based on work done by:
  16* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
  17* Copyright (c) 2008 Qumranet
  18* Based on work done by:
  19* Copyright (c) 2007 Dan Aloni
  20* Copyright (c) 2004 Antony T Curtis
  21*
  22* This library is free software; you can redistribute it and/or
  23* modify it under the terms of the GNU Lesser General Public
  24* License as published by the Free Software Foundation; either
  25* version 2 of the License, or (at your option) any later version.
  26*
  27* This library is distributed in the hope that it will be useful,
  28* but WITHOUT ANY WARRANTY; without even the implied warranty of
  29* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  30* Lesser General Public License for more details.
  31*
  32* You should have received a copy of the GNU Lesser General Public
  33* License along with this library; if not, see <http://www.gnu.org/licenses/>.
  34*/
  35
  36#define E1000E_PHY_PAGE_SIZE    (0x20)
  37#define E1000E_PHY_PAGES        (0x07)
  38#define E1000E_MAC_SIZE         (0x8000)
  39#define E1000E_EEPROM_SIZE      (64)
  40#define E1000E_MSIX_VEC_NUM     (5)
  41#define E1000E_NUM_QUEUES       (2)
  42
  43typedef struct E1000Core E1000ECore;
  44
  45enum { PHY_R = BIT(0),
  46       PHY_W = BIT(1),
  47       PHY_RW = PHY_R | PHY_W,
  48       PHY_ANYPAGE = BIT(2) };
  49
  50typedef struct E1000IntrDelayTimer_st {
  51    QEMUTimer *timer;
  52    bool running;
  53    uint32_t delay_reg;
  54    uint32_t delay_resolution_ns;
  55    E1000ECore *core;
  56} E1000IntrDelayTimer;
  57
  58struct E1000Core {
  59    uint32_t mac[E1000E_MAC_SIZE];
  60    uint16_t phy[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];
  61    uint16_t eeprom[E1000E_EEPROM_SIZE];
  62
  63    uint32_t rxbuf_sizes[E1000_PSRCTL_BUFFS_PER_DESC];
  64    uint32_t rx_desc_buf_size;
  65    uint32_t rxbuf_min_shift;
  66    uint8_t rx_desc_len;
  67
  68    QEMUTimer *autoneg_timer;
  69
  70    struct e1000e_tx {
  71        e1000x_txd_props props;
  72
  73        bool skip_cp;
  74        unsigned char sum_needed;
  75        bool cptse;
  76        struct NetTxPkt *tx_pkt;
  77    } tx[E1000E_NUM_QUEUES];
  78
  79    struct NetRxPkt *rx_pkt;
  80
  81    bool has_vnet;
  82    int max_queue_num;
  83
  84    /* Interrupt moderation management */
  85    uint32_t delayed_causes;
  86
  87    E1000IntrDelayTimer radv;
  88    E1000IntrDelayTimer rdtr;
  89    E1000IntrDelayTimer raid;
  90
  91    E1000IntrDelayTimer tadv;
  92    E1000IntrDelayTimer tidv;
  93
  94    E1000IntrDelayTimer itr;
  95    bool itr_intr_pending;
  96
  97    E1000IntrDelayTimer eitr[E1000E_MSIX_VEC_NUM];
  98    bool eitr_intr_pending[E1000E_MSIX_VEC_NUM];
  99
 100    VMChangeStateEntry *vmstate;
 101
 102    uint32_t itr_guest_value;
 103    uint32_t eitr_guest_value[E1000E_MSIX_VEC_NUM];
 104
 105    uint16_t vet;
 106
 107    uint8_t permanent_mac[ETH_ALEN];
 108
 109    NICState *owner_nic;
 110    PCIDevice *owner;
 111    void (*owner_start_recv)(PCIDevice *d);
 112};
 113
 114void
 115e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size);
 116
 117uint64_t
 118e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size);
 119
 120void
 121e1000e_core_pci_realize(E1000ECore      *regs,
 122                       const uint16_t *eeprom_templ,
 123                       uint32_t        eeprom_size,
 124                       const uint8_t  *macaddr);
 125
 126void
 127e1000e_core_reset(E1000ECore *core);
 128
 129void
 130e1000e_core_pre_save(E1000ECore *core);
 131
 132int
 133e1000e_core_post_load(E1000ECore *core);
 134
 135void
 136e1000e_core_set_link_status(E1000ECore *core);
 137
 138void
 139e1000e_core_pci_uninit(E1000ECore *core);
 140
 141int
 142e1000e_can_receive(E1000ECore *core);
 143
 144ssize_t
 145e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size);
 146
 147ssize_t
 148e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt);
 149
 150void
 151e1000e_start_recv(E1000ECore *core);
 152