LXR qemu/hw/net/lance.c

   1/*
   2 * QEMU AMD PC-Net II (Am79C970A) emulation
   3 *
   4 * Copyright (c) 2004 Antony T Curtis
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25/* This software was written to be compatible with the specification:
  26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
  27 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
  28 */
  29
  30/*
  31 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
  32 * produced as NCR89C100. See
  33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  34 * and
  35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
  36 */
  37
  38#include "qemu/osdep.h"
  39#include "qemu/timer.h"
  40#include "hw/sparc/sparc32_dma.h"
  41#include "hw/net/lance.h"
  42#include "trace.h"
  43#include "sysemu/sysemu.h"
  44
  45
  46static void parent_lance_reset(void *opaque, int irq, int level)
  47{
  48    SysBusPCNetState *d = opaque;
  49    if (level)
  50        pcnet_h_reset(&d->state);
  51}
  52
  53static void lance_mem_write(void *opaque, hwaddr addr,
  54                            uint64_t val, unsigned size)
  55{
  56    SysBusPCNetState *d = opaque;
  57
  58    trace_lance_mem_writew(addr, val & 0xffff);
  59    pcnet_ioport_writew(&d->state, addr, val & 0xffff);
  60}
  61
  62static uint64_t lance_mem_read(void *opaque, hwaddr addr,
  63                               unsigned size)
  64{
  65    SysBusPCNetState *d = opaque;
  66    uint32_t val;
  67
  68    val = pcnet_ioport_readw(&d->state, addr);
  69    trace_lance_mem_readw(addr, val & 0xffff);
  70    return val & 0xffff;
  71}
  72
  73static const MemoryRegionOps lance_mem_ops = {
  74    .read = lance_mem_read,
  75    .write = lance_mem_write,
  76    .endianness = DEVICE_NATIVE_ENDIAN,
  77    .valid = {
  78        .min_access_size = 2,
  79        .max_access_size = 2,
  80    },
  81};
  82
  83static NetClientInfo net_lance_info = {
  84    .type = NET_CLIENT_DRIVER_NIC,
  85    .size = sizeof(NICState),
  86    .receive = pcnet_receive,
  87    .link_status_changed = pcnet_set_link_status,
  88};
  89
  90static const VMStateDescription vmstate_lance = {
  91    .name = "pcnet",
  92    .version_id = 3,
  93    .minimum_version_id = 2,
  94    .fields = (VMStateField[]) {
  95        VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState),
  96        VMSTATE_END_OF_LIST()
  97    }
  98};
  99
 100static int lance_init(SysBusDevice *sbd)
 101{
 102    DeviceState *dev = DEVICE(sbd);
 103    SysBusPCNetState *d = SYSBUS_PCNET(dev);
 104    PCNetState *s = &d->state;
 105
 106    memory_region_init_io(&s->mmio, OBJECT(d), &lance_mem_ops, d,
 107                          "lance-mmio", 4);
 108
 109    qdev_init_gpio_in(dev, parent_lance_reset, 1);
 110
 111    sysbus_init_mmio(sbd, &s->mmio);
 112
 113    sysbus_init_irq(sbd, &s->irq);
 114
 115    s->phys_mem_read = ledma_memory_read;
 116    s->phys_mem_write = ledma_memory_write;
 117    pcnet_common_init(dev, s, &net_lance_info);
 118    return 0;
 119}
 120
 121static void lance_reset(DeviceState *dev)
 122{
 123    SysBusPCNetState *d = SYSBUS_PCNET(dev);
 124
 125    pcnet_h_reset(&d->state);
 126}
 127
 128static void lance_instance_init(Object *obj)
 129{
 130    SysBusPCNetState *d = SYSBUS_PCNET(obj);
 131    PCNetState *s = &d->state;
 132
 133    device_add_bootindex_property(obj, &s->conf.bootindex,
 134                                  "bootindex", "/ethernet-phy@0",
 135                                  DEVICE(obj), NULL);
 136}
 137
 138static Property lance_properties[] = {
 139    DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
 140    DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),
 141    DEFINE_PROP_END_OF_LIST(),
 142};
 143
 144static void lance_class_init(ObjectClass *klass, void *data)
 145{
 146    DeviceClass *dc = DEVICE_CLASS(klass);
 147    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 148
 149    k->init = lance_init;
 150    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 151    dc->fw_name = "ethernet";
 152    dc->reset = lance_reset;
 153    dc->vmsd = &vmstate_lance;
 154    dc->props = lance_properties;
 155    /* Reason: pointer property "dma" */
 156    dc->user_creatable = false;
 157}
 158
 159static const TypeInfo lance_info = {
 160    .name          = TYPE_LANCE,
 161    .parent        = TYPE_SYS_BUS_DEVICE,
 162    .instance_size = sizeof(SysBusPCNetState),
 163    .class_init    = lance_class_init,
 164    .instance_init = lance_instance_init,
 165};
 166
 167static void lance_register_types(void)
 168{
 169    type_register_static(&lance_info);
 170}
 171
 172type_init(lance_register_types)
 173