LXR qemu/hw/pci-bridge/gen_pcie_root

   1/*
   2 * Generic PCI Express Root Port emulation
   3 *
   4 * Copyright (C) 2017 Red Hat Inc
   5 *
   6 * Authors:
   7 *   Marcel Apfelbaum <marcel@redhat.com>
   8 *
   9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10 * See the COPYING file in the top-level directory.
  11 */
  12
  13#include "qemu/osdep.h"
  14#include "qapi/error.h"
  15#include "hw/pci/msix.h"
  16#include "hw/pci/pcie_port.h"
  17
  18#define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
  19#define GEN_PCIE_ROOT_PORT(obj) \
  20        OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT)
  21
  22#define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
  23#define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
  24
  25typedef struct GenPCIERootPort {
  26    /*< private >*/
  27    PCIESlot parent_obj;
  28    /*< public >*/
  29
  30    bool migrate_msix;
  31
  32    /* additional resources to reserve on firmware init */
  33    uint32_t bus_reserve;
  34    uint64_t io_reserve;
  35    uint64_t mem_reserve;
  36    uint64_t pref32_reserve;
  37    uint64_t pref64_reserve;
  38} GenPCIERootPort;
  39
  40static uint8_t gen_rp_aer_vector(const PCIDevice *d)
  41{
  42    return 0;
  43}
  44
  45static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
  46{
  47    int rc;
  48
  49    rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
  50
  51    if (rc < 0) {
  52        assert(rc == -ENOTSUP);
  53    } else {
  54        msix_vector_use(d, 0);
  55    }
  56
  57    return rc;
  58}
  59
  60static void gen_rp_interrupts_uninit(PCIDevice *d)
  61{
  62    msix_uninit_exclusive_bar(d);
  63}
  64
  65static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
  66{
  67    GenPCIERootPort *rp = opaque;
  68
  69    return rp->migrate_msix;
  70}
  71
  72static void gen_rp_realize(DeviceState *dev, Error **errp)
  73{
  74    PCIDevice *d = PCI_DEVICE(dev);
  75    GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
  76    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
  77    Error *local_err = NULL;
  78
  79    rpc->parent_realize(dev, &local_err);
  80    if (local_err) {
  81        error_propagate(errp, local_err);
  82        return;
  83    }
  84
  85    int rc = pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve,
  86            grp->io_reserve, grp->mem_reserve, grp->pref32_reserve,
  87            grp->pref64_reserve, errp);
  88
  89    if (rc < 0) {
  90        rpc->parent_class.exit(d);
  91        return;
  92    }
  93
  94    if (!grp->io_reserve) {
  95        pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
  96                                     PCI_COMMAND_IO);
  97        d->wmask[PCI_IO_BASE] = 0;
  98        d->wmask[PCI_IO_LIMIT] = 0;
  99    }
 100}
 101
 102static const VMStateDescription vmstate_rp_dev = {
 103    .name = "pcie-root-port",
 104    .priority = MIG_PRI_PCI_BUS,
 105    .version_id = 1,
 106    .minimum_version_id = 1,
 107    .post_load = pcie_cap_slot_post_load,
 108    .fields = (VMStateField[]) {
 109        VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 110        VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 111                       PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 112        VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
 113                          GenPCIERootPort,
 114                          gen_rp_test_migrate_msix),
 115        VMSTATE_END_OF_LIST()
 116    }
 117};
 118
 119static Property gen_rp_props[] = {
 120    DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true),
 121    DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1),
 122    DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1),
 123    DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1),
 124    DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1),
 125    DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1),
 126    DEFINE_PROP_END_OF_LIST()
 127};
 128
 129static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
 130{
 131    DeviceClass *dc = DEVICE_CLASS(klass);
 132    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 133    PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
 134
 135    k->vendor_id = PCI_VENDOR_ID_REDHAT;
 136    k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
 137    dc->desc = "PCI Express Root Port";
 138    dc->vmsd = &vmstate_rp_dev;
 139    dc->props = gen_rp_props;
 140
 141    device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
 142
 143    rpc->aer_vector = gen_rp_aer_vector;
 144    rpc->interrupts_init = gen_rp_interrupts_init;
 145    rpc->interrupts_uninit = gen_rp_interrupts_uninit;
 146    rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
 147}
 148
 149static const TypeInfo gen_rp_dev_info = {
 150    .name          = TYPE_GEN_PCIE_ROOT_PORT,
 151    .parent        = TYPE_PCIE_ROOT_PORT,
 152    .instance_size = sizeof(GenPCIERootPort),
 153    .class_init    = gen_rp_dev_class_init,
 154};
 155
 156 static void gen_rp_register_types(void)
 157 {
 158    type_register_static(&gen_rp_dev_info);
 159 }
 160 type_init(gen_rp_register_types)
 161