LXR qemu/hw/riscv/riscv

   1/*
   2 * QEMU RISCV Hart Array
   3 *
   4 * Copyright (c) 2017 SiFive, Inc.
   5 *
   6 * Holds the state of a heterogenous array of RISC-V harts
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms and conditions of the GNU General Public License,
  10 * version 2 or later, as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along with
  18 * this program.  If not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "hw/sysbus.h"
  24#include "target/riscv/cpu.h"
  25#include "hw/riscv/riscv_hart.h"
  26
  27static Property riscv_harts_props[] = {
  28    DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
  29    DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
  30    DEFINE_PROP_END_OF_LIST(),
  31};
  32
  33static void riscv_harts_cpu_reset(void *opaque)
  34{
  35    RISCVCPU *cpu = opaque;
  36    cpu_reset(CPU(cpu));
  37}
  38
  39static void riscv_harts_realize(DeviceState *dev, Error **errp)
  40{
  41    RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
  42    Error *err = NULL;
  43    int n;
  44
  45    s->harts = g_new0(RISCVCPU, s->num_harts);
  46
  47    for (n = 0; n < s->num_harts; n++) {
  48
  49        object_initialize(&s->harts[n], sizeof(RISCVCPU), s->cpu_type);
  50        s->harts[n].env.mhartid = n;
  51        object_property_add_child(OBJECT(s), "harts[*]", OBJECT(&s->harts[n]),
  52                                  &error_abort);
  53        qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
  54        object_property_set_bool(OBJECT(&s->harts[n]), true,
  55                                 "realized", &err);
  56        if (err) {
  57            error_propagate(errp, err);
  58            return;
  59        }
  60    }
  61}
  62
  63static void riscv_harts_class_init(ObjectClass *klass, void *data)
  64{
  65    DeviceClass *dc = DEVICE_CLASS(klass);
  66
  67    dc->props = riscv_harts_props;
  68    dc->realize = riscv_harts_realize;
  69}
  70
  71static void riscv_harts_init(Object *obj)
  72{
  73    /* RISCVHartArrayState *s = SIFIVE_COREPLEX(obj); */
  74}
  75
  76static const TypeInfo riscv_harts_info = {
  77    .name          = TYPE_RISCV_HART_ARRAY,
  78    .parent        = TYPE_SYS_BUS_DEVICE,
  79    .instance_size = sizeof(RISCVHartArrayState),
  80    .instance_init = riscv_harts_init,
  81    .class_init    = riscv_harts_class_init,
  82};
  83
  84static void riscv_harts_register_types(void)
  85{
  86    type_register_static(&riscv_harts_info);
  87}
  88
  89type_init(riscv_harts_register_types)
  90