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19#include "qemu/osdep.h"
20#include "hw/hw.h"
21#include "hw/arm/omap.h"
22#include "hw/sd/sd.h"
23
24struct omap_mmc_s {
25 qemu_irq irq;
26 qemu_irq *dma;
27 qemu_irq coverswitch;
28 MemoryRegion iomem;
29 omap_clk clk;
30 SDState *card;
31 uint16_t last_cmd;
32 uint16_t sdio;
33 uint16_t rsp[8];
34 uint32_t arg;
35 int lines;
36 int dw;
37 int mode;
38 int enable;
39 int be;
40 int rev;
41 uint16_t status;
42 uint16_t mask;
43 uint8_t cto;
44 uint16_t dto;
45 int clkdiv;
46 uint16_t fifo[32];
47 int fifo_start;
48 int fifo_len;
49 uint16_t blen;
50 uint16_t blen_counter;
51 uint16_t nblk;
52 uint16_t nblk_counter;
53 int tx_dma;
54 int rx_dma;
55 int af_level;
56 int ae_level;
57
58 int ddir;
59 int transfer;
60
61 int cdet_wakeup;
62 int cdet_enable;
63 int cdet_state;
64 qemu_irq cdet;
65};
66
67static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
68{
69 qemu_set_irq(s->irq, !!(s->status & s->mask));
70}
71
72static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
73{
74 if (!host->transfer && !host->fifo_len) {
75 host->status &= 0xf3ff;
76 return;
77 }
78
79 if (host->fifo_len > host->af_level && host->ddir) {
80 if (host->rx_dma) {
81 host->status &= 0xfbff;
82 qemu_irq_raise(host->dma[1]);
83 } else
84 host->status |= 0x0400;
85 } else {
86 host->status &= 0xfbff;
87 qemu_irq_lower(host->dma[1]);
88 }
89
90 if (host->fifo_len < host->ae_level && !host->ddir) {
91 if (host->tx_dma) {
92 host->status &= 0xf7ff;
93 qemu_irq_raise(host->dma[0]);
94 } else
95 host->status |= 0x0800;
96 } else {
97 qemu_irq_lower(host->dma[0]);
98 host->status &= 0xf7ff;
99 }
100}
101
102typedef enum {
103 sd_nore = 0,
104 sd_r1,
105 sd_r2,
106 sd_r3,
107 sd_r6 = 6,
108 sd_r1b = -1,
109} sd_rsp_type_t;
110
111static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
112 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
113{
114 uint32_t rspstatus, mask;
115 int rsplen, timeout;
116 SDRequest request;
117 uint8_t response[16];
118
119 if (init && cmd == 0) {
120 host->status |= 0x0001;
121 return;
122 }
123
124 if (resptype == sd_r1 && busy)
125 resptype = sd_r1b;
126
127 if (type == sd_adtc) {
128 host->fifo_start = 0;
129 host->fifo_len = 0;
130 host->transfer = 1;
131 host->ddir = dir;
132 } else
133 host->transfer = 0;
134 timeout = 0;
135 mask = 0;
136 rspstatus = 0;
137
138 request.cmd = cmd;
139 request.arg = host->arg;
140 request.crc = 0;
141
142 rsplen = sd_do_command(host->card, &request, response);
143
144
145 switch (resptype) {
146 case sd_nore:
147 rsplen = 0;
148 break;
149
150 case sd_r1:
151 case sd_r1b:
152 if (rsplen < 4) {
153 timeout = 1;
154 break;
155 }
156 rsplen = 4;
157
158 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
159 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
160 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
161 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
162 CID_CSD_OVERWRITE;
163 if (host->sdio & (1 << 13))
164 mask |= AKE_SEQ_ERROR;
165 rspstatus = (response[0] << 24) | (response[1] << 16) |
166 (response[2] << 8) | (response[3] << 0);
167 break;
168
169 case sd_r2:
170 if (rsplen < 16) {
171 timeout = 1;
172 break;
173 }
174 rsplen = 16;
175 break;
176
177 case sd_r3:
178 if (rsplen < 4) {
179 timeout = 1;
180 break;
181 }
182 rsplen = 4;
183
184 rspstatus = (response[0] << 24) | (response[1] << 16) |
185 (response[2] << 8) | (response[3] << 0);
186 if (rspstatus & 0x80000000)
187 host->status &= 0xe000;
188 else
189 host->status |= 0x1000;
190 break;
191
192 case sd_r6:
193 if (rsplen < 4) {
194 timeout = 1;
195 break;
196 }
197 rsplen = 4;
198
199 mask = 0xe000 | AKE_SEQ_ERROR;
200 rspstatus = (response[2] << 8) | (response[3] << 0);
201 }
202
203 if (rspstatus & mask)
204 host->status |= 0x4000;
205 else
206 host->status &= 0xb000;
207
208 if (rsplen)
209 for (rsplen = 0; rsplen < 8; rsplen ++)
210 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
211 (response[(rsplen << 1) | 0] << 8);
212
213 if (timeout)
214 host->status |= 0x0080;
215 else if (cmd == 12)
216 host->status |= 0x0005;
217 else
218 host->status |= 0x0001;
219}
220
221static void omap_mmc_transfer(struct omap_mmc_s *host)
222{
223 uint8_t value;
224
225 if (!host->transfer)
226 return;
227
228 while (1) {
229 if (host->ddir) {
230 if (host->fifo_len > host->af_level)
231 break;
232
233 value = sd_read_data(host->card);
234 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
235 if (-- host->blen_counter) {
236 value = sd_read_data(host->card);
237 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
238 value << 8;
239 host->blen_counter --;
240 }
241
242 host->fifo_len ++;
243 } else {
244 if (!host->fifo_len)
245 break;
246
247 value = host->fifo[host->fifo_start] & 0xff;
248 sd_write_data(host->card, value);
249 if (-- host->blen_counter) {
250 value = host->fifo[host->fifo_start] >> 8;
251 sd_write_data(host->card, value);
252 host->blen_counter --;
253 }
254
255 host->fifo_start ++;
256 host->fifo_len --;
257 host->fifo_start &= 31;
258 }
259
260 if (host->blen_counter == 0) {
261 host->nblk_counter --;
262 host->blen_counter = host->blen;
263
264 if (host->nblk_counter == 0) {
265 host->nblk_counter = host->nblk;
266 host->transfer = 0;
267 host->status |= 0x0008;
268 break;
269 }
270 }
271 }
272}
273
274static void omap_mmc_update(void *opaque)
275{
276 struct omap_mmc_s *s = opaque;
277 omap_mmc_transfer(s);
278 omap_mmc_fifolevel_update(s);
279 omap_mmc_interrupts_update(s);
280}
281
282void omap_mmc_reset(struct omap_mmc_s *host)
283{
284 host->last_cmd = 0;
285 memset(host->rsp, 0, sizeof(host->rsp));
286 host->arg = 0;
287 host->dw = 0;
288 host->mode = 0;
289 host->enable = 0;
290 host->status = 0;
291 host->mask = 0;
292 host->cto = 0;
293 host->dto = 0;
294 host->fifo_len = 0;
295 host->blen = 0;
296 host->blen_counter = 0;
297 host->nblk = 0;
298 host->nblk_counter = 0;
299 host->tx_dma = 0;
300 host->rx_dma = 0;
301 host->ae_level = 0x00;
302 host->af_level = 0x1f;
303 host->transfer = 0;
304 host->cdet_wakeup = 0;
305 host->cdet_enable = 0;
306 qemu_set_irq(host->coverswitch, host->cdet_state);
307 host->clkdiv = 0;
308
309
310
311
312
313 device_reset(DEVICE(host->card));
314}
315
316static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
317 unsigned size)
318{
319 uint16_t i;
320 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
321
322 if (size != 2) {
323 return omap_badwidth_read16(opaque, offset);
324 }
325
326 switch (offset) {
327 case 0x00:
328 return s->last_cmd;
329
330 case 0x04:
331 return s->arg & 0x0000ffff;
332
333 case 0x08:
334 return s->arg >> 16;
335
336 case 0x0c:
337 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
338 (s->be << 10) | s->clkdiv;
339
340 case 0x10:
341 return s->status;
342
343 case 0x14:
344 return s->mask;
345
346 case 0x18:
347 return s->cto;
348
349 case 0x1c:
350 return s->dto;
351
352 case 0x20:
353
354 i = s->fifo[s->fifo_start];
355 if (s->fifo_len == 0) {
356 printf("MMC: FIFO underrun\n");
357 return i;
358 }
359 s->fifo_start ++;
360 s->fifo_len --;
361 s->fifo_start &= 31;
362 omap_mmc_transfer(s);
363 omap_mmc_fifolevel_update(s);
364 omap_mmc_interrupts_update(s);
365 return i;
366
367 case 0x24:
368 return s->blen_counter;
369
370 case 0x28:
371 return s->nblk_counter;
372
373 case 0x2c:
374 return (s->rx_dma << 15) | (s->af_level << 8) |
375 (s->tx_dma << 7) | s->ae_level;
376
377 case 0x30:
378 return 0x0000;
379 case 0x34:
380 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
381 case 0x38:
382 return 0x0000;
383
384 case 0x3c:
385 return s->rev;
386
387 case 0x40:
388 case 0x44:
389 case 0x48:
390 case 0x4c:
391 case 0x50:
392 case 0x54:
393 case 0x58:
394 case 0x5c:
395 return s->rsp[(offset - 0x40) >> 2];
396
397
398 case 0x60:
399 case 0x64:
400 return 0;
401 case 0x68:
402 return 1;
403 }
404
405 OMAP_BAD_REG(offset);
406 return 0;
407}
408
409static void omap_mmc_write(void *opaque, hwaddr offset,
410 uint64_t value, unsigned size)
411{
412 int i;
413 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
414
415 if (size != 2) {
416 omap_badwidth_write16(opaque, offset, value);
417 return;
418 }
419
420 switch (offset) {
421 case 0x00:
422 if (!s->enable)
423 break;
424
425 s->last_cmd = value;
426 for (i = 0; i < 8; i ++)
427 s->rsp[i] = 0x0000;
428 omap_mmc_command(s, value & 63, (value >> 15) & 1,
429 (sd_cmd_type_t) ((value >> 12) & 3),
430 (value >> 11) & 1,
431 (sd_rsp_type_t) ((value >> 8) & 7),
432 (value >> 7) & 1);
433 omap_mmc_update(s);
434 break;
435
436 case 0x04:
437 s->arg &= 0xffff0000;
438 s->arg |= 0x0000ffff & value;
439 break;
440
441 case 0x08:
442 s->arg &= 0x0000ffff;
443 s->arg |= value << 16;
444 break;
445
446 case 0x0c:
447 s->dw = (value >> 15) & 1;
448 s->mode = (value >> 12) & 3;
449 s->enable = (value >> 11) & 1;
450 s->be = (value >> 10) & 1;
451 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
452 if (s->mode != 0)
453 printf("SD mode %i unimplemented!\n", s->mode);
454 if (s->be != 0)
455 printf("SD FIFO byte sex unimplemented!\n");
456 if (s->dw != 0 && s->lines < 4)
457 printf("4-bit SD bus enabled\n");
458 if (!s->enable)
459 omap_mmc_reset(s);
460 break;
461
462 case 0x10:
463 s->status &= ~value;
464 omap_mmc_interrupts_update(s);
465 break;
466
467 case 0x14:
468 s->mask = value & 0x7fff;
469 omap_mmc_interrupts_update(s);
470 break;
471
472 case 0x18:
473 s->cto = value & 0xff;
474 if (s->cto > 0xfd && s->rev <= 1)
475 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
476 break;
477
478 case 0x1c:
479 s->dto = value & 0xffff;
480 break;
481
482 case 0x20:
483
484 if (s->fifo_len == 32)
485 break;
486 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
487 s->fifo_len ++;
488 omap_mmc_transfer(s);
489 omap_mmc_fifolevel_update(s);
490 omap_mmc_interrupts_update(s);
491 break;
492
493 case 0x24:
494 s->blen = (value & 0x07ff) + 1;
495 s->blen_counter = s->blen;
496 break;
497
498 case 0x28:
499 s->nblk = (value & 0x07ff) + 1;
500 s->nblk_counter = s->nblk;
501 s->blen_counter = s->blen;
502 break;
503
504 case 0x2c:
505 s->rx_dma = (value >> 15) & 1;
506 s->af_level = (value >> 8) & 0x1f;
507 s->tx_dma = (value >> 7) & 1;
508 s->ae_level = value & 0x1f;
509
510 if (s->rx_dma)
511 s->status &= 0xfbff;
512 if (s->tx_dma)
513 s->status &= 0xf7ff;
514 omap_mmc_fifolevel_update(s);
515 omap_mmc_interrupts_update(s);
516 break;
517
518
519 case 0x30:
520 break;
521 case 0x34:
522 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
523 s->cdet_wakeup = (value >> 9) & 1;
524 s->cdet_enable = (value >> 2) & 1;
525 break;
526 case 0x38:
527 break;
528
529 case 0x3c:
530 case 0x40:
531 case 0x44:
532 case 0x48:
533 case 0x4c:
534 case 0x50:
535 case 0x54:
536 case 0x58:
537 case 0x5c:
538 OMAP_RO_REG(offset);
539 break;
540
541
542 case 0x60:
543 if (value & 0xf)
544 printf("MMC: SDIO bits used!\n");
545 break;
546 case 0x64:
547 if (value & (1 << 2))
548 omap_mmc_reset(s);
549 break;
550 case 0x68:
551 OMAP_RO_REG(offset);
552 break;
553
554 default:
555 OMAP_BAD_REG(offset);
556 }
557}
558
559static const MemoryRegionOps omap_mmc_ops = {
560 .read = omap_mmc_read,
561 .write = omap_mmc_write,
562 .endianness = DEVICE_NATIVE_ENDIAN,
563};
564
565static void omap_mmc_cover_cb(void *opaque, int line, int level)
566{
567 struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
568
569 if (!host->cdet_state && level) {
570 host->status |= 0x0002;
571 omap_mmc_interrupts_update(host);
572 if (host->cdet_wakeup) {
573
574 }
575 }
576
577 if (host->cdet_state != level) {
578 qemu_set_irq(host->coverswitch, level);
579 host->cdet_state = level;
580 }
581}
582
583struct omap_mmc_s *omap_mmc_init(hwaddr base,
584 MemoryRegion *sysmem,
585 BlockBackend *blk,
586 qemu_irq irq, qemu_irq dma[], omap_clk clk)
587{
588 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
589
590 s->irq = irq;
591 s->dma = dma;
592 s->clk = clk;
593 s->lines = 1;
594 s->rev = 1;
595
596 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
597 memory_region_add_subregion(sysmem, base, &s->iomem);
598
599
600 s->card = sd_init(blk, false);
601 if (s->card == NULL) {
602 exit(1);
603 }
604
605 omap_mmc_reset(s);
606
607 return s;
608}
609
610struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
611 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
612 omap_clk fclk, omap_clk iclk)
613{
614 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
615
616 s->irq = irq;
617 s->dma = dma;
618 s->clk = fclk;
619 s->lines = 4;
620 s->rev = 2;
621
622 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
623 omap_l4_region_size(ta, 0));
624 omap_l4_attach(ta, 0, &s->iomem);
625
626
627 s->card = sd_init(blk, false);
628 if (s->card == NULL) {
629 exit(1);
630 }
631
632 s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
633 sd_set_cb(s->card, NULL, s->cdet);
634
635 omap_mmc_reset(s);
636
637 return s;
638}
639
640void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
641{
642 if (s->cdet) {
643 sd_set_cb(s->card, ro, s->cdet);
644 s->coverswitch = cover;
645 qemu_set_irq(cover, s->cdet_state);
646 } else
647 sd_set_cb(s->card, ro, cover);
648}
649
650void omap_mmc_enable(struct omap_mmc_s *s, int enable)
651{
652 sd_enable(s->card, enable);
653}
654