LXR qemu/hw/timer/cmsdk-apb-timer.c

   1/*
   2 * ARM CMSDK APB timer emulation
   3 *
   4 * Copyright (c) 2017 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 *  This program is free software; you can redistribute it and/or modify
   8 *  it under the terms of the GNU General Public License version 2 or
   9 *  (at your option) any later version.
  10 */
  11
  12/* This is a model of the "APB timer" which is part of the Cortex-M
  13 * System Design Kit (CMSDK) and documented in the Cortex-M System
  14 * Design Kit Technical Reference Manual (ARM DDI0479C):
  15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
  16 *
  17 * The hardware has an EXTIN input wire, which can be configured
  18 * by the guest to act either as a 'timer enable' (timer does not run
  19 * when EXTIN is low), or as a 'timer clock' (timer runs at frequency
  20 * of EXTIN clock, not PCLK frequency). We don't model this.
  21 *
  22 * The documentation is not very clear about the exact behaviour;
  23 * we choose to implement that the interrupt is triggered when
  24 * the counter goes from 1 to 0, that the counter then holds at 0
  25 * for one clock cycle before reloading from the RELOAD register,
  26 * and that if the RELOAD register is 0 this does not cause an
  27 * interrupt (as there is no further 1->0 transition).
  28 */
  29
  30#include "qemu/osdep.h"
  31#include "qemu/log.h"
  32#include "qemu/main-loop.h"
  33#include "qapi/error.h"
  34#include "trace.h"
  35#include "hw/sysbus.h"
  36#include "hw/registerfields.h"
  37#include "hw/timer/cmsdk-apb-timer.h"
  38
  39REG32(CTRL, 0)
  40    FIELD(CTRL, EN, 0, 1)
  41    FIELD(CTRL, SELEXTEN, 1, 1)
  42    FIELD(CTRL, SELEXTCLK, 2, 1)
  43    FIELD(CTRL, IRQEN, 3, 1)
  44REG32(VALUE, 4)
  45REG32(RELOAD, 8)
  46REG32(INTSTATUS, 0xc)
  47    FIELD(INTSTATUS, IRQ, 0, 1)
  48REG32(PID4, 0xFD0)
  49REG32(PID5, 0xFD4)
  50REG32(PID6, 0xFD8)
  51REG32(PID7, 0xFDC)
  52REG32(PID0, 0xFE0)
  53REG32(PID1, 0xFE4)
  54REG32(PID2, 0xFE8)
  55REG32(PID3, 0xFEC)
  56REG32(CID0, 0xFF0)
  57REG32(CID1, 0xFF4)
  58REG32(CID2, 0xFF8)
  59REG32(CID3, 0xFFC)
  60
  61/* PID/CID values */
  62static const int timer_id[] = {
  63    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
  64    0x22, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
  65    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  66};
  67
  68static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s)
  69{
  70    qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK));
  71}
  72
  73static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
  74{
  75    CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
  76    uint64_t r;
  77
  78    switch (offset) {
  79    case A_CTRL:
  80        r = s->ctrl;
  81        break;
  82    case A_VALUE:
  83        r = ptimer_get_count(s->timer);
  84        break;
  85    case A_RELOAD:
  86        r = ptimer_get_limit(s->timer);
  87        break;
  88    case A_INTSTATUS:
  89        r = s->intstatus;
  90        break;
  91    case A_PID4 ... A_CID3:
  92        r = timer_id[(offset - A_PID4) / 4];
  93        break;
  94    default:
  95        qemu_log_mask(LOG_GUEST_ERROR,
  96                      "CMSDK APB timer read: bad offset %x\n", (int) offset);
  97        r = 0;
  98        break;
  99    }
 100    trace_cmsdk_apb_timer_read(offset, r, size);
 101    return r;
 102}
 103
 104static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
 105                                  unsigned size)
 106{
 107    CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
 108
 109    trace_cmsdk_apb_timer_write(offset, value, size);
 110
 111    switch (offset) {
 112    case A_CTRL:
 113        if (value & 6) {
 114            /* Bits [1] and [2] enable using EXTIN as either clock or
 115             * an enable line. We don't model this.
 116             */
 117            qemu_log_mask(LOG_UNIMP,
 118                          "CMSDK APB timer: EXTIN input not supported\n");
 119        }
 120        s->ctrl = value & 0xf;
 121        if (s->ctrl & R_CTRL_EN_MASK) {
 122            ptimer_run(s->timer, 0);
 123        } else {
 124            ptimer_stop(s->timer);
 125        }
 126        break;
 127    case A_RELOAD:
 128        /* Writing to reload also sets the current timer value */
 129        ptimer_set_limit(s->timer, value, 1);
 130        break;
 131    case A_VALUE:
 132        ptimer_set_count(s->timer, value);
 133        break;
 134    case A_INTSTATUS:
 135        /* Just one bit, which is W1C. */
 136        value &= 1;
 137        s->intstatus &= ~value;
 138        cmsdk_apb_timer_update(s);
 139        break;
 140    case A_PID4 ... A_CID3:
 141        qemu_log_mask(LOG_GUEST_ERROR,
 142                      "CMSDK APB timer write: write to RO offset 0x%x\n",
 143                      (int)offset);
 144        break;
 145    default:
 146        qemu_log_mask(LOG_GUEST_ERROR,
 147                      "CMSDK APB timer write: bad offset 0x%x\n", (int) offset);
 148        break;
 149    }
 150}
 151
 152static const MemoryRegionOps cmsdk_apb_timer_ops = {
 153    .read = cmsdk_apb_timer_read,
 154    .write = cmsdk_apb_timer_write,
 155    .endianness = DEVICE_LITTLE_ENDIAN,
 156};
 157
 158static void cmsdk_apb_timer_tick(void *opaque)
 159{
 160    CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
 161
 162    if (s->ctrl & R_CTRL_IRQEN_MASK) {
 163        s->intstatus |= R_INTSTATUS_IRQ_MASK;
 164        cmsdk_apb_timer_update(s);
 165    }
 166}
 167
 168static void cmsdk_apb_timer_reset(DeviceState *dev)
 169{
 170    CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
 171
 172    trace_cmsdk_apb_timer_reset();
 173    s->ctrl = 0;
 174    s->intstatus = 0;
 175    ptimer_stop(s->timer);
 176    /* Set the limit and the count */
 177    ptimer_set_limit(s->timer, 0, 1);
 178}
 179
 180static void cmsdk_apb_timer_init(Object *obj)
 181{
 182    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 183    CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj);
 184
 185    memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops,
 186                          s, "cmsdk-apb-timer", 0x1000);
 187    sysbus_init_mmio(sbd, &s->iomem);
 188    sysbus_init_irq(sbd, &s->timerint);
 189}
 190
 191static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
 192{
 193    CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
 194    QEMUBH *bh;
 195
 196    if (s->pclk_frq == 0) {
 197        error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
 198        return;
 199    }
 200
 201    bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
 202    s->timer = ptimer_init(bh,
 203                           PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
 204                           PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
 205                           PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
 206                           PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
 207
 208    ptimer_set_freq(s->timer, s->pclk_frq);
 209}
 210
 211static const VMStateDescription cmsdk_apb_timer_vmstate = {
 212    .name = "cmsdk-apb-timer",
 213    .version_id = 1,
 214    .minimum_version_id = 1,
 215    .fields = (VMStateField[]) {
 216        VMSTATE_PTIMER(timer, CMSDKAPBTIMER),
 217        VMSTATE_UINT32(ctrl, CMSDKAPBTIMER),
 218        VMSTATE_UINT32(value, CMSDKAPBTIMER),
 219        VMSTATE_UINT32(reload, CMSDKAPBTIMER),
 220        VMSTATE_UINT32(intstatus, CMSDKAPBTIMER),
 221        VMSTATE_END_OF_LIST()
 222    }
 223};
 224
 225static Property cmsdk_apb_timer_properties[] = {
 226    DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0),
 227    DEFINE_PROP_END_OF_LIST(),
 228};
 229
 230static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
 231{
 232    DeviceClass *dc = DEVICE_CLASS(klass);
 233
 234    dc->realize = cmsdk_apb_timer_realize;
 235    dc->vmsd = &cmsdk_apb_timer_vmstate;
 236    dc->reset = cmsdk_apb_timer_reset;
 237    dc->props = cmsdk_apb_timer_properties;
 238}
 239
 240static const TypeInfo cmsdk_apb_timer_info = {
 241    .name = TYPE_CMSDK_APB_TIMER,
 242    .parent = TYPE_SYS_BUS_DEVICE,
 243    .instance_size = sizeof(CMSDKAPBTIMER),
 244    .instance_init = cmsdk_apb_timer_init,
 245    .class_init = cmsdk_apb_timer_class_init,
 246};
 247
 248static void cmsdk_apb_timer_register_types(void)
 249{
 250    type_register_static(&cmsdk_apb_timer_info);
 251}
 252
 253type_init(cmsdk_apb_timer_register_types);
 254