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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/isa/isa.h"
28#include "qemu/timer.h"
29#include "hw/timer/i8254.h"
30#include "hw/timer/i8254_internal.h"
31
32
33void pit_set_gate(ISADevice *dev, int channel, int val)
34{
35 PITCommonState *pit = PIT_COMMON(dev);
36 PITChannelState *s = &pit->channels[channel];
37 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
38
39 c->set_channel_gate(pit, s, val);
40}
41
42
43int pit_get_out(PITChannelState *s, int64_t current_time)
44{
45 uint64_t d;
46 int out;
47
48 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
49 NANOSECONDS_PER_SECOND);
50 switch (s->mode) {
51 default:
52 case 0:
53 out = (d >= s->count);
54 break;
55 case 1:
56 out = (d < s->count);
57 break;
58 case 2:
59 if ((d % s->count) == 0 && d != 0) {
60 out = 1;
61 } else {
62 out = 0;
63 }
64 break;
65 case 3:
66 out = (d % s->count) < ((s->count + 1) >> 1);
67 break;
68 case 4:
69 case 5:
70 out = (d == s->count);
71 break;
72 }
73 return out;
74}
75
76
77int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
78{
79 uint64_t d, next_time, base;
80 int period2;
81
82 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
83 NANOSECONDS_PER_SECOND);
84 switch (s->mode) {
85 default:
86 case 0:
87 case 1:
88 if (d < s->count) {
89 next_time = s->count;
90 } else {
91 return -1;
92 }
93 break;
94 case 2:
95 base = QEMU_ALIGN_DOWN(d, s->count);
96 if ((d - base) == 0 && d != 0) {
97 next_time = base + s->count;
98 } else {
99 next_time = base + s->count + 1;
100 }
101 break;
102 case 3:
103 base = QEMU_ALIGN_DOWN(d, s->count);
104 period2 = ((s->count + 1) >> 1);
105 if ((d - base) < period2) {
106 next_time = base + period2;
107 } else {
108 next_time = base + s->count;
109 }
110 break;
111 case 4:
112 case 5:
113 if (d < s->count) {
114 next_time = s->count;
115 } else if (d == s->count) {
116 next_time = s->count + 1;
117 } else {
118 return -1;
119 }
120 break;
121 }
122
123 next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND,
124 PIT_FREQ);
125
126
127 if (next_time <= current_time) {
128 next_time = current_time + 1;
129 }
130 return next_time;
131}
132
133void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
134 PITChannelInfo *info)
135{
136 info->gate = sc->gate;
137 info->mode = sc->mode;
138 info->initial_count = sc->count;
139 info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
140}
141
142void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
143{
144 PITCommonState *pit = PIT_COMMON(dev);
145 PITChannelState *s = &pit->channels[channel];
146 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
147
148 c->get_channel_info(pit, s, info);
149}
150
151void pit_reset_common(PITCommonState *pit)
152{
153 PITChannelState *s;
154 int i;
155
156 for (i = 0; i < 3; i++) {
157 s = &pit->channels[i];
158 s->mode = 3;
159 s->gate = (i != 2);
160 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
161 s->count = 0x10000;
162 if (i == 0 && !s->irq_disabled) {
163 s->next_transition_time =
164 pit_get_next_transition_time(s, s->count_load_time);
165 }
166 }
167}
168
169static void pit_common_realize(DeviceState *dev, Error **errp)
170{
171 ISADevice *isadev = ISA_DEVICE(dev);
172 PITCommonState *pit = PIT_COMMON(dev);
173
174 isa_register_ioport(isadev, &pit->ioports, pit->iobase);
175
176 qdev_set_legacy_instance_id(dev, pit->iobase, 2);
177}
178
179static const VMStateDescription vmstate_pit_channel = {
180 .name = "pit channel",
181 .version_id = 2,
182 .minimum_version_id = 2,
183 .fields = (VMStateField[]) {
184 VMSTATE_INT32(count, PITChannelState),
185 VMSTATE_UINT16(latched_count, PITChannelState),
186 VMSTATE_UINT8(count_latched, PITChannelState),
187 VMSTATE_UINT8(status_latched, PITChannelState),
188 VMSTATE_UINT8(status, PITChannelState),
189 VMSTATE_UINT8(read_state, PITChannelState),
190 VMSTATE_UINT8(write_state, PITChannelState),
191 VMSTATE_UINT8(write_latch, PITChannelState),
192 VMSTATE_UINT8(rw_mode, PITChannelState),
193 VMSTATE_UINT8(mode, PITChannelState),
194 VMSTATE_UINT8(bcd, PITChannelState),
195 VMSTATE_UINT8(gate, PITChannelState),
196 VMSTATE_INT64(count_load_time, PITChannelState),
197 VMSTATE_INT64(next_transition_time, PITChannelState),
198 VMSTATE_END_OF_LIST()
199 }
200};
201
202static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
203{
204 PITCommonState *pit = opaque;
205 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
206 PITChannelState *s;
207 int i;
208
209 if (version_id != 1) {
210 return -EINVAL;
211 }
212
213 for (i = 0; i < 3; i++) {
214 s = &pit->channels[i];
215 s->count = qemu_get_be32(f);
216 qemu_get_be16s(f, &s->latched_count);
217 qemu_get_8s(f, &s->count_latched);
218 qemu_get_8s(f, &s->status_latched);
219 qemu_get_8s(f, &s->status);
220 qemu_get_8s(f, &s->read_state);
221 qemu_get_8s(f, &s->write_state);
222 qemu_get_8s(f, &s->write_latch);
223 qemu_get_8s(f, &s->rw_mode);
224 qemu_get_8s(f, &s->mode);
225 qemu_get_8s(f, &s->bcd);
226 qemu_get_8s(f, &s->gate);
227 s->count_load_time = qemu_get_be64(f);
228 s->irq_disabled = 0;
229 if (i == 0) {
230 s->next_transition_time = qemu_get_be64(f);
231 }
232 }
233 if (c->post_load) {
234 c->post_load(pit);
235 }
236 return 0;
237}
238
239static int pit_dispatch_pre_save(void *opaque)
240{
241 PITCommonState *s = opaque;
242 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
243
244 if (c->pre_save) {
245 c->pre_save(s);
246 }
247
248 return 0;
249}
250
251static int pit_dispatch_post_load(void *opaque, int version_id)
252{
253 PITCommonState *s = opaque;
254 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
255
256 if (c->post_load) {
257 c->post_load(s);
258 }
259 return 0;
260}
261
262static const VMStateDescription vmstate_pit_common = {
263 .name = "i8254",
264 .version_id = 3,
265 .minimum_version_id = 2,
266 .minimum_version_id_old = 1,
267 .load_state_old = pit_load_old,
268 .pre_save = pit_dispatch_pre_save,
269 .post_load = pit_dispatch_post_load,
270 .fields = (VMStateField[]) {
271 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
272 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
273 vmstate_pit_channel, PITChannelState),
274 VMSTATE_INT64(channels[0].next_transition_time,
275 PITCommonState),
276 VMSTATE_END_OF_LIST()
277 }
278};
279
280static void pit_common_class_init(ObjectClass *klass, void *data)
281{
282 DeviceClass *dc = DEVICE_CLASS(klass);
283
284 dc->realize = pit_common_realize;
285 dc->vmsd = &vmstate_pit_common;
286
287
288
289
290
291 dc->user_creatable = false;
292}
293
294static const TypeInfo pit_common_type = {
295 .name = TYPE_PIT_COMMON,
296 .parent = TYPE_ISA_DEVICE,
297 .instance_size = sizeof(PITCommonState),
298 .class_size = sizeof(PITCommonClass),
299 .class_init = pit_common_class_init,
300 .abstract = true,
301};
302
303static void register_devices(void)
304{
305 type_register_static(&pit_common_type);
306}
307
308type_init(register_devices);
309