1/* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19#ifndef CPU_DEFS_H 20#define CPU_DEFS_H 21 22#ifndef NEED_CPU_H 23#error cpu.h included from common code 24#endif 25 26#include "qemu/host-utils.h" 27#include "qemu/queue.h" 28#ifdef CONFIG_TCG 29#include "tcg-target.h" 30#endif 31#ifndef CONFIG_USER_ONLY 32#include "exec/hwaddr.h" 33#endif 34#include "exec/memattrs.h" 35 36#ifndef TARGET_LONG_BITS 37#error TARGET_LONG_BITS must be defined before including this header 38#endif 39 40#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 41 42/* target_ulong is the type of a virtual address */ 43#if TARGET_LONG_SIZE == 4 44typedef int32_t target_long; 45typedef uint32_t target_ulong; 46#define TARGET_FMT_lx "%08x" 47#define TARGET_FMT_ld "%d" 48#define TARGET_FMT_lu "%u" 49#elif TARGET_LONG_SIZE == 8 50typedef int64_t target_long; 51typedef uint64_t target_ulong; 52#define TARGET_FMT_lx "%016" PRIx64 53#define TARGET_FMT_ld "%" PRId64 54#define TARGET_FMT_lu "%" PRIu64 55#else 56#error TARGET_LONG_SIZE undefined 57#endif 58 59#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 60/* use a fully associative victim tlb of 8 entries */ 61#define CPU_VTLB_SIZE 8 62 63#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 64#define CPU_TLB_ENTRY_BITS 4 65#else 66#define CPU_TLB_ENTRY_BITS 5 67#endif 68 69/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that 70 * the TLB is not unnecessarily small, but still small enough for the 71 * TLB lookup instruction sequence used by the TCG target. 72 * 73 * TCG will have to generate an operand as large as the distance between 74 * env and the tlb_table[NB_MMU_MODES - 1][0].addend. For simplicity, 75 * the TCG targets just round everything up to the next power of two, and 76 * count bits. This works because: 1) the size of each TLB is a largish 77 * power of two, 2) and because the limit of the displacement is really close 78 * to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller 79 * than the size of a TLB. 80 * 81 * For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG 82 * just says "the displacement is 16 bits". TCG_TARGET_TLB_DISPLACEMENT_BITS 83 * then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily 84 * small": 2^15). The operand then will come up smaller than 0xFFF0 without 85 * any particular care, because the TLB for a single MMU mode is larger than 86 * 0x10000-0xFFF0=16 bytes. In the end, the maximum value of the operand 87 * could be something like 0xC000 (the offset of the last TLB table) plus 88 * 0x18 (the offset of the addend field in each TLB entry) plus the offset 89 * of tlb_table inside env (which is non-trivial but not huge). 90 */ 91#define CPU_TLB_BITS \ 92 MIN(8, \ 93 TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ 94 (NB_MMU_MODES <= 1 ? 0 : \ 95 NB_MMU_MODES <= 2 ? 1 : \ 96 NB_MMU_MODES <= 4 ? 2 : \ 97 NB_MMU_MODES <= 8 ? 3 : 4)) 98 99#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 100 101typedef struct CPUTLBEntry { 102 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 103 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 104 go directly to ram. 105 bit 3 : indicates that the entry is invalid 106 bit 2..0 : zero 107 */ 108 union { 109 struct { 110 target_ulong addr_read; 111 target_ulong addr_write; 112 target_ulong addr_code; 113 /* Addend to virtual address to get host address. IO accesses 114 use the corresponding iotlb value. */ 115 uintptr_t addend; 116 }; 117 /* padding to get a power of two size */ 118 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 119 }; 120} CPUTLBEntry; 121 122QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 123 124/* The IOTLB is not accessed directly inline by generated TCG code, 125 * so the CPUIOTLBEntry layout is not as critical as that of the 126 * CPUTLBEntry. (This is also why we don't want to combine the two 127 * structs into one.) 128 */ 129typedef struct CPUIOTLBEntry { 130 hwaddr addr; 131 MemTxAttrs attrs; 132} CPUIOTLBEntry; 133 134#define CPU_COMMON_TLB \ 135 /* The meaning of the MMU modes is defined in the target code. */ \ 136 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 137 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 138 CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 139 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 140 size_t tlb_flush_count; \ 141 target_ulong tlb_flush_addr; \ 142 target_ulong tlb_flush_mask; \ 143 target_ulong vtlb_index; \ 144 145#else 146 147#define CPU_COMMON_TLB 148 149#endif 150 151 152#define CPU_COMMON \ 153 /* soft mmu support */ \ 154 CPU_COMMON_TLB \ 155 156#endif 157