LXR qemu/include/hw/arm/iotkit.h

   1/*
   2 * ARM IoT Kit
   3 *
   4 * Copyright (c) 2018 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 or
   9 * (at your option) any later version.
  10 */
  11
  12/* This is a model of the Arm IoT Kit which is documented in
  13 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  14 * It contains:
  15 *  a Cortex-M33
  16 *  the IDAU
  17 *  some timers and watchdogs
  18 *  two peripheral protection controllers
  19 *  a memory protection controller
  20 *  a security controller
  21 *  a bus fabric which arranges that some parts of the address
  22 *  space are secure and non-secure aliases of each other
  23 *
  24 * QEMU interface:
  25 *  + QOM property "memory" is a MemoryRegion containing the devices provided
  26 *    by the board model.
  27 *  + QOM property "MAINCLK" is the frequency of the main system clock
  28 *  + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts
  29 *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which
  30 *    are wired to the NVIC lines 32 .. n+32
  31 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
  32 * might provide:
  33 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
  34 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
  35 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
  36 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
  37 *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
  38 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
  39 * might provide:
  40 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
  41 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
  42 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  43 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  44 *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
  45 */
  46
  47#ifndef IOTKIT_H
  48#define IOTKIT_H
  49
  50#include "hw/sysbus.h"
  51#include "hw/arm/armv7m.h"
  52#include "hw/misc/iotkit-secctl.h"
  53#include "hw/misc/tz-ppc.h"
  54#include "hw/timer/cmsdk-apb-timer.h"
  55#include "hw/misc/unimp.h"
  56#include "hw/or-irq.h"
  57#include "hw/core/split-irq.h"
  58
  59#define TYPE_IOTKIT "iotkit"
  60#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT)
  61
  62/* We have an IRQ splitter and an OR gate input for each external PPC
  63 * and the 2 internal PPCs
  64 */
  65#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
  66#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
  67
  68typedef struct IoTKit {
  69    /*< private >*/
  70    SysBusDevice parent_obj;
  71
  72    /*< public >*/
  73    ARMv7MState armv7m;
  74    IoTKitSecCtl secctl;
  75    TZPPC apb_ppc0;
  76    TZPPC apb_ppc1;
  77    CMSDKAPBTIMER timer0;
  78    CMSDKAPBTIMER timer1;
  79    qemu_or_irq ppc_irq_orgate;
  80    SplitIRQ sec_resp_splitter;
  81    SplitIRQ ppc_irq_splitter[NUM_PPCS];
  82
  83    UnimplementedDeviceState dualtimer;
  84    UnimplementedDeviceState s32ktimer;
  85
  86    MemoryRegion container;
  87    MemoryRegion alias1;
  88    MemoryRegion alias2;
  89    MemoryRegion alias3;
  90    MemoryRegion sram0;
  91
  92    qemu_irq *exp_irqs;
  93    qemu_irq ppc0_irq;
  94    qemu_irq ppc1_irq;
  95    qemu_irq sec_resp_cfg;
  96    qemu_irq sec_resp_cfg_in;
  97    qemu_irq nsc_cfg_in;
  98
  99    qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
 100
 101    uint32_t nsccfg;
 102
 103    /* Properties */
 104    MemoryRegion *board_memory;
 105    uint32_t exp_numirq;
 106    uint32_t mainclk_frq;
 107} IoTKit;
 108
 109#endif
 110