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25#ifndef HW_MISC_AUXBUS_H
26#define HW_MISC_AUXBUS_H
27
28#include "hw/qdev.h"
29
30typedef struct AUXBus AUXBus;
31typedef struct AUXSlave AUXSlave;
32typedef enum AUXCommand AUXCommand;
33typedef enum AUXReply AUXReply;
34typedef struct AUXTOI2CState AUXTOI2CState;
35
36enum AUXCommand {
37 WRITE_I2C = 0,
38 READ_I2C = 1,
39 WRITE_I2C_STATUS = 2,
40 WRITE_I2C_MOT = 4,
41 READ_I2C_MOT = 5,
42 WRITE_AUX = 8,
43 READ_AUX = 9
44};
45
46enum AUXReply {
47 AUX_I2C_ACK = 0,
48 AUX_NACK = 1,
49 AUX_DEFER = 2,
50 AUX_I2C_NACK = 4,
51 AUX_I2C_DEFER = 8
52};
53
54#define TYPE_AUX_BUS "aux-bus"
55#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
56
57struct AUXBus {
58
59 BusState qbus;
60
61
62 AUXSlave *current_dev;
63 AUXSlave *dev;
64 uint32_t last_i2c_address;
65 AUXCommand last_transaction;
66
67 AUXTOI2CState *bridge;
68
69 MemoryRegion *aux_io;
70 AddressSpace aux_addr_space;
71};
72
73#define TYPE_AUX_SLAVE "aux-slave"
74#define AUX_SLAVE(obj) \
75 OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
76
77struct AUXSlave {
78
79 DeviceState parent_obj;
80
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82 MemoryRegion *mmio;
83};
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93AUXBus *aux_init_bus(DeviceState *parent, const char *name);
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106AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
107 uint8_t len, uint8_t *data);
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116I2CBus *aux_get_i2c_bus(AUXBus *bus);
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124void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
125
126DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
127
128#endif
129