LXR qemu/include/hw/misc/iotkit-secctl.h

   1/*
   2 * ARM IoT Kit security controller
   3 *
   4 * Copyright (c) 2018 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 or
   9 * (at your option) any later version.
  10 */
  11
  12/* This is a model of the security controller which is part of the
  13 * Arm IoT Kit and documented in
  14 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  15 *
  16 * QEMU interface:
  17 *  + sysbus MMIO region 0 is the "secure privilege control block" registers
  18 *  + sysbus MMIO region 1 is the "non-secure privilege control block" registers
  19 *  + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
  20 *    should RAZ/WI or bus error
  21 *  + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value
  22 * Controlling the 2 APB PPCs in the IoTKit:
  23 *  + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
  24 *  + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
  25 *  + named GPIO outputs apb_ppc{0,1}_irq_enable
  26 *  + named GPIO outputs apb_ppc{0,1}_irq_clear
  27 *  + named GPIO inputs apb_ppc{0,1}_irq_status
  28 * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit
  29 * might provide:
  30 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
  31 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
  32 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
  33 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
  34 *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
  35 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
  36 * might provide:
  37 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
  38 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
  39 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  40 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  41 *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
  42 */
  43
  44#ifndef IOTKIT_SECCTL_H
  45#define IOTKIT_SECCTL_H
  46
  47#include "hw/sysbus.h"
  48
  49#define TYPE_IOTKIT_SECCTL "iotkit-secctl"
  50#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL)
  51
  52#define IOTS_APB_PPC0_NUM_PORTS 3
  53#define IOTS_APB_PPC1_NUM_PORTS 1
  54#define IOTS_PPC_NUM_PORTS 16
  55#define IOTS_NUM_APB_PPC 2
  56#define IOTS_NUM_APB_EXP_PPC 4
  57#define IOTS_NUM_AHB_EXP_PPC 4
  58
  59typedef struct IoTKitSecCtl IoTKitSecCtl;
  60
  61/* State and IRQ lines relating to a PPC. For the
  62 * PPCs in the IoTKit not all the IRQ lines are used.
  63 */
  64typedef struct IoTKitSecCtlPPC {
  65    qemu_irq nonsec[IOTS_PPC_NUM_PORTS];
  66    qemu_irq ap[IOTS_PPC_NUM_PORTS];
  67    qemu_irq irq_enable;
  68    qemu_irq irq_clear;
  69
  70    uint32_t ns;
  71    uint32_t sp;
  72    uint32_t nsp;
  73
  74    /* Number of ports actually present */
  75    int numports;
  76    /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */
  77    int irq_bit_offset;
  78    IoTKitSecCtl *parent;
  79} IoTKitSecCtlPPC;
  80
  81struct IoTKitSecCtl {
  82    /*< private >*/
  83    SysBusDevice parent_obj;
  84
  85    /*< public >*/
  86    qemu_irq sec_resp_cfg;
  87    qemu_irq nsc_cfg_irq;
  88
  89    MemoryRegion s_regs;
  90    MemoryRegion ns_regs;
  91
  92    uint32_t secppcintstat;
  93    uint32_t secppcinten;
  94    uint32_t secrespcfg;
  95    uint32_t nsccfg;
  96    uint32_t brginten;
  97
  98    IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
  99    IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
 100    IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC];
 101};
 102
 103#endif
 104