1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25
26#if defined(TARGET_AARCH64)
27
28# define TARGET_LONG_BITS 64
29#else
30# define TARGET_LONG_BITS 32
31#endif
32
33
34#define TCG_GUEST_DEFAULT_MO (0)
35
36#define CPUArchState struct CPUARMState
37
38#include "qemu-common.h"
39#include "cpu-qom.h"
40#include "exec/cpu-defs.h"
41
42#define EXCP_UDEF 1
43#define EXCP_SWI 2
44#define EXCP_PREFETCH_ABORT 3
45#define EXCP_DATA_ABORT 4
46#define EXCP_IRQ 5
47#define EXCP_FIQ 6
48#define EXCP_BKPT 7
49#define EXCP_EXCEPTION_EXIT 8
50#define EXCP_KERNEL_TRAP 9
51#define EXCP_HVC 11
52#define EXCP_HYP_TRAP 12
53#define EXCP_SMC 13
54#define EXCP_VIRQ 14
55#define EXCP_VFIQ 15
56#define EXCP_SEMIHOST 16
57#define EXCP_NOCP 17
58#define EXCP_INVSTATE 18
59
60
61#define ARMV7M_EXCP_RESET 1
62#define ARMV7M_EXCP_NMI 2
63#define ARMV7M_EXCP_HARD 3
64#define ARMV7M_EXCP_MEM 4
65#define ARMV7M_EXCP_BUS 5
66#define ARMV7M_EXCP_USAGE 6
67#define ARMV7M_EXCP_SECURE 7
68#define ARMV7M_EXCP_SVC 11
69#define ARMV7M_EXCP_DEBUG 12
70#define ARMV7M_EXCP_PENDSV 14
71#define ARMV7M_EXCP_SYSTICK 15
72
73
74
75
76
77
78
79
80
81
82enum {
83 M_REG_NS = 0,
84 M_REG_S = 1,
85 M_REG_NUM_BANKS = 2,
86};
87
88
89#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
90#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
91#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
92
93
94
95
96
97
98
99#ifdef HOST_WORDS_BIGENDIAN
100#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
101#define offsetofhigh32(S, M) offsetof(S, M)
102#else
103#define offsetoflow32(S, M) offsetof(S, M)
104#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
105#endif
106
107
108#define ARM_CPU_IRQ 0
109#define ARM_CPU_FIQ 1
110#define ARM_CPU_VIRQ 2
111#define ARM_CPU_VFIQ 3
112
113#define NB_MMU_MODES 8
114
115
116
117
118#define TARGET_INSN_START_EXTRA_WORDS 2
119
120
121
122
123
124
125#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
126#define ARM_INSN_START_WORD2_SHIFT 14
127
128
129
130
131
132
133
134
135
136
137typedef struct ARMGenericTimer {
138 uint64_t cval;
139 uint64_t ctl;
140} ARMGenericTimer;
141
142#define GTIMER_PHYS 0
143#define GTIMER_VIRT 1
144#define GTIMER_HYP 2
145#define GTIMER_SEC 3
146#define NUM_GTIMERS 4
147
148typedef struct {
149 uint64_t raw_tcr;
150 uint32_t mask;
151 uint32_t base_mask;
152} TCR;
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180#ifdef TARGET_AARCH64
181# define ARM_MAX_VQ 16
182#else
183# define ARM_MAX_VQ 1
184#endif
185
186typedef struct ARMVectorReg {
187 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
188} ARMVectorReg;
189
190
191#ifdef TARGET_AARCH64
192typedef struct ARMPredicateReg {
193 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
194} ARMPredicateReg;
195#endif
196
197
198typedef struct CPUARMState {
199
200 uint32_t regs[16];
201
202
203
204
205
206
207 uint64_t xregs[32];
208 uint64_t pc;
209
210
211
212
213
214
215
216
217
218
219
220 uint32_t pstate;
221 uint32_t aarch64;
222
223
224
225
226 uint32_t uncached_cpsr;
227 uint32_t spsr;
228
229
230 uint64_t banked_spsr[8];
231 uint32_t banked_r13[8];
232 uint32_t banked_r14[8];
233
234
235 uint32_t usr_regs[5];
236 uint32_t fiq_regs[5];
237
238
239 uint32_t CF;
240 uint32_t VF;
241 uint32_t NF;
242 uint32_t ZF;
243 uint32_t QF;
244 uint32_t GE;
245 uint32_t thumb;
246 uint32_t condexec_bits;
247 uint64_t daif;
248
249 uint64_t elr_el[4];
250 uint64_t sp_el[4];
251
252
253 struct {
254 uint32_t c0_cpuid;
255 union {
256 struct {
257 uint64_t _unused_csselr0;
258 uint64_t csselr_ns;
259 uint64_t _unused_csselr1;
260 uint64_t csselr_s;
261 };
262 uint64_t csselr_el[4];
263 };
264 union {
265 struct {
266 uint64_t _unused_sctlr;
267 uint64_t sctlr_ns;
268 uint64_t hsctlr;
269 uint64_t sctlr_s;
270 };
271 uint64_t sctlr_el[4];
272 };
273 uint64_t cpacr_el1;
274 uint64_t cptr_el[4];
275 uint32_t c1_xscaleauxcr;
276 uint64_t sder;
277 uint32_t nsacr;
278 union {
279 struct {
280 uint64_t _unused_ttbr0_0;
281 uint64_t ttbr0_ns;
282 uint64_t _unused_ttbr0_1;
283 uint64_t ttbr0_s;
284 };
285 uint64_t ttbr0_el[4];
286 };
287 union {
288 struct {
289 uint64_t _unused_ttbr1_0;
290 uint64_t ttbr1_ns;
291 uint64_t _unused_ttbr1_1;
292 uint64_t ttbr1_s;
293 };
294 uint64_t ttbr1_el[4];
295 };
296 uint64_t vttbr_el2;
297
298 TCR tcr_el[4];
299 TCR vtcr_el2;
300 uint32_t c2_data;
301 uint32_t c2_insn;
302 union {
303
304
305 struct {
306 uint64_t dacr_ns;
307 uint64_t dacr_s;
308 };
309 struct {
310 uint64_t dacr32_el2;
311 };
312 };
313 uint32_t pmsav5_data_ap;
314 uint32_t pmsav5_insn_ap;
315 uint64_t hcr_el2;
316 uint64_t scr_el3;
317 union {
318 struct {
319 uint64_t ifsr_ns;
320 uint64_t ifsr_s;
321 };
322 struct {
323 uint64_t ifsr32_el2;
324 };
325 };
326 union {
327 struct {
328 uint64_t _unused_dfsr;
329 uint64_t dfsr_ns;
330 uint64_t hsr;
331 uint64_t dfsr_s;
332 };
333 uint64_t esr_el[4];
334 };
335 uint32_t c6_region[8];
336 union {
337 struct {
338 uint64_t _unused_far0;
339#ifdef HOST_WORDS_BIGENDIAN
340 uint32_t ifar_ns;
341 uint32_t dfar_ns;
342 uint32_t ifar_s;
343 uint32_t dfar_s;
344#else
345 uint32_t dfar_ns;
346 uint32_t ifar_ns;
347 uint32_t dfar_s;
348 uint32_t ifar_s;
349#endif
350 uint64_t _unused_far3;
351 };
352 uint64_t far_el[4];
353 };
354 uint64_t hpfar_el2;
355 uint64_t hstr_el2;
356 union {
357 struct {
358 uint64_t _unused_par_0;
359 uint64_t par_ns;
360 uint64_t _unused_par_1;
361 uint64_t par_s;
362 };
363 uint64_t par_el[4];
364 };
365
366 uint32_t c9_insn;
367 uint32_t c9_data;
368 uint64_t c9_pmcr;
369 uint64_t c9_pmcnten;
370 uint32_t c9_pmovsr;
371 uint32_t c9_pmuserenr;
372 uint64_t c9_pmselr;
373 uint64_t c9_pminten;
374 union {
375 struct {
376#ifdef HOST_WORDS_BIGENDIAN
377 uint64_t _unused_mair_0;
378 uint32_t mair1_ns;
379 uint32_t mair0_ns;
380 uint64_t _unused_mair_1;
381 uint32_t mair1_s;
382 uint32_t mair0_s;
383#else
384 uint64_t _unused_mair_0;
385 uint32_t mair0_ns;
386 uint32_t mair1_ns;
387 uint64_t _unused_mair_1;
388 uint32_t mair0_s;
389 uint32_t mair1_s;
390#endif
391 };
392 uint64_t mair_el[4];
393 };
394 union {
395 struct {
396 uint64_t _unused_vbar;
397 uint64_t vbar_ns;
398 uint64_t hvbar;
399 uint64_t vbar_s;
400 };
401 uint64_t vbar_el[4];
402 };
403 uint32_t mvbar;
404 struct {
405 uint32_t fcseidr_ns;
406 uint32_t fcseidr_s;
407 };
408 union {
409 struct {
410 uint64_t _unused_contextidr_0;
411 uint64_t contextidr_ns;
412 uint64_t _unused_contextidr_1;
413 uint64_t contextidr_s;
414 };
415 uint64_t contextidr_el[4];
416 };
417 union {
418 struct {
419 uint64_t tpidrurw_ns;
420 uint64_t tpidrprw_ns;
421 uint64_t htpidr;
422 uint64_t _tpidr_el3;
423 };
424 uint64_t tpidr_el[4];
425 };
426
427 uint64_t tpidrurw_s;
428 uint64_t tpidrprw_s;
429 uint64_t tpidruro_s;
430
431 union {
432 uint64_t tpidruro_ns;
433 uint64_t tpidrro_el[1];
434 };
435 uint64_t c14_cntfrq;
436 uint64_t c14_cntkctl;
437 uint32_t cnthctl_el2;
438 uint64_t cntvoff_el2;
439 ARMGenericTimer c14_timer[NUM_GTIMERS];
440 uint32_t c15_cpar;
441 uint32_t c15_ticonfig;
442 uint32_t c15_i_max;
443 uint32_t c15_i_min;
444 uint32_t c15_threadid;
445 uint32_t c15_config_base_address;
446 uint32_t c15_diagnostic;
447 uint32_t c15_power_diagnostic;
448 uint32_t c15_power_control;
449 uint64_t dbgbvr[16];
450 uint64_t dbgbcr[16];
451 uint64_t dbgwvr[16];
452 uint64_t dbgwcr[16];
453 uint64_t mdscr_el1;
454 uint64_t oslsr_el1;
455 uint64_t mdcr_el2;
456 uint64_t mdcr_el3;
457
458
459
460 uint64_t c15_ccnt;
461 uint64_t pmccfiltr_el0;
462 uint64_t vpidr_el2;
463 uint64_t vmpidr_el2;
464 } cp15;
465
466 struct {
467
468
469
470
471
472
473
474
475
476
477
478 uint32_t other_sp;
479 uint32_t other_ss_msp;
480 uint32_t other_ss_psp;
481 uint32_t vecbase[M_REG_NUM_BANKS];
482 uint32_t basepri[M_REG_NUM_BANKS];
483 uint32_t control[M_REG_NUM_BANKS];
484 uint32_t ccr[M_REG_NUM_BANKS];
485 uint32_t cfsr[M_REG_NUM_BANKS];
486 uint32_t hfsr;
487 uint32_t dfsr;
488 uint32_t sfsr;
489 uint32_t mmfar[M_REG_NUM_BANKS];
490 uint32_t bfar;
491 uint32_t sfar;
492 unsigned mpu_ctrl[M_REG_NUM_BANKS];
493 int exception;
494 uint32_t primask[M_REG_NUM_BANKS];
495 uint32_t faultmask[M_REG_NUM_BANKS];
496 uint32_t aircr;
497 uint32_t secure;
498 uint32_t csselr[M_REG_NUM_BANKS];
499 uint32_t scr[M_REG_NUM_BANKS];
500 uint32_t msplim[M_REG_NUM_BANKS];
501 uint32_t psplim[M_REG_NUM_BANKS];
502 } v7m;
503
504
505
506
507
508
509
510 struct {
511 uint32_t syndrome;
512 uint32_t fsr;
513 uint64_t vaddress;
514 uint32_t target_el;
515
516
517
518 } exception;
519
520
521 uint32_t teecr;
522 uint32_t teehbr;
523
524
525 struct {
526 ARMVectorReg zregs[32];
527
528#ifdef TARGET_AARCH64
529
530 ARMPredicateReg pregs[17];
531#endif
532
533 uint32_t xregs[16];
534
535 int vec_len;
536 int vec_stride;
537
538
539 uint32_t scratch[8];
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562 float_status fp_status;
563 float_status fp_status_f16;
564 float_status standard_fp_status;
565
566
567 uint64_t zcr_el[4];
568 } vfp;
569 uint64_t exclusive_addr;
570 uint64_t exclusive_val;
571 uint64_t exclusive_high;
572
573
574 struct {
575 uint64_t regs[16];
576 uint64_t val;
577
578 uint32_t cregs[16];
579 } iwmmxt;
580
581#if defined(CONFIG_USER_ONLY)
582
583 int eabi;
584#endif
585
586 struct CPUBreakpoint *cpu_breakpoint[16];
587 struct CPUWatchpoint *cpu_watchpoint[16];
588
589
590 struct {} end_reset_fields;
591
592 CPU_COMMON
593
594
595
596
597 uint64_t features;
598
599
600 struct {
601 uint32_t *drbar;
602 uint32_t *drsr;
603 uint32_t *dracr;
604 uint32_t rnr[M_REG_NUM_BANKS];
605 } pmsav7;
606
607
608 struct {
609
610
611
612
613
614 uint32_t *rbar[M_REG_NUM_BANKS];
615 uint32_t *rlar[M_REG_NUM_BANKS];
616 uint32_t mair0[M_REG_NUM_BANKS];
617 uint32_t mair1[M_REG_NUM_BANKS];
618 } pmsav8;
619
620
621 struct {
622 uint32_t *rbar;
623 uint32_t *rlar;
624 uint32_t rnr;
625 uint32_t ctrl;
626 } sau;
627
628 void *nvic;
629 const struct arm_boot_info *boot_info;
630
631 void *gicv3state;
632} CPUARMState;
633
634
635
636
637
638
639typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
640
641
642
643
644typedef enum ARMPSCIState {
645 PSCI_ON = 0,
646 PSCI_OFF = 1,
647 PSCI_ON_PENDING = 2
648} ARMPSCIState;
649
650
651
652
653
654
655
656struct ARMCPU {
657
658 CPUState parent_obj;
659
660
661 CPUARMState env;
662
663
664 GHashTable *cp_regs;
665
666
667
668
669
670
671
672 uint64_t *cpreg_indexes;
673
674 uint64_t *cpreg_values;
675
676 int32_t cpreg_array_len;
677
678
679
680
681 uint64_t *cpreg_vmstate_indexes;
682 uint64_t *cpreg_vmstate_values;
683 int32_t cpreg_vmstate_array_len;
684
685
686 QEMUTimer *gt_timer[NUM_GTIMERS];
687
688 qemu_irq gt_timer_outputs[NUM_GTIMERS];
689
690 qemu_irq gicv3_maintenance_interrupt;
691
692 qemu_irq pmu_interrupt;
693
694
695 MemoryRegion *secure_memory;
696
697
698 Object *idau;
699
700
701 const char *dtb_compatible;
702
703
704
705
706
707 uint32_t psci_version;
708
709
710 bool start_powered_off;
711
712
713 ARMPSCIState power_state;
714
715
716 bool has_el2;
717
718 bool has_el3;
719
720 bool has_pmu;
721
722
723 bool has_mpu;
724
725 uint32_t pmsav7_dregion;
726
727 uint32_t sau_sregion;
728
729
730
731
732 uint32_t psci_conduit;
733
734
735 uint32_t init_svtor;
736
737
738
739
740 uint32_t kvm_target;
741
742
743 uint32_t kvm_init_features[7];
744
745
746 bool mp_is_up;
747
748
749
750
751 bool host_cpu_probe_failed;
752
753
754
755
756 int32_t core_count;
757
758
759
760
761
762
763
764
765
766
767
768 uint32_t midr;
769 uint32_t revidr;
770 uint32_t reset_fpsid;
771 uint32_t mvfr0;
772 uint32_t mvfr1;
773 uint32_t mvfr2;
774 uint32_t ctr;
775 uint32_t reset_sctlr;
776 uint32_t id_pfr0;
777 uint32_t id_pfr1;
778 uint32_t id_dfr0;
779 uint32_t pmceid0;
780 uint32_t pmceid1;
781 uint32_t id_afr0;
782 uint32_t id_mmfr0;
783 uint32_t id_mmfr1;
784 uint32_t id_mmfr2;
785 uint32_t id_mmfr3;
786 uint32_t id_mmfr4;
787 uint32_t id_isar0;
788 uint32_t id_isar1;
789 uint32_t id_isar2;
790 uint32_t id_isar3;
791 uint32_t id_isar4;
792 uint32_t id_isar5;
793 uint64_t id_aa64pfr0;
794 uint64_t id_aa64pfr1;
795 uint64_t id_aa64dfr0;
796 uint64_t id_aa64dfr1;
797 uint64_t id_aa64afr0;
798 uint64_t id_aa64afr1;
799 uint64_t id_aa64isar0;
800 uint64_t id_aa64isar1;
801 uint64_t id_aa64mmfr0;
802 uint64_t id_aa64mmfr1;
803 uint32_t dbgdidr;
804 uint32_t clidr;
805 uint64_t mp_affinity;
806
807
808
809 uint32_t ccsidr[16];
810 uint64_t reset_cbar;
811 uint32_t reset_auxcr;
812 bool reset_hivecs;
813
814 uint32_t dcz_blocksize;
815 uint64_t rvbar;
816
817
818 int gic_num_lrs;
819 int gic_vpribits;
820 int gic_vprebits;
821
822
823
824
825
826
827 bool cfgend;
828
829 ARMELChangeHook *el_change_hook;
830 void *el_change_hook_opaque;
831
832 int32_t node_id;
833
834
835 uint8_t device_irq_level;
836};
837
838static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
839{
840 return container_of(env, ARMCPU, env);
841}
842
843uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
844
845#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
846
847#define ENV_OFFSET offsetof(ARMCPU, env)
848
849#ifndef CONFIG_USER_ONLY
850extern const struct VMStateDescription vmstate_arm_cpu;
851#endif
852
853void arm_cpu_do_interrupt(CPUState *cpu);
854void arm_v7m_cpu_do_interrupt(CPUState *cpu);
855bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
856
857void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
858 int flags);
859
860hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
861 MemTxAttrs *attrs);
862
863int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
864int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
865
866int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
867 int cpuid, void *opaque);
868int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
869 int cpuid, void *opaque);
870
871#ifdef TARGET_AARCH64
872int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
873int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
874void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
875#endif
876
877target_ulong do_arm_semihosting(CPUARMState *env);
878void aarch64_sync_32_to_64(CPUARMState *env);
879void aarch64_sync_64_to_32(CPUARMState *env);
880
881static inline bool is_a64(CPUARMState *env)
882{
883 return env->aarch64;
884}
885
886
887
888
889int cpu_arm_signal_handler(int host_signum, void *pinfo,
890 void *puc);
891
892
893
894
895
896
897
898
899
900
901void pmccntr_sync(CPUARMState *env);
902
903
904
905
906
907
908
909#define SCTLR_M (1U << 0)
910#define SCTLR_A (1U << 1)
911#define SCTLR_C (1U << 2)
912#define SCTLR_W (1U << 3)
913#define SCTLR_SA (1U << 3)
914#define SCTLR_P (1U << 4)
915#define SCTLR_SA0 (1U << 4)
916#define SCTLR_D (1U << 5)
917#define SCTLR_CP15BEN (1U << 5)
918#define SCTLR_L (1U << 6)
919#define SCTLR_B (1U << 7)
920#define SCTLR_ITD (1U << 7)
921#define SCTLR_S (1U << 8)
922#define SCTLR_SED (1U << 8)
923#define SCTLR_R (1U << 9)
924#define SCTLR_UMA (1U << 9)
925#define SCTLR_F (1U << 10)
926#define SCTLR_SW (1U << 10)
927#define SCTLR_Z (1U << 11)
928#define SCTLR_I (1U << 12)
929#define SCTLR_V (1U << 13)
930#define SCTLR_RR (1U << 14)
931#define SCTLR_DZE (1U << 14)
932#define SCTLR_L4 (1U << 15)
933#define SCTLR_UCT (1U << 15)
934#define SCTLR_DT (1U << 16)
935#define SCTLR_nTWI (1U << 16)
936#define SCTLR_HA (1U << 17)
937#define SCTLR_BR (1U << 17)
938#define SCTLR_IT (1U << 18)
939#define SCTLR_nTWE (1U << 18)
940#define SCTLR_WXN (1U << 19)
941#define SCTLR_ST (1U << 20)
942#define SCTLR_UWXN (1U << 20)
943#define SCTLR_FI (1U << 21)
944#define SCTLR_U (1U << 22)
945#define SCTLR_XP (1U << 23)
946#define SCTLR_VE (1U << 24)
947#define SCTLR_E0E (1U << 24)
948#define SCTLR_EE (1U << 25)
949#define SCTLR_L2 (1U << 26)
950#define SCTLR_UCI (1U << 26)
951#define SCTLR_NMFI (1U << 27)
952#define SCTLR_TRE (1U << 28)
953#define SCTLR_AFE (1U << 29)
954#define SCTLR_TE (1U << 30)
955
956#define CPTR_TCPAC (1U << 31)
957#define CPTR_TTA (1U << 20)
958#define CPTR_TFP (1U << 10)
959#define CPTR_TZ (1U << 8)
960#define CPTR_EZ (1U << 8)
961
962#define MDCR_EPMAD (1U << 21)
963#define MDCR_EDAD (1U << 20)
964#define MDCR_SPME (1U << 17)
965#define MDCR_SDD (1U << 16)
966#define MDCR_SPD (3U << 14)
967#define MDCR_TDRA (1U << 11)
968#define MDCR_TDOSA (1U << 10)
969#define MDCR_TDA (1U << 9)
970#define MDCR_TDE (1U << 8)
971#define MDCR_HPME (1U << 7)
972#define MDCR_TPM (1U << 6)
973#define MDCR_TPMCR (1U << 5)
974
975
976#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
977
978#define CPSR_M (0x1fU)
979#define CPSR_T (1U << 5)
980#define CPSR_F (1U << 6)
981#define CPSR_I (1U << 7)
982#define CPSR_A (1U << 8)
983#define CPSR_E (1U << 9)
984#define CPSR_IT_2_7 (0xfc00U)
985#define CPSR_GE (0xfU << 16)
986#define CPSR_IL (1U << 20)
987
988
989
990
991
992#define CPSR_RESERVED (0x7U << 21)
993#define CPSR_J (1U << 24)
994#define CPSR_IT_0_1 (3U << 25)
995#define CPSR_Q (1U << 27)
996#define CPSR_V (1U << 28)
997#define CPSR_C (1U << 29)
998#define CPSR_Z (1U << 30)
999#define CPSR_N (1U << 31)
1000#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1001#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1002
1003#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1004#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1005 | CPSR_NZCV)
1006
1007#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1008
1009#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1010
1011#define CPSR_ERET_MASK (~CPSR_RESERVED)
1012
1013
1014#define XPSR_EXCP 0x1ffU
1015#define XPSR_SPREALIGN (1U << 9)
1016#define XPSR_IT_2_7 CPSR_IT_2_7
1017#define XPSR_GE CPSR_GE
1018#define XPSR_SFPA (1U << 20)
1019#define XPSR_T (1U << 24)
1020#define XPSR_IT_0_1 CPSR_IT_0_1
1021#define XPSR_Q CPSR_Q
1022#define XPSR_V CPSR_V
1023#define XPSR_C CPSR_C
1024#define XPSR_Z CPSR_Z
1025#define XPSR_N CPSR_N
1026#define XPSR_NZCV CPSR_NZCV
1027#define XPSR_IT CPSR_IT
1028
1029#define TTBCR_N (7U << 0)
1030#define TTBCR_T0SZ (7U << 0)
1031#define TTBCR_PD0 (1U << 4)
1032#define TTBCR_PD1 (1U << 5)
1033#define TTBCR_EPD0 (1U << 7)
1034#define TTBCR_IRGN0 (3U << 8)
1035#define TTBCR_ORGN0 (3U << 10)
1036#define TTBCR_SH0 (3U << 12)
1037#define TTBCR_T1SZ (3U << 16)
1038#define TTBCR_A1 (1U << 22)
1039#define TTBCR_EPD1 (1U << 23)
1040#define TTBCR_IRGN1 (3U << 24)
1041#define TTBCR_ORGN1 (3U << 26)
1042#define TTBCR_SH1 (1U << 28)
1043#define TTBCR_EAE (1U << 31)
1044
1045
1046
1047
1048
1049#define PSTATE_SP (1U)
1050#define PSTATE_M (0xFU)
1051#define PSTATE_nRW (1U << 4)
1052#define PSTATE_F (1U << 6)
1053#define PSTATE_I (1U << 7)
1054#define PSTATE_A (1U << 8)
1055#define PSTATE_D (1U << 9)
1056#define PSTATE_IL (1U << 20)
1057#define PSTATE_SS (1U << 21)
1058#define PSTATE_V (1U << 28)
1059#define PSTATE_C (1U << 29)
1060#define PSTATE_Z (1U << 30)
1061#define PSTATE_N (1U << 31)
1062#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1063#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1064#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
1065
1066#define PSTATE_MODE_EL3h 13
1067#define PSTATE_MODE_EL3t 12
1068#define PSTATE_MODE_EL2h 9
1069#define PSTATE_MODE_EL2t 8
1070#define PSTATE_MODE_EL1h 5
1071#define PSTATE_MODE_EL1t 4
1072#define PSTATE_MODE_EL0t 0
1073
1074
1075
1076
1077void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1078
1079
1080static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1081{
1082 return (el << 2) | handler;
1083}
1084
1085
1086
1087
1088
1089static inline uint32_t pstate_read(CPUARMState *env)
1090{
1091 int ZF;
1092
1093 ZF = (env->ZF == 0);
1094 return (env->NF & 0x80000000) | (ZF << 30)
1095 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1096 | env->pstate | env->daif;
1097}
1098
1099static inline void pstate_write(CPUARMState *env, uint32_t val)
1100{
1101 env->ZF = (~val) & PSTATE_Z;
1102 env->NF = val;
1103 env->CF = (val >> 29) & 1;
1104 env->VF = (val << 3) & 0x80000000;
1105 env->daif = val & PSTATE_DAIF;
1106 env->pstate = val & ~CACHED_PSTATE_BITS;
1107}
1108
1109
1110uint32_t cpsr_read(CPUARMState *env);
1111
1112typedef enum CPSRWriteType {
1113 CPSRWriteByInstr = 0,
1114 CPSRWriteExceptionReturn = 1,
1115 CPSRWriteRaw = 2,
1116 CPSRWriteByGDBStub = 3,
1117} CPSRWriteType;
1118
1119
1120void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1121 CPSRWriteType write_type);
1122
1123
1124static inline uint32_t xpsr_read(CPUARMState *env)
1125{
1126 int ZF;
1127 ZF = (env->ZF == 0);
1128 return (env->NF & 0x80000000) | (ZF << 30)
1129 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1130 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1131 | ((env->condexec_bits & 0xfc) << 8)
1132 | env->v7m.exception;
1133}
1134
1135
1136static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1137{
1138 if (mask & XPSR_NZCV) {
1139 env->ZF = (~val) & XPSR_Z;
1140 env->NF = val;
1141 env->CF = (val >> 29) & 1;
1142 env->VF = (val << 3) & 0x80000000;
1143 }
1144 if (mask & XPSR_Q) {
1145 env->QF = ((val & XPSR_Q) != 0);
1146 }
1147 if (mask & XPSR_T) {
1148 env->thumb = ((val & XPSR_T) != 0);
1149 }
1150 if (mask & XPSR_IT_0_1) {
1151 env->condexec_bits &= ~3;
1152 env->condexec_bits |= (val >> 25) & 3;
1153 }
1154 if (mask & XPSR_IT_2_7) {
1155 env->condexec_bits &= 3;
1156 env->condexec_bits |= (val >> 8) & 0xfc;
1157 }
1158 if (mask & XPSR_EXCP) {
1159
1160 write_v7m_exception(env, val & XPSR_EXCP);
1161 }
1162}
1163
1164#define HCR_VM (1ULL << 0)
1165#define HCR_SWIO (1ULL << 1)
1166#define HCR_PTW (1ULL << 2)
1167#define HCR_FMO (1ULL << 3)
1168#define HCR_IMO (1ULL << 4)
1169#define HCR_AMO (1ULL << 5)
1170#define HCR_VF (1ULL << 6)
1171#define HCR_VI (1ULL << 7)
1172#define HCR_VSE (1ULL << 8)
1173#define HCR_FB (1ULL << 9)
1174#define HCR_BSU_MASK (3ULL << 10)
1175#define HCR_DC (1ULL << 12)
1176#define HCR_TWI (1ULL << 13)
1177#define HCR_TWE (1ULL << 14)
1178#define HCR_TID0 (1ULL << 15)
1179#define HCR_TID1 (1ULL << 16)
1180#define HCR_TID2 (1ULL << 17)
1181#define HCR_TID3 (1ULL << 18)
1182#define HCR_TSC (1ULL << 19)
1183#define HCR_TIDCP (1ULL << 20)
1184#define HCR_TACR (1ULL << 21)
1185#define HCR_TSW (1ULL << 22)
1186#define HCR_TPC (1ULL << 23)
1187#define HCR_TPU (1ULL << 24)
1188#define HCR_TTLB (1ULL << 25)
1189#define HCR_TVM (1ULL << 26)
1190#define HCR_TGE (1ULL << 27)
1191#define HCR_TDZ (1ULL << 28)
1192#define HCR_HCD (1ULL << 29)
1193#define HCR_TRVM (1ULL << 30)
1194#define HCR_RW (1ULL << 31)
1195#define HCR_CD (1ULL << 32)
1196#define HCR_ID (1ULL << 33)
1197#define HCR_MASK ((1ULL << 34) - 1)
1198
1199#define SCR_NS (1U << 0)
1200#define SCR_IRQ (1U << 1)
1201#define SCR_FIQ (1U << 2)
1202#define SCR_EA (1U << 3)
1203#define SCR_FW (1U << 4)
1204#define SCR_AW (1U << 5)
1205#define SCR_NET (1U << 6)
1206#define SCR_SMD (1U << 7)
1207#define SCR_HCE (1U << 8)
1208#define SCR_SIF (1U << 9)
1209#define SCR_RW (1U << 10)
1210#define SCR_ST (1U << 11)
1211#define SCR_TWI (1U << 12)
1212#define SCR_TWE (1U << 13)
1213#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1214#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1215
1216
1217uint32_t vfp_get_fpscr(CPUARMState *env);
1218void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1219
1220
1221
1222
1223
1224
1225
1226
1227#define FPSR_MASK 0xf800009f
1228#define FPCR_MASK 0x07f79f00
1229
1230#define FPCR_FZ16 (1 << 19)
1231#define FPCR_FZ (1 << 24)
1232#define FPCR_DN (1 << 25)
1233
1234static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1235{
1236 return vfp_get_fpscr(env) & FPSR_MASK;
1237}
1238
1239static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1240{
1241 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1242 vfp_set_fpscr(env, new_fpscr);
1243}
1244
1245static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1246{
1247 return vfp_get_fpscr(env) & FPCR_MASK;
1248}
1249
1250static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1251{
1252 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1253 vfp_set_fpscr(env, new_fpscr);
1254}
1255
1256enum arm_cpu_mode {
1257 ARM_CPU_MODE_USR = 0x10,
1258 ARM_CPU_MODE_FIQ = 0x11,
1259 ARM_CPU_MODE_IRQ = 0x12,
1260 ARM_CPU_MODE_SVC = 0x13,
1261 ARM_CPU_MODE_MON = 0x16,
1262 ARM_CPU_MODE_ABT = 0x17,
1263 ARM_CPU_MODE_HYP = 0x1a,
1264 ARM_CPU_MODE_UND = 0x1b,
1265 ARM_CPU_MODE_SYS = 0x1f
1266};
1267
1268
1269#define ARM_VFP_FPSID 0
1270#define ARM_VFP_FPSCR 1
1271#define ARM_VFP_MVFR2 5
1272#define ARM_VFP_MVFR1 6
1273#define ARM_VFP_MVFR0 7
1274#define ARM_VFP_FPEXC 8
1275#define ARM_VFP_FPINST 9
1276#define ARM_VFP_FPINST2 10
1277
1278
1279#define ARM_IWMMXT_wCID 0
1280#define ARM_IWMMXT_wCon 1
1281#define ARM_IWMMXT_wCSSF 2
1282#define ARM_IWMMXT_wCASF 3
1283#define ARM_IWMMXT_wCGR0 8
1284#define ARM_IWMMXT_wCGR1 9
1285#define ARM_IWMMXT_wCGR2 10
1286#define ARM_IWMMXT_wCGR3 11
1287
1288
1289FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1290FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1291FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1292FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1293FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1294FIELD(V7M_CCR, STKALIGN, 9, 1)
1295FIELD(V7M_CCR, DC, 16, 1)
1296FIELD(V7M_CCR, IC, 17, 1)
1297
1298
1299FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1300FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1301FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1302FIELD(V7M_SCR, SEVONPEND, 4, 1)
1303
1304
1305FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1306FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1307FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1308FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1309FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1310FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1311FIELD(V7M_AIRCR, PRIS, 14, 1)
1312FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1313FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1314
1315
1316FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1317FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1318FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1319FIELD(V7M_CFSR, MSTKERR, 4, 1)
1320FIELD(V7M_CFSR, MLSPERR, 5, 1)
1321FIELD(V7M_CFSR, MMARVALID, 7, 1)
1322
1323
1324FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1325FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1326FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1327FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1328FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1329FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1330FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1331
1332
1333FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1334FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1335FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1336FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1337FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1338FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1339
1340
1341FIELD(V7M_CFSR, MMFSR, 0, 8)
1342FIELD(V7M_CFSR, BFSR, 8, 8)
1343FIELD(V7M_CFSR, UFSR, 16, 16)
1344
1345
1346FIELD(V7M_HFSR, VECTTBL, 1, 1)
1347FIELD(V7M_HFSR, FORCED, 30, 1)
1348FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1349
1350
1351FIELD(V7M_DFSR, HALTED, 0, 1)
1352FIELD(V7M_DFSR, BKPT, 1, 1)
1353FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1354FIELD(V7M_DFSR, VCATCH, 3, 1)
1355FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1356
1357
1358FIELD(V7M_SFSR, INVEP, 0, 1)
1359FIELD(V7M_SFSR, INVIS, 1, 1)
1360FIELD(V7M_SFSR, INVER, 2, 1)
1361FIELD(V7M_SFSR, AUVIOL, 3, 1)
1362FIELD(V7M_SFSR, INVTRAN, 4, 1)
1363FIELD(V7M_SFSR, LSPERR, 5, 1)
1364FIELD(V7M_SFSR, SFARVALID, 6, 1)
1365FIELD(V7M_SFSR, LSERR, 7, 1)
1366
1367
1368FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1369FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1370FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1371
1372
1373FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1374FIELD(V7M_CLIDR, LOUIS, 21, 3)
1375FIELD(V7M_CLIDR, LOC, 24, 3)
1376FIELD(V7M_CLIDR, LOUU, 27, 3)
1377FIELD(V7M_CLIDR, ICB, 30, 2)
1378
1379FIELD(V7M_CSSELR, IND, 0, 1)
1380FIELD(V7M_CSSELR, LEVEL, 1, 3)
1381
1382
1383
1384
1385FIELD(V7M_CSSELR, INDEX, 0, 4)
1386
1387QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1388
1389
1390
1391
1392
1393enum arm_features {
1394 ARM_FEATURE_VFP,
1395 ARM_FEATURE_AUXCR,
1396 ARM_FEATURE_XSCALE,
1397 ARM_FEATURE_IWMMXT,
1398 ARM_FEATURE_V6,
1399 ARM_FEATURE_V6K,
1400 ARM_FEATURE_V7,
1401 ARM_FEATURE_THUMB2,
1402 ARM_FEATURE_PMSA,
1403 ARM_FEATURE_VFP3,
1404 ARM_FEATURE_VFP_FP16,
1405 ARM_FEATURE_NEON,
1406 ARM_FEATURE_THUMB_DIV,
1407 ARM_FEATURE_M,
1408 ARM_FEATURE_OMAPCP,
1409 ARM_FEATURE_THUMB2EE,
1410 ARM_FEATURE_V7MP,
1411 ARM_FEATURE_V4T,
1412 ARM_FEATURE_V5,
1413 ARM_FEATURE_STRONGARM,
1414 ARM_FEATURE_VAPA,
1415 ARM_FEATURE_ARM_DIV,
1416 ARM_FEATURE_VFP4,
1417 ARM_FEATURE_GENERIC_TIMER,
1418 ARM_FEATURE_MVFR,
1419 ARM_FEATURE_DUMMY_C15_REGS,
1420 ARM_FEATURE_CACHE_TEST_CLEAN,
1421 ARM_FEATURE_CACHE_DIRTY_REG,
1422 ARM_FEATURE_CACHE_BLOCK_OPS,
1423 ARM_FEATURE_MPIDR,
1424 ARM_FEATURE_PXN,
1425 ARM_FEATURE_LPAE,
1426 ARM_FEATURE_V8,
1427 ARM_FEATURE_AARCH64,
1428 ARM_FEATURE_V8_AES,
1429 ARM_FEATURE_CBAR,
1430 ARM_FEATURE_CRC,
1431 ARM_FEATURE_CBAR_RO,
1432 ARM_FEATURE_EL2,
1433 ARM_FEATURE_EL3,
1434 ARM_FEATURE_V8_SHA1,
1435 ARM_FEATURE_V8_SHA256,
1436 ARM_FEATURE_V8_PMULL,
1437 ARM_FEATURE_THUMB_DSP,
1438 ARM_FEATURE_PMU,
1439 ARM_FEATURE_VBAR,
1440 ARM_FEATURE_M_SECURITY,
1441 ARM_FEATURE_JAZELLE,
1442 ARM_FEATURE_SVE,
1443 ARM_FEATURE_V8_SHA512,
1444 ARM_FEATURE_V8_SHA3,
1445 ARM_FEATURE_V8_SM3,
1446 ARM_FEATURE_V8_SM4,
1447 ARM_FEATURE_V8_RDM,
1448 ARM_FEATURE_V8_FP16,
1449 ARM_FEATURE_V8_FCMA,
1450};
1451
1452static inline int arm_feature(CPUARMState *env, int feature)
1453{
1454 return (env->features & (1ULL << feature)) != 0;
1455}
1456
1457#if !defined(CONFIG_USER_ONLY)
1458
1459
1460
1461
1462
1463
1464static inline bool arm_is_secure_below_el3(CPUARMState *env)
1465{
1466 if (arm_feature(env, ARM_FEATURE_EL3)) {
1467 return !(env->cp15.scr_el3 & SCR_NS);
1468 } else {
1469
1470
1471
1472 return false;
1473 }
1474}
1475
1476
1477static inline bool arm_is_el3_or_mon(CPUARMState *env)
1478{
1479 if (arm_feature(env, ARM_FEATURE_EL3)) {
1480 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1481
1482 return true;
1483 } else if (!is_a64(env) &&
1484 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1485
1486 return true;
1487 }
1488 }
1489 return false;
1490}
1491
1492
1493static inline bool arm_is_secure(CPUARMState *env)
1494{
1495 if (arm_is_el3_or_mon(env)) {
1496 return true;
1497 }
1498 return arm_is_secure_below_el3(env);
1499}
1500
1501#else
1502static inline bool arm_is_secure_below_el3(CPUARMState *env)
1503{
1504 return false;
1505}
1506
1507static inline bool arm_is_secure(CPUARMState *env)
1508{
1509 return false;
1510}
1511#endif
1512
1513
1514static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1515{
1516
1517
1518
1519 assert(el >= 1 && el <= 3);
1520 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1521
1522
1523
1524
1525
1526 if (el == 3) {
1527 return aa64;
1528 }
1529
1530 if (arm_feature(env, ARM_FEATURE_EL3)) {
1531 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1532 }
1533
1534 if (el == 2) {
1535 return aa64;
1536 }
1537
1538 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1539 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1540 }
1541
1542 return aa64;
1543}
1544
1545
1546
1547
1548
1549
1550
1551
1552static inline bool access_secure_reg(CPUARMState *env)
1553{
1554 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1555 !arm_el_is_aa64(env, 3) &&
1556 !(env->cp15.scr_el3 & SCR_NS));
1557
1558 return ret;
1559}
1560
1561
1562#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1563 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1564
1565#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1566 do { \
1567 if (_secure) { \
1568 (_env)->cp15._regname##_s = (_val); \
1569 } else { \
1570 (_env)->cp15._regname##_ns = (_val); \
1571 } \
1572 } while (0)
1573
1574
1575
1576
1577
1578
1579#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1580 A32_BANKED_REG_GET((_env), _regname, \
1581 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1582
1583#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1584 A32_BANKED_REG_SET((_env), _regname, \
1585 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1586 (_val))
1587
1588void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1589uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1590 uint32_t cur_el, bool secure);
1591
1592
1593#ifndef CONFIG_USER_ONLY
1594bool armv7m_nvic_can_take_pending_exception(void *opaque);
1595#else
1596static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
1597{
1598 return true;
1599}
1600#endif
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
1641 bool *ptargets_secure);
1642
1643
1644
1645
1646
1647
1648
1649
1650void armv7m_nvic_acknowledge_irq(void *opaque);
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672int armv7m_nvic_raw_execution_priority(void *opaque);
1673
1674
1675
1676
1677
1678
1679
1680#ifndef CONFIG_USER_ONLY
1681bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
1682#else
1683static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
1684{
1685 return false;
1686}
1687#endif
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715#define CP_REG_AA64_SHIFT 28
1716#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1717
1718
1719
1720
1721
1722#define CP_REG_NS_SHIFT 29
1723#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1724
1725#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1726 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1727 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1728
1729#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1730 (CP_REG_AA64_MASK | \
1731 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1732 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1733 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1734 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1735 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1736 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1737
1738
1739
1740
1741static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1742{
1743 uint32_t cpregid = kvmid;
1744 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1745 cpregid |= CP_REG_AA64_MASK;
1746 } else {
1747 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1748 cpregid |= (1 << 15);
1749 }
1750
1751
1752
1753
1754 cpregid |= 1 << CP_REG_NS_SHIFT;
1755 }
1756 return cpregid;
1757}
1758
1759
1760
1761
1762static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1763{
1764 uint64_t kvmid;
1765
1766 if (cpregid & CP_REG_AA64_MASK) {
1767 kvmid = cpregid & ~CP_REG_AA64_MASK;
1768 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1769 } else {
1770 kvmid = cpregid & ~(1 << 15);
1771 if (cpregid & (1 << 15)) {
1772 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1773 } else {
1774 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1775 }
1776 }
1777 return kvmid;
1778}
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802#define ARM_CP_SPECIAL 0x0001
1803#define ARM_CP_CONST 0x0002
1804#define ARM_CP_64BIT 0x0004
1805#define ARM_CP_SUPPRESS_TB_END 0x0008
1806#define ARM_CP_OVERRIDE 0x0010
1807#define ARM_CP_ALIAS 0x0020
1808#define ARM_CP_IO 0x0040
1809#define ARM_CP_NO_RAW 0x0080
1810#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
1811#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
1812#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
1813#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
1814#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
1815#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1816#define ARM_CP_FPU 0x1000
1817#define ARM_CP_SVE 0x2000
1818
1819#define ARM_CP_SENTINEL 0xffff
1820
1821#define ARM_CP_FLAG_MASK 0x30ff
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832enum {
1833 ARM_CP_STATE_AA32 = 0,
1834 ARM_CP_STATE_AA64 = 1,
1835 ARM_CP_STATE_BOTH = 2,
1836};
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848enum {
1849 ARM_CP_SECSTATE_S = (1 << 0),
1850 ARM_CP_SECSTATE_NS = (1 << 1),
1851};
1852
1853
1854
1855
1856
1857static inline bool cptype_valid(int cptype)
1858{
1859 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1860 || ((cptype & ARM_CP_SPECIAL) &&
1861 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1862}
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881#define PL3_R 0x80
1882#define PL3_W 0x40
1883#define PL2_R (0x20 | PL3_R)
1884#define PL2_W (0x10 | PL3_W)
1885#define PL1_R (0x08 | PL2_R)
1886#define PL1_W (0x04 | PL2_W)
1887#define PL0_R (0x02 | PL1_R)
1888#define PL0_W (0x01 | PL1_W)
1889
1890#define PL3_RW (PL3_R | PL3_W)
1891#define PL2_RW (PL2_R | PL2_W)
1892#define PL1_RW (PL1_R | PL1_W)
1893#define PL0_RW (PL0_R | PL0_W)
1894
1895
1896static inline int arm_highest_el(CPUARMState *env)
1897{
1898 if (arm_feature(env, ARM_FEATURE_EL3)) {
1899 return 3;
1900 }
1901 if (arm_feature(env, ARM_FEATURE_EL2)) {
1902 return 2;
1903 }
1904 return 1;
1905}
1906
1907
1908static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
1909{
1910 return env->v7m.exception != 0;
1911}
1912
1913
1914
1915
1916static inline int arm_current_el(CPUARMState *env)
1917{
1918 if (arm_feature(env, ARM_FEATURE_M)) {
1919 return arm_v7m_is_handler_mode(env) ||
1920 !(env->v7m.control[env->v7m.secure] & 1);
1921 }
1922
1923 if (is_a64(env)) {
1924 return extract32(env->pstate, 2, 2);
1925 }
1926
1927 switch (env->uncached_cpsr & 0x1f) {
1928 case ARM_CPU_MODE_USR:
1929 return 0;
1930 case ARM_CPU_MODE_HYP:
1931 return 2;
1932 case ARM_CPU_MODE_MON:
1933 return 3;
1934 default:
1935 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1936
1937
1938
1939 return 3;
1940 }
1941
1942 return 1;
1943 }
1944}
1945
1946typedef struct ARMCPRegInfo ARMCPRegInfo;
1947
1948typedef enum CPAccessResult {
1949
1950 CP_ACCESS_OK = 0,
1951
1952
1953
1954
1955
1956
1957 CP_ACCESS_TRAP = 1,
1958
1959
1960
1961
1962 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1963
1964 CP_ACCESS_TRAP_EL2 = 3,
1965 CP_ACCESS_TRAP_EL3 = 4,
1966
1967 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
1968 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
1969
1970
1971
1972 CP_ACCESS_TRAP_FP_EL2 = 7,
1973 CP_ACCESS_TRAP_FP_EL3 = 8,
1974} CPAccessResult;
1975
1976
1977
1978
1979typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1980typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1981 uint64_t value);
1982
1983typedef CPAccessResult CPAccessFn(CPUARMState *env,
1984 const ARMCPRegInfo *opaque,
1985 bool isread);
1986
1987typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1988
1989#define CP_ANY 0xff
1990
1991
1992struct ARMCPRegInfo {
1993
1994 const char *name;
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012 uint8_t cp;
2013 uint8_t crn;
2014 uint8_t crm;
2015 uint8_t opc0;
2016 uint8_t opc1;
2017 uint8_t opc2;
2018
2019 int state;
2020
2021 int type;
2022
2023 int access;
2024
2025 int secure;
2026
2027
2028
2029
2030 void *opaque;
2031
2032
2033
2034 uint64_t resetvalue;
2035
2036
2037
2038
2039
2040
2041 ptrdiff_t fieldoffset;
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054 ptrdiff_t bank_fieldoffsets[2];
2055
2056
2057
2058
2059
2060
2061 CPAccessFn *accessfn;
2062
2063
2064
2065
2066 CPReadFn *readfn;
2067
2068
2069
2070
2071 CPWriteFn *writefn;
2072
2073
2074
2075
2076
2077 CPReadFn *raw_readfn;
2078
2079
2080
2081
2082
2083
2084 CPWriteFn *raw_writefn;
2085
2086
2087
2088
2089 CPResetFn *resetfn;
2090};
2091
2092
2093
2094
2095#define CPREG_FIELD32(env, ri) \
2096 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2097#define CPREG_FIELD64(env, ri) \
2098 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2099
2100#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2101
2102void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2103 const ARMCPRegInfo *regs, void *opaque);
2104void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2105 const ARMCPRegInfo *regs, void *opaque);
2106static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2107{
2108 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2109}
2110static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2111{
2112 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2113}
2114const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2115
2116
2117void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2118 uint64_t value);
2119
2120uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2121
2122
2123
2124
2125void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2126
2127
2128
2129
2130static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2131{
2132 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2133}
2134
2135static inline bool cp_access_ok(int current_el,
2136 const ARMCPRegInfo *ri, int isread)
2137{
2138 return (ri->access >> ((current_el * 2) + isread)) & 1;
2139}
2140
2141
2142uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158bool write_list_to_cpustate(ARMCPU *cpu);
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174bool write_cpustate_to_list(ARMCPU *cpu);
2175
2176#define ARM_CPUID_TI915T 0x54029152
2177#define ARM_CPUID_TI925T 0x54029252
2178
2179#if defined(CONFIG_USER_ONLY)
2180#define TARGET_PAGE_BITS 12
2181#else
2182
2183
2184
2185#define TARGET_PAGE_BITS_VARY
2186#define TARGET_PAGE_BITS_MIN 10
2187#endif
2188
2189#if defined(TARGET_AARCH64)
2190# define TARGET_PHYS_ADDR_SPACE_BITS 48
2191# define TARGET_VIRT_ADDR_SPACE_BITS 64
2192#else
2193# define TARGET_PHYS_ADDR_SPACE_BITS 40
2194# define TARGET_VIRT_ADDR_SPACE_BITS 32
2195#endif
2196
2197static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
2198 unsigned int target_el)
2199{
2200 CPUARMState *env = cs->env_ptr;
2201 unsigned int cur_el = arm_current_el(env);
2202 bool secure = arm_is_secure(env);
2203 bool pstate_unmasked;
2204 int8_t unmasked = 0;
2205
2206
2207
2208
2209
2210 if (cur_el > target_el) {
2211 return false;
2212 }
2213
2214 switch (excp_idx) {
2215 case EXCP_FIQ:
2216 pstate_unmasked = !(env->daif & PSTATE_F);
2217 break;
2218
2219 case EXCP_IRQ:
2220 pstate_unmasked = !(env->daif & PSTATE_I);
2221 break;
2222
2223 case EXCP_VFIQ:
2224 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
2225
2226 return false;
2227 }
2228 return !(env->daif & PSTATE_F);
2229 case EXCP_VIRQ:
2230 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
2231
2232 return false;
2233 }
2234 return !(env->daif & PSTATE_I);
2235 default:
2236 g_assert_not_reached();
2237 }
2238
2239
2240
2241
2242
2243 if ((target_el > cur_el) && (target_el != 1)) {
2244
2245 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2246
2247
2248
2249
2250
2251 if (target_el == 3 || !secure) {
2252 unmasked = 1;
2253 }
2254 } else {
2255
2256
2257
2258
2259 bool hcr, scr;
2260
2261 switch (excp_idx) {
2262 case EXCP_FIQ:
2263
2264
2265
2266
2267
2268
2269 hcr = (env->cp15.hcr_el2 & HCR_FMO);
2270 scr = (env->cp15.scr_el3 & SCR_FIQ);
2271
2272
2273
2274
2275
2276
2277 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
2278 break;
2279 case EXCP_IRQ:
2280
2281
2282
2283
2284
2285
2286 hcr = (env->cp15.hcr_el2 & HCR_IMO);
2287 scr = false;
2288 break;
2289 default:
2290 g_assert_not_reached();
2291 }
2292
2293 if ((scr || hcr) && !secure) {
2294 unmasked = 1;
2295 }
2296 }
2297 }
2298
2299
2300
2301
2302 return unmasked || pstate_unmasked;
2303}
2304
2305#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2306#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2307#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2308
2309#define cpu_signal_handler cpu_arm_signal_handler
2310#define cpu_list arm_cpu_list
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391#define ARM_MMU_IDX_A 0x10
2392#define ARM_MMU_IDX_NOTLB 0x20
2393#define ARM_MMU_IDX_M 0x40
2394
2395
2396#define ARM_MMU_IDX_M_PRIV 0x1
2397#define ARM_MMU_IDX_M_NEGPRI 0x2
2398#define ARM_MMU_IDX_M_S 0x4
2399
2400#define ARM_MMU_IDX_TYPE_MASK (~0x7)
2401#define ARM_MMU_IDX_COREIDX_MASK 0x7
2402
2403typedef enum ARMMMUIdx {
2404 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
2405 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
2406 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
2407 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
2408 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
2409 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
2410 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
2411 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
2412 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
2413 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M,
2414 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M,
2415 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M,
2416 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M,
2417 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M,
2418 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M,
2419
2420
2421
2422 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
2423 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
2424} ARMMMUIdx;
2425
2426
2427
2428
2429typedef enum ARMMMUIdxBit {
2430 ARMMMUIdxBit_S12NSE0 = 1 << 0,
2431 ARMMMUIdxBit_S12NSE1 = 1 << 1,
2432 ARMMMUIdxBit_S1E2 = 1 << 2,
2433 ARMMMUIdxBit_S1E3 = 1 << 3,
2434 ARMMMUIdxBit_S1SE0 = 1 << 4,
2435 ARMMMUIdxBit_S1SE1 = 1 << 5,
2436 ARMMMUIdxBit_S2NS = 1 << 6,
2437 ARMMMUIdxBit_MUser = 1 << 0,
2438 ARMMMUIdxBit_MPriv = 1 << 1,
2439 ARMMMUIdxBit_MUserNegPri = 1 << 2,
2440 ARMMMUIdxBit_MPrivNegPri = 1 << 3,
2441 ARMMMUIdxBit_MSUser = 1 << 4,
2442 ARMMMUIdxBit_MSPriv = 1 << 5,
2443 ARMMMUIdxBit_MSUserNegPri = 1 << 6,
2444 ARMMMUIdxBit_MSPrivNegPri = 1 << 7,
2445} ARMMMUIdxBit;
2446
2447#define MMU_USER_IDX 0
2448
2449static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
2450{
2451 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
2452}
2453
2454static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
2455{
2456 if (arm_feature(env, ARM_FEATURE_M)) {
2457 return mmu_idx | ARM_MMU_IDX_M;
2458 } else {
2459 return mmu_idx | ARM_MMU_IDX_A;
2460 }
2461}
2462
2463
2464static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
2465{
2466 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
2467 case ARM_MMU_IDX_A:
2468 return mmu_idx & 3;
2469 case ARM_MMU_IDX_M:
2470 return mmu_idx & ARM_MMU_IDX_M_PRIV;
2471 default:
2472 g_assert_not_reached();
2473 }
2474}
2475
2476
2477
2478
2479static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
2480 bool secstate,
2481 bool priv)
2482{
2483 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
2484
2485 if (priv) {
2486 mmu_idx |= ARM_MMU_IDX_M_PRIV;
2487 }
2488
2489 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
2490 mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
2491 }
2492
2493 if (secstate) {
2494 mmu_idx |= ARM_MMU_IDX_M_S;
2495 }
2496
2497 return mmu_idx;
2498}
2499
2500
2501static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
2502 bool secstate)
2503{
2504 bool priv = arm_current_el(env) != 0;
2505
2506 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
2507}
2508
2509
2510static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
2511{
2512 int el = arm_current_el(env);
2513
2514 if (arm_feature(env, ARM_FEATURE_M)) {
2515 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
2516
2517 return arm_to_core_mmu_idx(mmu_idx);
2518 }
2519
2520 if (el < 2 && arm_is_secure_below_el3(env)) {
2521 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
2522 }
2523 return el;
2524}
2525
2526
2527typedef enum ARMASIdx {
2528 ARMASIdx_NS = 0,
2529 ARMASIdx_S = 1,
2530} ARMASIdx;
2531
2532
2533static inline int arm_debug_target_el(CPUARMState *env)
2534{
2535 bool secure = arm_is_secure(env);
2536 bool route_to_el2 = false;
2537
2538 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
2539 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
2540 env->cp15.mdcr_el2 & (1 << 8);
2541 }
2542
2543 if (route_to_el2) {
2544 return 2;
2545 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
2546 !arm_el_is_aa64(env, 3) && secure) {
2547 return 3;
2548 } else {
2549 return 1;
2550 }
2551}
2552
2553static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2554{
2555
2556
2557
2558 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2559}
2560
2561static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2562{
2563 if (arm_is_secure(env)) {
2564
2565 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
2566 || arm_current_el(env) == 3) {
2567 return false;
2568 }
2569 }
2570
2571 if (arm_current_el(env) == arm_debug_target_el(env)) {
2572 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
2573 || (env->daif & PSTATE_D)) {
2574 return false;
2575 }
2576 }
2577 return true;
2578}
2579
2580static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
2581{
2582 int el = arm_current_el(env);
2583
2584 if (el == 0 && arm_el_is_aa64(env, 1)) {
2585 return aa64_generate_debug_exceptions(env);
2586 }
2587
2588 if (arm_is_secure(env)) {
2589 int spd;
2590
2591 if (el == 0 && (env->cp15.sder & 1)) {
2592
2593
2594
2595
2596 return true;
2597 }
2598
2599 spd = extract32(env->cp15.mdcr_el3, 14, 2);
2600 switch (spd) {
2601 case 1:
2602
2603 case 0:
2604
2605
2606
2607
2608
2609 return true;
2610 case 2:
2611 return false;
2612 case 3:
2613 return true;
2614 }
2615 }
2616
2617 return el != 2;
2618}
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634static inline bool arm_generate_debug_exceptions(CPUARMState *env)
2635{
2636 if (env->aarch64) {
2637 return aa64_generate_debug_exceptions(env);
2638 } else {
2639 return aa32_generate_debug_exceptions(env);
2640 }
2641}
2642
2643
2644
2645
2646static inline bool arm_singlestep_active(CPUARMState *env)
2647{
2648 return extract32(env->cp15.mdscr_el1, 0, 1)
2649 && arm_el_is_aa64(env, arm_debug_target_el(env))
2650 && arm_generate_debug_exceptions(env);
2651}
2652
2653static inline bool arm_sctlr_b(CPUARMState *env)
2654{
2655 return
2656
2657
2658
2659
2660#ifndef CONFIG_USER_ONLY
2661 !arm_feature(env, ARM_FEATURE_V7) &&
2662#endif
2663 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2664}
2665
2666
2667static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
2668{
2669 int cur_el;
2670
2671
2672 if (!is_a64(env)) {
2673 return
2674#ifdef CONFIG_USER_ONLY
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686 arm_sctlr_b(env) ||
2687#endif
2688 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
2689 }
2690
2691 cur_el = arm_current_el(env);
2692
2693 if (cur_el == 0) {
2694 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
2695 }
2696
2697 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
2698}
2699
2700#include "exec/cpu-all.h"
2701
2702
2703
2704
2705
2706
2707#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2708#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2709#define ARM_TBFLAG_MMUIDX_SHIFT 28
2710#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2711#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2712#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2713#define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2714#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2715
2716#define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2717#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2718
2719
2720#define ARM_TBFLAG_THUMB_SHIFT 0
2721#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2722#define ARM_TBFLAG_VECLEN_SHIFT 1
2723#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2724#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2725#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2726#define ARM_TBFLAG_VFPEN_SHIFT 7
2727#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2728#define ARM_TBFLAG_CONDEXEC_SHIFT 8
2729#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2730#define ARM_TBFLAG_SCTLR_B_SHIFT 16
2731#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2732
2733
2734
2735#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2736#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2737
2738
2739
2740
2741#define ARM_TBFLAG_NS_SHIFT 19
2742#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2743#define ARM_TBFLAG_BE_DATA_SHIFT 20
2744#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2745
2746#define ARM_TBFLAG_HANDLER_SHIFT 21
2747#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
2748
2749
2750#define ARM_TBFLAG_TBI0_SHIFT 0
2751#define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
2752#define ARM_TBFLAG_TBI1_SHIFT 1
2753#define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
2754#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2
2755#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT)
2756#define ARM_TBFLAG_ZCR_LEN_SHIFT 4
2757#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT)
2758
2759
2760#define ARM_TBFLAG_AARCH64_STATE(F) \
2761 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2762#define ARM_TBFLAG_MMUIDX(F) \
2763 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2764#define ARM_TBFLAG_SS_ACTIVE(F) \
2765 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2766#define ARM_TBFLAG_PSTATE_SS(F) \
2767 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2768#define ARM_TBFLAG_FPEXC_EL(F) \
2769 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2770#define ARM_TBFLAG_THUMB(F) \
2771 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2772#define ARM_TBFLAG_VECLEN(F) \
2773 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2774#define ARM_TBFLAG_VECSTRIDE(F) \
2775 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2776#define ARM_TBFLAG_VFPEN(F) \
2777 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2778#define ARM_TBFLAG_CONDEXEC(F) \
2779 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2780#define ARM_TBFLAG_SCTLR_B(F) \
2781 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2782#define ARM_TBFLAG_XSCALE_CPAR(F) \
2783 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2784#define ARM_TBFLAG_NS(F) \
2785 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2786#define ARM_TBFLAG_BE_DATA(F) \
2787 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2788#define ARM_TBFLAG_HANDLER(F) \
2789 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
2790#define ARM_TBFLAG_TBI0(F) \
2791 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
2792#define ARM_TBFLAG_TBI1(F) \
2793 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT)
2794#define ARM_TBFLAG_SVEEXC_EL(F) \
2795 (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT)
2796#define ARM_TBFLAG_ZCR_LEN(F) \
2797 (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT)
2798
2799static inline bool bswap_code(bool sctlr_b)
2800{
2801#ifdef CONFIG_USER_ONLY
2802
2803
2804
2805
2806 return
2807#ifdef TARGET_WORDS_BIGENDIAN
2808 1 ^
2809#endif
2810 sctlr_b;
2811#else
2812
2813
2814
2815 return 0;
2816#endif
2817}
2818
2819#ifdef CONFIG_USER_ONLY
2820static inline bool arm_cpu_bswap_data(CPUARMState *env)
2821{
2822 return
2823#ifdef TARGET_WORDS_BIGENDIAN
2824 1 ^
2825#endif
2826 arm_cpu_data_is_big_endian(env);
2827}
2828#endif
2829
2830#ifndef CONFIG_USER_ONLY
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
2852#else
2853
2854static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
2855{
2856 return 0;
2857}
2858
2859static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
2860{
2861 return 0;
2862}
2863#endif
2864
2865void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
2866 target_ulong *cs_base, uint32_t *flags);
2867
2868enum {
2869 QEMU_PSCI_CONDUIT_DISABLED = 0,
2870 QEMU_PSCI_CONDUIT_SMC = 1,
2871 QEMU_PSCI_CONDUIT_HVC = 2,
2872};
2873
2874#ifndef CONFIG_USER_ONLY
2875
2876static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2877{
2878 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
2879}
2880
2881
2882
2883
2884
2885static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
2886{
2887 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
2888}
2889#endif
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
2903 void *opaque);
2904
2905
2906
2907
2908
2909
2910static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
2911{
2912 return cpu->el_change_hook_opaque;
2913}
2914
2915
2916
2917
2918
2919static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
2920{
2921 return &env->vfp.zregs[regno >> 1].d[regno & 1];
2922}
2923
2924
2925
2926
2927
2928static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
2929{
2930 return &env->vfp.zregs[regno].d[0];
2931}
2932
2933
2934
2935
2936
2937static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
2938{
2939 return &env->vfp.zregs[regno].d[0];
2940}
2941
2942#endif
2943