LXR qemu/target/arm/translate.h

   1#ifndef TARGET_ARM_TRANSLATE_H
   2#define TARGET_ARM_TRANSLATE_H
   3
   4#include "exec/translator.h"
   5
   6
   7/* internal defines */
   8typedef struct DisasContext {
   9    DisasContextBase base;
  10
  11    target_ulong pc;
  12    target_ulong next_page_start;
  13    uint32_t insn;
  14    /* Nonzero if this instruction has been conditionally skipped.  */
  15    int condjmp;
  16    /* The label that will be jumped to when the instruction is skipped.  */
  17    TCGLabel *condlabel;
  18    /* Thumb-2 conditional execution bits.  */
  19    int condexec_mask;
  20    int condexec_cond;
  21    int thumb;
  22    int sctlr_b;
  23    TCGMemOp be_data;
  24#if !defined(CONFIG_USER_ONLY)
  25    int user;
  26#endif
  27    ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  28    bool tbi0;         /* TBI0 for EL0/1 or TBI for EL2/3 */
  29    bool tbi1;         /* TBI1 for EL0/1, not used for EL2/3 */
  30    bool ns;        /* Use non-secure CPREG bank on access */
  31    int fp_excp_el; /* FP exception EL or 0 if enabled */
  32    int sve_excp_el; /* SVE exception EL or 0 if enabled */
  33    int sve_len;     /* SVE vector length in bytes */
  34    /* Flag indicating that exceptions from secure mode are routed to EL3. */
  35    bool secure_routed_to_el3;
  36    bool vfp_enabled; /* FP enabled via FPSCR.EN */
  37    int vec_len;
  38    int vec_stride;
  39    bool v7m_handler_mode;
  40    bool v8m_secure; /* true if v8M and we're in Secure mode */
  41    /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  42     * so that top level loop can generate correct syndrome information.
  43     */
  44    uint32_t svc_imm;
  45    int aarch64;
  46    int current_el;
  47    GHashTable *cp_regs;
  48    uint64_t features; /* CPU features bits */
  49    /* Because unallocated encodings generate different exception syndrome
  50     * information from traps due to FP being disabled, we can't do a single
  51     * "is fp access disabled" check at a high level in the decode tree.
  52     * To help in catching bugs where the access check was forgotten in some
  53     * code path, we set this flag when the access check is done, and assert
  54     * that it is set at the point where we actually touch the FP regs.
  55     */
  56    bool fp_access_checked;
  57    /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  58     * single-step support).
  59     */
  60    bool ss_active;
  61    bool pstate_ss;
  62    /* True if the insn just emitted was a load-exclusive instruction
  63     * (necessary for syndrome information for single step exceptions),
  64     * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  65     */
  66    bool is_ldex;
  67    /* True if a single-step exception will be taken to the current EL */
  68    bool ss_same_el;
  69    /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  70    int c15_cpar;
  71    /* TCG op of the current insn_start.  */
  72    TCGOp *insn_start;
  73#define TMP_A64_MAX 16
  74    int tmp_a64_count;
  75    TCGv_i64 tmp_a64[TMP_A64_MAX];
  76} DisasContext;
  77
  78typedef struct DisasCompare {
  79    TCGCond cond;
  80    TCGv_i32 value;
  81    bool value_global;
  82} DisasCompare;
  83
  84/* Share the TCG temporaries common between 32 and 64 bit modes.  */
  85extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
  86extern TCGv_i64 cpu_exclusive_addr;
  87extern TCGv_i64 cpu_exclusive_val;
  88
  89static inline int arm_dc_feature(DisasContext *dc, int feature)
  90{
  91    return (dc->features & (1ULL << feature)) != 0;
  92}
  93
  94static inline int get_mem_index(DisasContext *s)
  95{
  96    return arm_to_core_mmu_idx(s->mmu_idx);
  97}
  98
  99/* Function used to determine the target exception EL when otherwise not known
 100 * or default.
 101 */
 102static inline int default_exception_el(DisasContext *s)
 103{
 104    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 105     * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 106     * exceptions can only be routed to ELs above 1, so we target the higher of
 107     * 1 or the current EL.
 108     */
 109    return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 110            ? 3 : MAX(1, s->current_el);
 111}
 112
 113static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 114{
 115    /* We don't need to save all of the syndrome so we mask and shift
 116     * out unneeded bits to help the sleb128 encoder do a better job.
 117     */
 118    syn &= ARM_INSN_START_WORD2_MASK;
 119    syn >>= ARM_INSN_START_WORD2_SHIFT;
 120
 121    /* We check and clear insn_start_idx to catch multiple updates.  */
 122    assert(s->insn_start != NULL);
 123    tcg_set_insn_start_param(s->insn_start, 2, syn);
 124    s->insn_start = NULL;
 125}
 126
 127/* is_jmp field values */
 128#define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 129#define DISAS_UPDATE    DISAS_TARGET_1 /* cpu state was modified dynamically */
 130/* These instructions trap after executing, so the A32/T32 decoder must
 131 * defer them until after the conditional execution state has been updated.
 132 * WFI also needs special handling when single-stepping.
 133 */
 134#define DISAS_WFI       DISAS_TARGET_2
 135#define DISAS_SWI       DISAS_TARGET_3
 136/* WFE */
 137#define DISAS_WFE       DISAS_TARGET_4
 138#define DISAS_HVC       DISAS_TARGET_5
 139#define DISAS_SMC       DISAS_TARGET_6
 140#define DISAS_YIELD     DISAS_TARGET_7
 141/* M profile branch which might be an exception return (and so needs
 142 * custom end-of-TB code)
 143 */
 144#define DISAS_BX_EXCRET DISAS_TARGET_8
 145/* For instructions which want an immediate exit to the main loop,
 146 * as opposed to attempting to use lookup_and_goto_ptr. Unlike
 147 * DISAS_UPDATE this doesn't write the PC on exiting the translation
 148 * loop so you need to ensure something (gen_a64_set_pc_im or runtime
 149 * helper) has done so before we reach return from cpu_tb_exec.
 150 */
 151#define DISAS_EXIT      DISAS_TARGET_9
 152
 153#ifdef TARGET_AARCH64
 154void a64_translate_init(void);
 155void gen_a64_set_pc_im(uint64_t val);
 156void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 157                            fprintf_function cpu_fprintf, int flags);
 158extern const TranslatorOps aarch64_translator_ops;
 159#else
 160static inline void a64_translate_init(void)
 161{
 162}
 163
 164static inline void gen_a64_set_pc_im(uint64_t val)
 165{
 166}
 167
 168static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 169                                          fprintf_function cpu_fprintf,
 170                                          int flags)
 171{
 172}
 173#endif
 174
 175void arm_test_cc(DisasCompare *cmp, int cc);
 176void arm_free_cc(DisasCompare *cmp);
 177void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 178void arm_gen_test_cc(int cc, TCGLabel *label);
 179
 180#endif /* TARGET_ARM_TRANSLATE_H */
 181