LXR qemu/target/i386/smm

   1/*
   2 *  x86 SMM helpers
   3 *
   4 *  Copyright (c) 2003 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "qemu/main-loop.h"
  22#include "cpu.h"
  23#include "exec/helper-proto.h"
  24#include "exec/log.h"
  25
  26/* SMM support */
  27
  28#if defined(CONFIG_USER_ONLY)
  29
  30void do_smm_enter(X86CPU *cpu)
  31{
  32}
  33
  34void helper_rsm(CPUX86State *env)
  35{
  36}
  37
  38#else
  39
  40#ifdef TARGET_X86_64
  41#define SMM_REVISION_ID 0x00020064
  42#else
  43#define SMM_REVISION_ID 0x00020000
  44#endif
  45
  46void do_smm_enter(X86CPU *cpu)
  47{
  48    CPUX86State *env = &cpu->env;
  49    CPUState *cs = CPU(cpu);
  50    target_ulong sm_state;
  51    SegmentCache *dt;
  52    int i, offset;
  53
  54    qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
  55    log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
  56
  57    env->hflags |= HF_SMM_MASK;
  58    if (env->hflags2 & HF2_NMI_MASK) {
  59        env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
  60    } else {
  61        env->hflags2 |= HF2_NMI_MASK;
  62    }
  63
  64    sm_state = env->smbase + 0x8000;
  65
  66#ifdef TARGET_X86_64
  67    for (i = 0; i < 6; i++) {
  68        dt = &env->segs[i];
  69        offset = 0x7e00 + i * 16;
  70        x86_stw_phys(cs, sm_state + offset, dt->selector);
  71        x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
  72        x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
  73        x86_stq_phys(cs, sm_state + offset + 8, dt->base);
  74    }
  75
  76    x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
  77    x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
  78
  79    x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
  80    x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
  81    x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
  82    x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
  83
  84    x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
  85    x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
  86
  87    x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
  88    x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
  89    x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
  90    x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
  91
  92    /* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
  93       is saved at offset 7ED0.  Vol 3, 34.4.1.1, Table 32-2, has
  94       7EA0-7ED7 as "reserved".  What's this, and what's really
  95       supposed to happen?  */
  96    x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
  97
  98    x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
  99    x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
 100    x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
 101    x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
 102    x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
 103    x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
 104    x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
 105    x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
 106    for (i = 8; i < 16; i++) {
 107        x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
 108    }
 109    x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
 110    x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
 111    x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
 112    x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
 113
 114    x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
 115    x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
 116    x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
 117
 118    x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 119    x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
 120#else
 121    x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
 122    x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
 123    x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
 124    x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
 125    x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
 126    x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
 127    x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
 128    x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
 129    x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
 130    x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
 131    x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
 132    x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
 133    x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
 134    x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
 135
 136    x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
 137    x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
 138    x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
 139    x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
 140
 141    x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
 142    x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
 143    x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
 144    x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
 145
 146    x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
 147    x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
 148
 149    x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
 150    x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
 151
 152    for (i = 0; i < 6; i++) {
 153        dt = &env->segs[i];
 154        if (i < 3) {
 155            offset = 0x7f84 + i * 12;
 156        } else {
 157            offset = 0x7f2c + (i - 3) * 12;
 158        }
 159        x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
 160        x86_stl_phys(cs, sm_state + offset + 8, dt->base);
 161        x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
 162        x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
 163    }
 164    x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
 165
 166    x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 167    x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
 168#endif
 169    /* init SMM cpu state */
 170
 171#ifdef TARGET_X86_64
 172    cpu_load_efer(env, 0);
 173#endif
 174    cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
 175                              DF_MASK));
 176    env->eip = 0x00008000;
 177    cpu_x86_update_cr0(env,
 178                       env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
 179                                      CR0_PG_MASK));
 180    cpu_x86_update_cr4(env, 0);
 181    env->dr[7] = 0x00000400;
 182
 183    cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
 184                           0xffffffff,
 185                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 186                           DESC_G_MASK | DESC_A_MASK);
 187    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
 188                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 189                           DESC_G_MASK | DESC_A_MASK);
 190    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
 191                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 192                           DESC_G_MASK | DESC_A_MASK);
 193    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
 194                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 195                           DESC_G_MASK | DESC_A_MASK);
 196    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
 197                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 198                           DESC_G_MASK | DESC_A_MASK);
 199    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
 200                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 201                           DESC_G_MASK | DESC_A_MASK);
 202}
 203
 204void helper_rsm(CPUX86State *env)
 205{
 206    X86CPU *cpu = x86_env_get_cpu(env);
 207    CPUState *cs = CPU(cpu);
 208    target_ulong sm_state;
 209    int i, offset;
 210    uint32_t val;
 211
 212    sm_state = env->smbase + 0x8000;
 213#ifdef TARGET_X86_64
 214    cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
 215
 216    env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
 217    env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
 218
 219    env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
 220    env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
 221    env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
 222    env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
 223
 224    env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
 225    env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
 226
 227    env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
 228    env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
 229    env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
 230    env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
 231
 232    env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
 233    env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
 234    env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
 235    env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
 236    env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
 237    env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
 238    env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
 239    env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
 240    for (i = 8; i < 16; i++) {
 241        env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
 242    }
 243    env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
 244    cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
 245                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 246    env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
 247    env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
 248
 249    cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
 250    cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
 251    cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
 252
 253    for (i = 0; i < 6; i++) {
 254        offset = 0x7e00 + i * 16;
 255        cpu_x86_load_seg_cache(env, i,
 256                               x86_lduw_phys(cs, sm_state + offset),
 257                               x86_ldq_phys(cs, sm_state + offset + 8),
 258                               x86_ldl_phys(cs, sm_state + offset + 4),
 259                               (x86_lduw_phys(cs, sm_state + offset + 2) &
 260                                0xf0ff) << 8);
 261    }
 262
 263    val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 264    if (val & 0x20000) {
 265        env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
 266    }
 267#else
 268    cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
 269    cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
 270    cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
 271                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 272    env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
 273    env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
 274    env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
 275    env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
 276    env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
 277    env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
 278    env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
 279    env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
 280    env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
 281    env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
 282    env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
 283
 284    env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
 285    env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
 286    env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
 287    env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
 288
 289    env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
 290    env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
 291    env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
 292    env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
 293
 294    env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
 295    env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
 296
 297    env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
 298    env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
 299
 300    for (i = 0; i < 6; i++) {
 301        if (i < 3) {
 302            offset = 0x7f84 + i * 12;
 303        } else {
 304            offset = 0x7f2c + (i - 3) * 12;
 305        }
 306        cpu_x86_load_seg_cache(env, i,
 307                               x86_ldl_phys(cs,
 308                                        sm_state + 0x7fa8 + i * 4) & 0xffff,
 309                               x86_ldl_phys(cs, sm_state + offset + 8),
 310                               x86_ldl_phys(cs, sm_state + offset + 4),
 311                               (x86_ldl_phys(cs,
 312                                         sm_state + offset) & 0xf0ff) << 8);
 313    }
 314    cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
 315
 316    val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 317    if (val & 0x20000) {
 318        env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
 319    }
 320#endif
 321    if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
 322        env->hflags2 &= ~HF2_NMI_MASK;
 323    }
 324    env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
 325    env->hflags &= ~HF_SMM_MASK;
 326
 327    qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
 328    log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
 329}
 330
 331#endif /* !CONFIG_USER_ONLY */
 332