LXR qemu/target/mips/internal.h

   1/* mips internal definitions and helpers
   2 *
   3 * This work is licensed under the terms of the GNU GPL, version 2 or later.
   4 * See the COPYING file in the top-level directory.
   5 */
   6
   7#ifndef MIPS_INTERNAL_H
   8#define MIPS_INTERNAL_H
   9
  10
  11/* MMU types, the first four entries have the same layout as the
  12   CP0C0_MT field.  */
  13enum mips_mmu_types {
  14    MMU_TYPE_NONE,
  15    MMU_TYPE_R4000,
  16    MMU_TYPE_RESERVED,
  17    MMU_TYPE_FMT,
  18    MMU_TYPE_R3000,
  19    MMU_TYPE_R6000,
  20    MMU_TYPE_R8000
  21};
  22
  23struct mips_def_t {
  24    const char *name;
  25    int32_t CP0_PRid;
  26    int32_t CP0_Config0;
  27    int32_t CP0_Config1;
  28    int32_t CP0_Config2;
  29    int32_t CP0_Config3;
  30    int32_t CP0_Config4;
  31    int32_t CP0_Config4_rw_bitmask;
  32    int32_t CP0_Config5;
  33    int32_t CP0_Config5_rw_bitmask;
  34    int32_t CP0_Config6;
  35    int32_t CP0_Config7;
  36    target_ulong CP0_LLAddr_rw_bitmask;
  37    int CP0_LLAddr_shift;
  38    int32_t SYNCI_Step;
  39    int32_t CCRes;
  40    int32_t CP0_Status_rw_bitmask;
  41    int32_t CP0_TCStatus_rw_bitmask;
  42    int32_t CP0_SRSCtl;
  43    int32_t CP1_fcr0;
  44    int32_t CP1_fcr31_rw_bitmask;
  45    int32_t CP1_fcr31;
  46    int32_t MSAIR;
  47    int32_t SEGBITS;
  48    int32_t PABITS;
  49    int32_t CP0_SRSConf0_rw_bitmask;
  50    int32_t CP0_SRSConf0;
  51    int32_t CP0_SRSConf1_rw_bitmask;
  52    int32_t CP0_SRSConf1;
  53    int32_t CP0_SRSConf2_rw_bitmask;
  54    int32_t CP0_SRSConf2;
  55    int32_t CP0_SRSConf3_rw_bitmask;
  56    int32_t CP0_SRSConf3;
  57    int32_t CP0_SRSConf4_rw_bitmask;
  58    int32_t CP0_SRSConf4;
  59    int32_t CP0_PageGrain_rw_bitmask;
  60    int32_t CP0_PageGrain;
  61    target_ulong CP0_EBaseWG_rw_bitmask;
  62    int insn_flags;
  63    enum mips_mmu_types mmu_type;
  64};
  65
  66extern const struct mips_def_t mips_defs[];
  67extern const int mips_defs_number;
  68
  69enum CPUMIPSMSADataFormat {
  70    DF_BYTE = 0,
  71    DF_HALF,
  72    DF_WORD,
  73    DF_DOUBLE
  74};
  75
  76void mips_cpu_do_interrupt(CPUState *cpu);
  77bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
  78void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
  79                         int flags);
  80hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  81int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
  82int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  83void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  84                                  MMUAccessType access_type,
  85                                  int mmu_idx, uintptr_t retaddr);
  86
  87#if !defined(CONFIG_USER_ONLY)
  88
  89typedef struct r4k_tlb_t r4k_tlb_t;
  90struct r4k_tlb_t {
  91    target_ulong VPN;
  92    uint32_t PageMask;
  93    uint16_t ASID;
  94    unsigned int G:1;
  95    unsigned int C0:3;
  96    unsigned int C1:3;
  97    unsigned int V0:1;
  98    unsigned int V1:1;
  99    unsigned int D0:1;
 100    unsigned int D1:1;
 101    unsigned int XI0:1;
 102    unsigned int XI1:1;
 103    unsigned int RI0:1;
 104    unsigned int RI1:1;
 105    unsigned int EHINV:1;
 106    uint64_t PFN[2];
 107};
 108
 109struct CPUMIPSTLBContext {
 110    uint32_t nb_tlb;
 111    uint32_t tlb_in_use;
 112    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
 113                       target_ulong address, int rw, int access_type);
 114    void (*helper_tlbwi)(struct CPUMIPSState *env);
 115    void (*helper_tlbwr)(struct CPUMIPSState *env);
 116    void (*helper_tlbp)(struct CPUMIPSState *env);
 117    void (*helper_tlbr)(struct CPUMIPSState *env);
 118    void (*helper_tlbinv)(struct CPUMIPSState *env);
 119    void (*helper_tlbinvf)(struct CPUMIPSState *env);
 120    union {
 121        struct {
 122            r4k_tlb_t tlb[MIPS_TLB_MAX];
 123        } r4k;
 124    } mmu;
 125};
 126
 127int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 128                       target_ulong address, int rw, int access_type);
 129int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 130                          target_ulong address, int rw, int access_type);
 131int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 132                    target_ulong address, int rw, int access_type);
 133void r4k_helper_tlbwi(CPUMIPSState *env);
 134void r4k_helper_tlbwr(CPUMIPSState *env);
 135void r4k_helper_tlbp(CPUMIPSState *env);
 136void r4k_helper_tlbr(CPUMIPSState *env);
 137void r4k_helper_tlbinv(CPUMIPSState *env);
 138void r4k_helper_tlbinvf(CPUMIPSState *env);
 139void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 140
 141void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 142                                bool is_write, bool is_exec, int unused,
 143                                unsigned size);
 144hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
 145                                  int rw);
 146#endif
 147
 148#define cpu_signal_handler cpu_mips_signal_handler
 149
 150#ifndef CONFIG_USER_ONLY
 151extern const struct VMStateDescription vmstate_mips_cpu;
 152#endif
 153
 154static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 155{
 156    return (env->CP0_Status & (1 << CP0St_IE)) &&
 157        !(env->CP0_Status & (1 << CP0St_EXL)) &&
 158        !(env->CP0_Status & (1 << CP0St_ERL)) &&
 159        !(env->hflags & MIPS_HFLAG_DM) &&
 160        /* Note that the TCStatus IXMT field is initialized to zero,
 161           and only MT capable cores can set it to one. So we don't
 162           need to check for MT capabilities here.  */
 163        !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 164}
 165
 166/* Check if there is pending and not masked out interrupt */
 167static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 168{
 169    int32_t pending;
 170    int32_t status;
 171    bool r;
 172
 173    pending = env->CP0_Cause & CP0Ca_IP_mask;
 174    status = env->CP0_Status & CP0Ca_IP_mask;
 175
 176    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 177        /* A MIPS configured with a vectorizing external interrupt controller
 178           will feed a vector into the Cause pending lines. The core treats
 179           the status lines as a vector level, not as indiviual masks.  */
 180        r = pending > status;
 181    } else {
 182        /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 183           treats the pending lines as individual interrupt lines, the status
 184           lines are individual masks.  */
 185        r = (pending & status) != 0;
 186    }
 187    return r;
 188}
 189
 190void mips_tcg_init(void);
 191
 192/* TODO QOM'ify CPU reset and remove */
 193void cpu_state_reset(CPUMIPSState *s);
 194void cpu_mips_realize_env(CPUMIPSState *env);
 195
 196/* cp0_timer.c */
 197uint32_t cpu_mips_get_random(CPUMIPSState *env);
 198uint32_t cpu_mips_get_count(CPUMIPSState *env);
 199void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
 200void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
 201void cpu_mips_start_count(CPUMIPSState *env);
 202void cpu_mips_stop_count(CPUMIPSState *env);
 203
 204/* helper.c */
 205int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
 206                              int mmu_idx);
 207
 208/* op_helper.c */
 209uint32_t float_class_s(uint32_t arg, float_status *fst);
 210uint64_t float_class_d(uint64_t arg, float_status *fst);
 211
 212extern unsigned int ieee_rm[];
 213int ieee_ex_to_mips(int xcpt);
 214
 215static inline void restore_rounding_mode(CPUMIPSState *env)
 216{
 217    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 218                            &env->active_fpu.fp_status);
 219}
 220
 221static inline void restore_flush_mode(CPUMIPSState *env)
 222{
 223    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
 224                      &env->active_fpu.fp_status);
 225}
 226
 227static inline void restore_fp_status(CPUMIPSState *env)
 228{
 229    restore_rounding_mode(env);
 230    restore_flush_mode(env);
 231    restore_snan_bit_mode(env);
 232}
 233
 234static inline void restore_msa_fp_status(CPUMIPSState *env)
 235{
 236    float_status *status = &env->active_tc.msa_fp_status;
 237    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 238    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 239
 240    set_float_rounding_mode(ieee_rm[rounding_mode], status);
 241    set_flush_to_zero(flush_to_zero, status);
 242    set_flush_inputs_to_zero(flush_to_zero, status);
 243}
 244
 245static inline void restore_pamask(CPUMIPSState *env)
 246{
 247    if (env->hflags & MIPS_HFLAG_ELPA) {
 248        env->PAMask = (1ULL << env->PABITS) - 1;
 249    } else {
 250        env->PAMask = PAMASK_BASE;
 251    }
 252}
 253
 254static inline int mips_vpe_active(CPUMIPSState *env)
 255{
 256    int active = 1;
 257
 258    /* Check that the VPE is enabled.  */
 259    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 260        active = 0;
 261    }
 262    /* Check that the VPE is activated.  */
 263    if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 264        active = 0;
 265    }
 266
 267    /* Now verify that there are active thread contexts in the VPE.
 268
 269       This assumes the CPU model will internally reschedule threads
 270       if the active one goes to sleep. If there are no threads available
 271       the active one will be in a sleeping state, and we can turn off
 272       the entire VPE.  */
 273    if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 274        /* TC is not activated.  */
 275        active = 0;
 276    }
 277    if (env->active_tc.CP0_TCHalt & 1) {
 278        /* TC is in halt state.  */
 279        active = 0;
 280    }
 281
 282    return active;
 283}
 284
 285static inline int mips_vp_active(CPUMIPSState *env)
 286{
 287    CPUState *other_cs = first_cpu;
 288
 289    /* Check if the VP disabled other VPs (which means the VP is enabled) */
 290    if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 291        return 1;
 292    }
 293
 294    /* Check if the virtual processor is disabled due to a DVP */
 295    CPU_FOREACH(other_cs) {
 296        MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 297        if ((&other_cpu->env != env) &&
 298            ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 299            return 0;
 300        }
 301    }
 302    return 1;
 303}
 304
 305static inline void compute_hflags(CPUMIPSState *env)
 306{
 307    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 308                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 309                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 310                     MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
 311                     MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
 312    if (env->CP0_Status & (1 << CP0St_ERL)) {
 313        env->hflags |= MIPS_HFLAG_ERL;
 314    }
 315    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 316        !(env->CP0_Status & (1 << CP0St_ERL)) &&
 317        !(env->hflags & MIPS_HFLAG_DM)) {
 318        env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 319    }
 320#if defined(TARGET_MIPS64)
 321    if ((env->insn_flags & ISA_MIPS3) &&
 322        (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 323         (env->CP0_Status & (1 << CP0St_PX)) ||
 324         (env->CP0_Status & (1 << CP0St_UX)))) {
 325        env->hflags |= MIPS_HFLAG_64;
 326    }
 327
 328    if (!(env->insn_flags & ISA_MIPS3)) {
 329        env->hflags |= MIPS_HFLAG_AWRAP;
 330    } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 331               !(env->CP0_Status & (1 << CP0St_UX))) {
 332        env->hflags |= MIPS_HFLAG_AWRAP;
 333    } else if (env->insn_flags & ISA_MIPS64R6) {
 334        /* Address wrapping for Supervisor and Kernel is specified in R6 */
 335        if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 336             !(env->CP0_Status & (1 << CP0St_SX))) ||
 337            (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 338             !(env->CP0_Status & (1 << CP0St_KX)))) {
 339            env->hflags |= MIPS_HFLAG_AWRAP;
 340        }
 341    }
 342#endif
 343    if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 344         !(env->insn_flags & ISA_MIPS32R6)) ||
 345        !(env->hflags & MIPS_HFLAG_KSU)) {
 346        env->hflags |= MIPS_HFLAG_CP0;
 347    }
 348    if (env->CP0_Status & (1 << CP0St_CU1)) {
 349        env->hflags |= MIPS_HFLAG_FPU;
 350    }
 351    if (env->CP0_Status & (1 << CP0St_FR)) {
 352        env->hflags |= MIPS_HFLAG_F64;
 353    }
 354    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 355        (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 356        env->hflags |= MIPS_HFLAG_SBRI;
 357    }
 358    if (env->insn_flags & ASE_DSPR2) {
 359        /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 360           so enable to access DSPR2 resources. */
 361        if (env->CP0_Status & (1 << CP0St_MX)) {
 362            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 363        }
 364
 365    } else if (env->insn_flags & ASE_DSP) {
 366        /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 367           so enable to access DSP resources. */
 368        if (env->CP0_Status & (1 << CP0St_MX)) {
 369            env->hflags |= MIPS_HFLAG_DSP;
 370        }
 371
 372    }
 373    if (env->insn_flags & ISA_MIPS32R2) {
 374        if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 375            env->hflags |= MIPS_HFLAG_COP1X;
 376        }
 377    } else if (env->insn_flags & ISA_MIPS32) {
 378        if (env->hflags & MIPS_HFLAG_64) {
 379            env->hflags |= MIPS_HFLAG_COP1X;
 380        }
 381    } else if (env->insn_flags & ISA_MIPS4) {
 382        /* All supported MIPS IV CPUs use the XX (CU3) to enable
 383           and disable the MIPS IV extensions to the MIPS III ISA.
 384           Some other MIPS IV CPUs ignore the bit, so the check here
 385           would be too restrictive for them.  */
 386        if (env->CP0_Status & (1U << CP0St_CU3)) {
 387            env->hflags |= MIPS_HFLAG_COP1X;
 388        }
 389    }
 390    if (env->insn_flags & ASE_MSA) {
 391        if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 392            env->hflags |= MIPS_HFLAG_MSA;
 393        }
 394    }
 395    if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 396        if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 397            env->hflags |= MIPS_HFLAG_FRE;
 398        }
 399    }
 400    if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 401        if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 402            env->hflags |= MIPS_HFLAG_ELPA;
 403        }
 404    }
 405}
 406
 407void cpu_mips_tlb_flush(CPUMIPSState *env);
 408void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 409void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 410void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 411
 412void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
 413                                          int error_code, uintptr_t pc);
 414
 415static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
 416                                                    uint32_t exception,
 417                                                    uintptr_t pc)
 418{
 419    do_raise_exception_err(env, exception, 0, pc);
 420}
 421
 422#endif
 423