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20#ifndef CPU_NIOS2_H
21#define CPU_NIOS2_H
22
23#include "qemu-common.h"
24
25#define TARGET_LONG_BITS 32
26
27#define CPUArchState struct CPUNios2State
28
29#include "exec/cpu-defs.h"
30#include "qom/cpu.h"
31struct CPUNios2State;
32typedef struct CPUNios2State CPUNios2State;
33#if !defined(CONFIG_USER_ONLY)
34#include "mmu.h"
35#endif
36
37#define TYPE_NIOS2_CPU "nios2-cpu"
38
39#define NIOS2_CPU_CLASS(klass) \
40 OBJECT_CLASS_CHECK(Nios2CPUClass, (klass), TYPE_NIOS2_CPU)
41#define NIOS2_CPU(obj) \
42 OBJECT_CHECK(Nios2CPU, (obj), TYPE_NIOS2_CPU)
43#define NIOS2_CPU_GET_CLASS(obj) \
44 OBJECT_GET_CLASS(Nios2CPUClass, (obj), TYPE_NIOS2_CPU)
45
46
47
48
49
50
51
52typedef struct Nios2CPUClass {
53
54 CPUClass parent_class;
55
56
57 DeviceRealize parent_realize;
58 void (*parent_reset)(CPUState *cpu);
59} Nios2CPUClass;
60
61#define TARGET_HAS_ICE 1
62
63
64#define RESET_ADDRESS 0x00000000
65#define EXCEPTION_ADDRESS 0x00000004
66#define FAST_TLB_MISS_ADDRESS 0x00000008
67
68
69
70#define NUM_CORE_REGS (32 + 32 + 1)
71
72
73#define R_ZERO 0
74#define R_AT 1
75#define R_RET0 2
76#define R_RET1 3
77#define R_ARG0 4
78#define R_ARG1 5
79#define R_ARG2 6
80#define R_ARG3 7
81#define R_ET 24
82#define R_BT 25
83#define R_GP 26
84#define R_SP 27
85#define R_FP 28
86#define R_EA 29
87#define R_BA 30
88#define R_RA 31
89
90
91#define CR_BASE 32
92#define CR_STATUS (CR_BASE + 0)
93#define CR_STATUS_PIE (1 << 0)
94#define CR_STATUS_U (1 << 1)
95#define CR_STATUS_EH (1 << 2)
96#define CR_STATUS_IH (1 << 3)
97#define CR_STATUS_IL (63 << 4)
98#define CR_STATUS_CRS (63 << 10)
99#define CR_STATUS_PRS (63 << 16)
100#define CR_STATUS_NMI (1 << 22)
101#define CR_STATUS_RSIE (1 << 23)
102#define CR_ESTATUS (CR_BASE + 1)
103#define CR_BSTATUS (CR_BASE + 2)
104#define CR_IENABLE (CR_BASE + 3)
105#define CR_IPENDING (CR_BASE + 4)
106#define CR_CPUID (CR_BASE + 5)
107#define CR_CTL6 (CR_BASE + 6)
108#define CR_EXCEPTION (CR_BASE + 7)
109#define CR_PTEADDR (CR_BASE + 8)
110#define CR_PTEADDR_PTBASE_SHIFT 22
111#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
112#define CR_PTEADDR_VPN_SHIFT 2
113#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
114#define CR_TLBACC (CR_BASE + 9)
115#define CR_TLBACC_IGN_SHIFT 25
116#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT)
117#define CR_TLBACC_C (1 << 24)
118#define CR_TLBACC_R (1 << 23)
119#define CR_TLBACC_W (1 << 22)
120#define CR_TLBACC_X (1 << 21)
121#define CR_TLBACC_G (1 << 20)
122#define CR_TLBACC_PFN_MASK 0x000FFFFF
123#define CR_TLBMISC (CR_BASE + 10)
124#define CR_TLBMISC_WAY_SHIFT 20
125#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
126#define CR_TLBMISC_RD (1 << 19)
127#define CR_TLBMISC_WR (1 << 18)
128#define CR_TLBMISC_PID_SHIFT 4
129#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
130#define CR_TLBMISC_DBL (1 << 3)
131#define CR_TLBMISC_BAD (1 << 2)
132#define CR_TLBMISC_PERM (1 << 1)
133#define CR_TLBMISC_D (1 << 0)
134#define CR_ENCINJ (CR_BASE + 11)
135#define CR_BADADDR (CR_BASE + 12)
136#define CR_CONFIG (CR_BASE + 13)
137#define CR_MPUBASE (CR_BASE + 14)
138#define CR_MPUACC (CR_BASE + 15)
139
140
141#define R_PC 64
142
143
144#define EXCP_BREAK -1
145#define EXCP_RESET 0
146#define EXCP_PRESET 1
147#define EXCP_IRQ 2
148#define EXCP_TRAP 3
149#define EXCP_UNIMPL 4
150#define EXCP_ILLEGAL 5
151#define EXCP_UNALIGN 6
152#define EXCP_UNALIGND 7
153#define EXCP_DIV 8
154#define EXCP_SUPERA 9
155#define EXCP_SUPERI 10
156#define EXCP_SUPERD 11
157#define EXCP_TLBD 12
158#define EXCP_TLBX 13
159#define EXCP_TLBR 14
160#define EXCP_TLBW 15
161#define EXCP_MPUI 16
162#define EXCP_MPUD 17
163
164#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
165
166#define NB_MMU_MODES 2
167
168struct CPUNios2State {
169 uint32_t regs[NUM_CORE_REGS];
170
171#if !defined(CONFIG_USER_ONLY)
172 Nios2MMU mmu;
173
174 uint32_t irq_pending;
175#endif
176
177 CPU_COMMON
178};
179
180
181
182
183
184
185
186typedef struct Nios2CPU {
187
188 CPUState parent_obj;
189
190
191 CPUNios2State env;
192 bool mmu_present;
193 uint32_t pid_num_bits;
194 uint32_t tlb_num_ways;
195 uint32_t tlb_num_entries;
196
197
198 uint32_t reset_addr;
199 uint32_t exception_addr;
200 uint32_t fast_tlb_miss_addr;
201} Nios2CPU;
202
203static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
204{
205 return NIOS2_CPU(container_of(env, Nios2CPU, env));
206}
207
208#define ENV_GET_CPU(e) CPU(nios2_env_get_cpu(e))
209
210#define ENV_OFFSET offsetof(Nios2CPU, env)
211
212void nios2_tcg_init(void);
213void nios2_cpu_do_interrupt(CPUState *cs);
214int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);
215void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env);
216void nios2_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
217 int flags);
218hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
219void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
220 MMUAccessType access_type,
221 int mmu_idx, uintptr_t retaddr);
222
223qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu);
224void nios2_check_interrupts(CPUNios2State *env);
225
226#define TARGET_PHYS_ADDR_SPACE_BITS 32
227#ifdef CONFIG_USER_ONLY
228# define TARGET_VIRT_ADDR_SPACE_BITS 31
229#else
230# define TARGET_VIRT_ADDR_SPACE_BITS 32
231#endif
232
233#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
234
235#define cpu_gen_code cpu_nios2_gen_code
236#define cpu_signal_handler cpu_nios2_signal_handler
237
238#define CPU_SAVE_VERSION 1
239
240#define TARGET_PAGE_BITS 12
241
242
243#define MMU_MODE0_SUFFIX _kernel
244#define MMU_MODE1_SUFFIX _user
245#define MMU_SUPERVISOR_IDX 0
246#define MMU_USER_IDX 1
247
248static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
249{
250 return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
251 MMU_SUPERVISOR_IDX;
252}
253
254int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address, int size,
255 int rw, int mmu_idx);
256
257static inline int cpu_interrupts_enabled(CPUNios2State *env)
258{
259 return env->regs[CR_STATUS] & CR_STATUS_PIE;
260}
261
262#include "exec/cpu-all.h"
263#include "exec/exec-all.h"
264
265static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
266 target_ulong *cs_base, uint32_t *flags)
267{
268 *pc = env->regs[R_PC];
269 *cs_base = 0;
270 *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
271}
272
273#endif
274
