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20#ifndef OPENRISC_CPU_H
21#define OPENRISC_CPU_H
22
23#define TARGET_LONG_BITS 32
24
25#define CPUArchState struct CPUOpenRISCState
26
27
28struct OpenRISCCPU;
29
30#include "qemu-common.h"
31#include "exec/cpu-defs.h"
32#include "qom/cpu.h"
33
34#define TYPE_OPENRISC_CPU "or1k-cpu"
35
36#define OPENRISC_CPU_CLASS(klass) \
37 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
38#define OPENRISC_CPU(obj) \
39 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
40#define OPENRISC_CPU_GET_CLASS(obj) \
41 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
42
43
44
45
46
47
48
49
50typedef struct OpenRISCCPUClass {
51
52 CPUClass parent_class;
53
54
55 DeviceRealize parent_realize;
56 void (*parent_reset)(CPUState *cpu);
57} OpenRISCCPUClass;
58
59#define NB_MMU_MODES 3
60#define TARGET_INSN_START_EXTRA_WORDS 1
61
62enum {
63 MMU_NOMMU_IDX = 0,
64 MMU_SUPERVISOR_IDX = 1,
65 MMU_USER_IDX = 2,
66};
67
68#define TARGET_PAGE_BITS 13
69
70#define TARGET_PHYS_ADDR_SPACE_BITS 32
71#define TARGET_VIRT_ADDR_SPACE_BITS 32
72
73#define SET_FP_CAUSE(reg, v) do {\
74 (reg) = ((reg) & ~(0x3f << 12)) | \
75 ((v & 0x3f) << 12);\
76 } while (0)
77#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
78#define UPDATE_FP_FLAGS(reg, v) do {\
79 (reg) |= ((v & 0x1f) << 2);\
80 } while (0)
81
82
83#define SPR_VR 0xFFFF003F
84
85
86#define NR_IRQS 32
87
88
89enum {
90 UPR_UP = (1 << 0),
91 UPR_DCP = (1 << 1),
92 UPR_ICP = (1 << 2),
93 UPR_DMP = (1 << 3),
94 UPR_IMP = (1 << 4),
95 UPR_MP = (1 << 5),
96 UPR_DUP = (1 << 6),
97 UPR_PCUR = (1 << 7),
98 UPR_PMP = (1 << 8),
99 UPR_PICP = (1 << 9),
100 UPR_TTP = (1 << 10),
101 UPR_CUP = (255 << 24),
102};
103
104
105enum {
106 CPUCFGR_NSGF = (15 << 0),
107 CPUCFGR_CGF = (1 << 4),
108 CPUCFGR_OB32S = (1 << 5),
109 CPUCFGR_OB64S = (1 << 6),
110 CPUCFGR_OF32S = (1 << 7),
111 CPUCFGR_OF64S = (1 << 8),
112 CPUCFGR_OV64S = (1 << 9),
113
114
115 CPUCFGR_EVBARP = (1 << 12),
116
117
118};
119
120
121enum {
122 DMMUCFGR_NTW = (3 << 0),
123 DMMUCFGR_NTS = (7 << 2),
124 DMMUCFGR_NAE = (7 << 5),
125 DMMUCFGR_CRI = (1 << 8),
126 DMMUCFGR_PRI = (1 << 9),
127 DMMUCFGR_TEIRI = (1 << 10),
128 DMMUCFGR_HTR = (1 << 11),
129};
130
131
132enum {
133 IMMUCFGR_NTW = (3 << 0),
134 IMMUCFGR_NTS = (7 << 2),
135 IMMUCFGR_NAE = (7 << 5),
136 IMMUCFGR_CRI = (1 << 8),
137 IMMUCFGR_PRI = (1 << 9),
138 IMMUCFGR_TEIRI = (1 << 10),
139 IMMUCFGR_HTR = (1 << 11),
140};
141
142
143enum {
144 PMR_SDF = (15 << 0),
145 PMR_DME = (1 << 4),
146 PMR_SME = (1 << 5),
147 PMR_DCGE = (1 << 6),
148 PMR_SUME = (1 << 7),
149};
150
151
152enum {
153 FPCSR_FPEE = 1,
154 FPCSR_RM = (3 << 1),
155 FPCSR_OVF = (1 << 3),
156 FPCSR_UNF = (1 << 4),
157 FPCSR_SNF = (1 << 5),
158 FPCSR_QNF = (1 << 6),
159 FPCSR_ZF = (1 << 7),
160 FPCSR_IXF = (1 << 8),
161 FPCSR_IVF = (1 << 9),
162 FPCSR_INF = (1 << 10),
163 FPCSR_DZF = (1 << 11),
164};
165
166
167enum {
168 EXCP_RESET = 0x1,
169 EXCP_BUSERR = 0x2,
170 EXCP_DPF = 0x3,
171 EXCP_IPF = 0x4,
172 EXCP_TICK = 0x5,
173 EXCP_ALIGN = 0x6,
174 EXCP_ILLEGAL = 0x7,
175 EXCP_INT = 0x8,
176 EXCP_DTLBMISS = 0x9,
177 EXCP_ITLBMISS = 0xa,
178 EXCP_RANGE = 0xb,
179 EXCP_SYSCALL = 0xc,
180 EXCP_FPE = 0xd,
181 EXCP_TRAP = 0xe,
182 EXCP_NR,
183};
184
185
186enum {
187 SR_SM = (1 << 0),
188 SR_TEE = (1 << 1),
189 SR_IEE = (1 << 2),
190 SR_DCE = (1 << 3),
191 SR_ICE = (1 << 4),
192 SR_DME = (1 << 5),
193 SR_IME = (1 << 6),
194 SR_LEE = (1 << 7),
195 SR_CE = (1 << 8),
196 SR_F = (1 << 9),
197 SR_CY = (1 << 10),
198 SR_OV = (1 << 11),
199 SR_OVE = (1 << 12),
200 SR_DSX = (1 << 13),
201 SR_EPH = (1 << 14),
202 SR_FO = (1 << 15),
203 SR_SUMRA = (1 << 16),
204 SR_SCE = (1 << 17),
205};
206
207
208enum {
209 TTMR_TP = (0xfffffff),
210 TTMR_IP = (1 << 28),
211 TTMR_IE = (1 << 29),
212 TTMR_M = (3 << 30),
213};
214
215
216enum {
217 TIMER_NONE = (0 << 30),
218 TIMER_INTR = (1 << 30),
219 TIMER_SHOT = (2 << 30),
220 TIMER_CONT = (3 << 30),
221};
222
223
224enum {
225 DTLB_WAYS = 1,
226 DTLB_SIZE = 64,
227 DTLB_MASK = (DTLB_SIZE-1),
228 ITLB_WAYS = 1,
229 ITLB_SIZE = 64,
230 ITLB_MASK = (ITLB_SIZE-1),
231};
232
233
234enum {
235 URE = (1 << 6),
236 UWE = (1 << 7),
237 SRE = (1 << 8),
238 SWE = (1 << 9),
239
240 SXE = (1 << 6),
241 UXE = (1 << 7),
242};
243
244
245enum {
246 TLBRET_INVALID = -3,
247 TLBRET_NOMATCH = -2,
248 TLBRET_BADADDR = -1,
249 TLBRET_MATCH = 0
250};
251
252typedef struct OpenRISCTLBEntry {
253 uint32_t mr;
254 uint32_t tr;
255} OpenRISCTLBEntry;
256
257#ifndef CONFIG_USER_ONLY
258typedef struct CPUOpenRISCTLBContext {
259 OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
260 OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
261
262 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
263 hwaddr *physical,
264 int *prot,
265 target_ulong address, int rw);
266 int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
267 hwaddr *physical,
268 int *prot,
269 target_ulong address, int rw);
270} CPUOpenRISCTLBContext;
271#endif
272
273typedef struct CPUOpenRISCState {
274 target_ulong shadow_gpr[16][32];
275
276 target_ulong pc;
277 target_ulong ppc;
278 target_ulong jmp_pc;
279
280 uint64_t mac;
281
282 target_ulong epcr;
283 target_ulong eear;
284
285 target_ulong sr_f;
286 target_ulong sr_cy;
287 target_long sr_ov;
288 uint32_t sr;
289 uint32_t vr;
290 uint32_t upr;
291 uint32_t dmmucfgr;
292 uint32_t immucfgr;
293 uint32_t esr;
294 uint32_t evbar;
295 uint32_t pmr;
296 uint32_t fpcsr;
297 float_status fp_status;
298
299 target_ulong lock_addr;
300 target_ulong lock_value;
301
302 uint32_t dflag;
303
304
305 struct {} end_reset_fields;
306
307 CPU_COMMON
308
309
310 uint32_t cpucfgr;
311
312#ifndef CONFIG_USER_ONLY
313 CPUOpenRISCTLBContext * tlb;
314
315 QEMUTimer *timer;
316 uint32_t ttmr;
317 int is_counting;
318
319 uint32_t picmr;
320 uint32_t picsr;
321#endif
322 void *irq[32];
323} CPUOpenRISCState;
324
325
326
327
328
329
330
331typedef struct OpenRISCCPU {
332
333 CPUState parent_obj;
334
335
336 CPUOpenRISCState env;
337
338} OpenRISCCPU;
339
340static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
341{
342 return container_of(env, OpenRISCCPU, env);
343}
344
345#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
346
347#define ENV_OFFSET offsetof(OpenRISCCPU, env)
348
349void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
350void openrisc_cpu_do_interrupt(CPUState *cpu);
351bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
352void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
353 fprintf_function cpu_fprintf, int flags);
354hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
355int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
356int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
357void openrisc_translate_init(void);
358int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
359 int rw, int mmu_idx);
360int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
361
362#define cpu_list cpu_openrisc_list
363#define cpu_signal_handler cpu_openrisc_signal_handler
364
365#ifndef CONFIG_USER_ONLY
366extern const struct VMStateDescription vmstate_openrisc_cpu;
367
368
369void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
370
371
372void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
373uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu);
374void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val);
375void cpu_openrisc_count_update(OpenRISCCPU *cpu);
376void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
377void cpu_openrisc_count_start(OpenRISCCPU *cpu);
378void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
379
380void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
381int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
382 hwaddr *physical,
383 int *prot, target_ulong address, int rw);
384int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
385 hwaddr *physical,
386 int *prot, target_ulong address, int rw);
387int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
388 hwaddr *physical,
389 int *prot, target_ulong address, int rw);
390#endif
391
392#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
393#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
394#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
395
396#include "exec/cpu-all.h"
397
398#define TB_FLAGS_DFLAG 1
399#define TB_FLAGS_R0_0 2
400#define TB_FLAGS_OVE SR_OVE
401
402static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i)
403{
404 return env->shadow_gpr[0][i];
405}
406
407static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
408{
409 env->shadow_gpr[0][i] = val;
410}
411
412static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
413 target_ulong *pc,
414 target_ulong *cs_base, uint32_t *flags)
415{
416 *pc = env->pc;
417 *cs_base = 0;
418 *flags = (env->dflag
419 | (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0)
420 | (env->sr & SR_OVE));
421}
422
423static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
424{
425 if (!(env->sr & SR_IME)) {
426 return MMU_NOMMU_IDX;
427 }
428 return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
429}
430
431static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
432{
433 return (env->sr
434 + env->sr_f * SR_F
435 + env->sr_cy * SR_CY
436 + (env->sr_ov < 0) * SR_OV);
437}
438
439static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val)
440{
441 env->sr_f = (val & SR_F) != 0;
442 env->sr_cy = (val & SR_CY) != 0;
443 env->sr_ov = (val & SR_OV ? -1 : 0);
444 env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
445}
446
447#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
448
449#endif
450