LXR qemu/target/openrisc/gdbstub.c

   1/*
   2 * OpenRISC gdb server stub
   3 *
   4 * Copyright (c) 2003-2005 Fabrice Bellard
   5 * Copyright (c) 2013 SUSE LINUX Products GmbH
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20#include "qemu/osdep.h"
  21#include "qemu-common.h"
  22#include "cpu.h"
  23#include "exec/gdbstub.h"
  24
  25int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
  26{
  27    OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  28    CPUOpenRISCState *env = &cpu->env;
  29
  30    if (n < 32) {
  31        return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n));
  32    } else {
  33        switch (n) {
  34        case 32:    /* PPC */
  35            return gdb_get_reg32(mem_buf, env->ppc);
  36
  37        case 33:    /* NPC (equals PC) */
  38            return gdb_get_reg32(mem_buf, env->pc);
  39
  40        case 34:    /* SR */
  41            return gdb_get_reg32(mem_buf, cpu_get_sr(env));
  42
  43        default:
  44            break;
  45        }
  46    }
  47    return 0;
  48}
  49
  50int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  51{
  52    OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  53    CPUClass *cc = CPU_GET_CLASS(cs);
  54    CPUOpenRISCState *env = &cpu->env;
  55    uint32_t tmp;
  56
  57    if (n > cc->gdb_num_core_regs) {
  58        return 0;
  59    }
  60
  61    tmp = ldl_p(mem_buf);
  62
  63    if (n < 32) {
  64        cpu_set_gpr(env, n, tmp);
  65    } else {
  66        switch (n) {
  67        case 32: /* PPC */
  68            env->ppc = tmp;
  69            break;
  70
  71        case 33: /* NPC (equals PC) */
  72            /* If setting PC to something different,
  73               also clear delayed branch status.  */
  74            if (env->pc != tmp) {
  75                env->pc = tmp;
  76                env->dflag = 0;
  77            }
  78            break;
  79
  80        case 34: /* SR */
  81            cpu_set_sr(env, tmp);
  82            break;
  83
  84        default:
  85            break;
  86        }
  87    }
  88    return 4;
  89}
  90