qemu/target/ppc/helper_regs.h
<<
>>
Prefs 
   1/*
   2 *  PowerPC emulation special registers manipulation helpers for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef HELPER_REGS_H
  21#define HELPER_REGS_H
  22
  23#include "qemu/main-loop.h"
  24
  25/* Swap temporary saved registers with GPRs */
  26static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
  27{
  28    target_ulong tmp;
  29
  30    tmp = env->gpr[0];
  31    env->gpr[0] = env->tgpr[0];
  32    env->tgpr[0] = tmp;
  33    tmp = env->gpr[1];
  34    env->gpr[1] = env->tgpr[1];
  35    env->tgpr[1] = tmp;
  36    tmp = env->gpr[2];
  37    env->gpr[2] = env->tgpr[2];
  38    env->tgpr[2] = tmp;
  39    tmp = env->gpr[3];
  40    env->gpr[3] = env->tgpr[3];
  41    env->tgpr[3] = tmp;
  42}
  43
  44static inline void hreg_compute_mem_idx(CPUPPCState *env)
  45{
  46    /* This is our encoding for server processors. The architecture
  47     * specifies that there is no such thing as userspace with
  48     * translation off, however it appears that MacOS does it and
  49     * some 32-bit CPUs support it. Weird...
  50     *
  51     *   0 = Guest User space virtual mode
  52     *   1 = Guest Kernel space virtual mode
  53     *   2 = Guest User space real mode
  54     *   3 = Guest Kernel space real mode
  55     *   4 = HV User space virtual mode
  56     *   5 = HV Kernel space virtual mode
  57     *   6 = HV User space real mode
  58     *   7 = HV Kernel space real mode
  59     *
  60     * For BookE, we need 8 MMU modes as follow:
  61     *
  62     *  0 = AS 0 HV User space
  63     *  1 = AS 0 HV Kernel space
  64     *  2 = AS 1 HV User space
  65     *  3 = AS 1 HV Kernel space
  66     *  4 = AS 0 Guest User space
  67     *  5 = AS 0 Guest Kernel space
  68     *  6 = AS 1 Guest User space
  69     *  7 = AS 1 Guest Kernel space
  70     */
  71    if (env->mmu_model & POWERPC_MMU_BOOKE) {
  72        env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  73        env->immu_idx += msr_is ? 2 : 0;
  74        env->dmmu_idx += msr_ds ? 2 : 0;
  75        env->immu_idx += msr_gs ? 4 : 0;
  76        env->dmmu_idx += msr_gs ? 4 : 0;
  77    } else {
  78        env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  79        env->immu_idx += msr_ir ? 0 : 2;
  80        env->dmmu_idx += msr_dr ? 0 : 2;
  81        env->immu_idx += msr_hv ? 4 : 0;
  82        env->dmmu_idx += msr_hv ? 4 : 0;
  83    }
  84}
  85
  86static inline void hreg_compute_hflags(CPUPPCState *env)
  87{
  88    target_ulong hflags_mask;
  89
  90    /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
  91    hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
  92        (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
  93        (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
  94    hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
  95    hreg_compute_mem_idx(env);
  96    env->hflags = env->msr & hflags_mask;
  97    /* Merge with hflags coming from other registers */
  98    env->hflags |= env->hflags_nmsr;
  99}
 100
 101static inline void cpu_interrupt_exittb(CPUState *cs)
 102{
 103    if (!qemu_mutex_iothread_locked()) {
 104        qemu_mutex_lock_iothread();
 105        cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 106        qemu_mutex_unlock_iothread();
 107    } else {
 108        cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 109    }
 110}
 111
 112static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
 113                                 int alter_hv)
 114{
 115    int excp;
 116#if !defined(CONFIG_USER_ONLY)
 117    CPUState *cs = CPU(ppc_env_get_cpu(env));
 118#endif
 119
 120    excp = 0;
 121    value &= env->msr_mask;
 122#if !defined(CONFIG_USER_ONLY)
 123    /* Neither mtmsr nor guest state can alter HV */
 124    if (!alter_hv || !(env->msr & MSR_HVB)) {
 125        value &= ~MSR_HVB;
 126        value |= env->msr & MSR_HVB;
 127    }
 128    if (((value >> MSR_IR) & 1) != msr_ir ||
 129        ((value >> MSR_DR) & 1) != msr_dr) {
 130        cpu_interrupt_exittb(cs);
 131    }
 132    if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
 133        ((value >> MSR_GS) & 1) != msr_gs) {
 134        cpu_interrupt_exittb(cs);
 135    }
 136    if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
 137                 ((value ^ env->msr) & (1 << MSR_TGPR)))) {
 138        /* Swap temporary saved registers with GPRs */
 139        hreg_swap_gpr_tgpr(env);
 140    }
 141    if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
 142        /* Change the exception prefix on PowerPC 601 */
 143        env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
 144    }
 145    /* If PR=1 then EE, IR and DR must be 1
 146     *
 147     * Note: We only enforce this on 64-bit server processors.
 148     * It appears that:
 149     * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
 150     *   exploits it.
 151     * - 64-bit embedded implementations do not need any operation to be
 152     *   performed when PR is set.
 153     */
 154    if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
 155        value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
 156    }
 157#endif
 158    env->msr = value;
 159    hreg_compute_hflags(env);
 160#if !defined(CONFIG_USER_ONLY)
 161    if (unlikely(msr_pow == 1)) {
 162        if (!env->pending_interrupts && (*env->check_pow)(env)) {
 163            cs->halted = 1;
 164            excp = EXCP_HALTED;
 165        }
 166    }
 167#endif
 168
 169    return excp;
 170}
 171
 172#if !defined(CONFIG_USER_ONLY)
 173static inline void check_tlb_flush(CPUPPCState *env, bool global)
 174{
 175    CPUState *cs = CPU(ppc_env_get_cpu(env));
 176    if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
 177        tlb_flush(cs);
 178        env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 179    }
 180
 181    /* Propagate TLB invalidations to other CPUs when the guest uses broadcast
 182     * TLB invalidation instructions.
 183     */
 184    if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
 185        CPUState *other_cs;
 186        CPU_FOREACH(other_cs) {
 187            if (other_cs != cs) {
 188                PowerPCCPU *cpu = POWERPC_CPU(other_cs);
 189                CPUPPCState *other_env = &cpu->env;
 190
 191                other_env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 192                tlb_flush(other_cs);
 193            }
 194        }
 195        env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
 196    }
 197}
 198#else
 199static inline void check_tlb_flush(CPUPPCState *env, bool global) { }
 200#endif
 201
 202#endif /* HELPER_REGS_H */
 203
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.