LXR qemu/target/s390x/cpu.h

   1/*
   2 * S/390 virtual CPU header
   3 *
   4 *  Copyright (c) 2009 Ulrich Hecht
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * Contributions after 2012-10-29 are licensed under the terms of the
  17 * GNU GPL, version 2 or (at your option) any later version.
  18 *
  19 * You should have received a copy of the GNU (Lesser) General Public
  20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21 */
  22
  23#ifndef S390X_CPU_H
  24#define S390X_CPU_H
  25
  26#include "qemu-common.h"
  27#include "cpu-qom.h"
  28#include "cpu_models.h"
  29
  30#define TARGET_LONG_BITS 64
  31
  32#define ELF_MACHINE_UNAME "S390X"
  33
  34#define CPUArchState struct CPUS390XState
  35
  36#include "exec/cpu-defs.h"
  37#define TARGET_PAGE_BITS 12
  38
  39#define TARGET_PHYS_ADDR_SPACE_BITS 64
  40#define TARGET_VIRT_ADDR_SPACE_BITS 64
  41
  42#include "exec/cpu-all.h"
  43
  44#define NB_MMU_MODES 4
  45#define TARGET_INSN_START_EXTRA_WORDS 1
  46
  47#define MMU_MODE0_SUFFIX _primary
  48#define MMU_MODE1_SUFFIX _secondary
  49#define MMU_MODE2_SUFFIX _home
  50#define MMU_MODE3_SUFFIX _real
  51
  52#define MMU_USER_IDX 0
  53
  54#define S390_MAX_CPUS 248
  55
  56typedef struct PSW {
  57    uint64_t mask;
  58    uint64_t addr;
  59} PSW;
  60
  61struct CPUS390XState {
  62    uint64_t regs[16];     /* GP registers */
  63    /*
  64     * The floating point registers are part of the vector registers.
  65     * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  66     */
  67    CPU_DoubleU vregs[32][2];  /* vector registers */
  68    uint32_t aregs[16];    /* access registers */
  69    uint8_t riccb[64];     /* runtime instrumentation control */
  70    uint64_t gscb[4];      /* guarded storage control */
  71
  72    /* Fields up to this point are not cleared by initial CPU reset */
  73    struct {} start_initial_reset_fields;
  74
  75    uint32_t fpc;          /* floating-point control register */
  76    uint32_t cc_op;
  77    bool bpbc;             /* branch prediction blocking */
  78
  79    float_status fpu_status; /* passed to softfloat lib */
  80
  81    /* The low part of a 128-bit return, or remainder of a divide.  */
  82    uint64_t retxl;
  83
  84    PSW psw;
  85
  86    S390CrashReason crash_reason;
  87
  88    uint64_t cc_src;
  89    uint64_t cc_dst;
  90    uint64_t cc_vr;
  91
  92    uint64_t ex_value;
  93
  94    uint64_t __excp_addr;
  95    uint64_t psa;
  96
  97    uint32_t int_pgm_code;
  98    uint32_t int_pgm_ilen;
  99
 100    uint32_t int_svc_code;
 101    uint32_t int_svc_ilen;
 102
 103    uint64_t per_address;
 104    uint16_t per_perc_atmid;
 105
 106    uint64_t cregs[16]; /* control registers */
 107
 108    int pending_int;
 109    uint16_t external_call_addr;
 110    DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
 111
 112    uint64_t ckc;
 113    uint64_t cputm;
 114    uint32_t todpr;
 115
 116    uint64_t pfault_token;
 117    uint64_t pfault_compare;
 118    uint64_t pfault_select;
 119
 120    uint64_t gbea;
 121    uint64_t pp;
 122
 123    /* Fields up to this point are cleared by a CPU reset */
 124    struct {} end_reset_fields;
 125
 126    CPU_COMMON
 127
 128#if !defined(CONFIG_USER_ONLY)
 129    uint32_t core_id; /* PoP "CPU address", same as cpu_index */
 130    uint64_t cpuid;
 131#endif
 132
 133    uint64_t tod_offset;
 134    uint64_t tod_basetime;
 135    QEMUTimer *tod_timer;
 136
 137    QEMUTimer *cpu_timer;
 138
 139    /*
 140     * The cpu state represents the logical state of a cpu. In contrast to other
 141     * architectures, there is a difference between a halt and a stop on s390.
 142     * If all cpus are either stopped (including check stop) or in the disabled
 143     * wait state, the vm can be shut down.
 144     * The acceptable cpu_state values are defined in the CpuInfoS390State
 145     * enum.
 146     */
 147    uint8_t cpu_state;
 148
 149    /* currently processed sigp order */
 150    uint8_t sigp_order;
 151
 152};
 153
 154static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 155{
 156    return &cs->vregs[nr][0];
 157}
 158
 159/**
 160 * S390CPU:
 161 * @env: #CPUS390XState.
 162 *
 163 * An S/390 CPU.
 164 */
 165struct S390CPU {
 166    /*< private >*/
 167    CPUState parent_obj;
 168    /*< public >*/
 169
 170    CPUS390XState env;
 171    S390CPUModel *model;
 172    /* needed for live migration */
 173    void *irqstate;
 174    uint32_t irqstate_saved_size;
 175};
 176
 177static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
 178{
 179    return container_of(env, S390CPU, env);
 180}
 181
 182#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
 183
 184#define ENV_OFFSET offsetof(S390CPU, env)
 185
 186#ifndef CONFIG_USER_ONLY
 187extern const struct VMStateDescription vmstate_s390_cpu;
 188#endif
 189
 190/* distinguish between 24 bit and 31 bit addressing */
 191#define HIGH_ORDER_BIT 0x80000000
 192
 193/* Interrupt Codes */
 194/* Program Interrupts */
 195#define PGM_OPERATION                   0x0001
 196#define PGM_PRIVILEGED                  0x0002
 197#define PGM_EXECUTE                     0x0003
 198#define PGM_PROTECTION                  0x0004
 199#define PGM_ADDRESSING                  0x0005
 200#define PGM_SPECIFICATION               0x0006
 201#define PGM_DATA                        0x0007
 202#define PGM_FIXPT_OVERFLOW              0x0008
 203#define PGM_FIXPT_DIVIDE                0x0009
 204#define PGM_DEC_OVERFLOW                0x000a
 205#define PGM_DEC_DIVIDE                  0x000b
 206#define PGM_HFP_EXP_OVERFLOW            0x000c
 207#define PGM_HFP_EXP_UNDERFLOW           0x000d
 208#define PGM_HFP_SIGNIFICANCE            0x000e
 209#define PGM_HFP_DIVIDE                  0x000f
 210#define PGM_SEGMENT_TRANS               0x0010
 211#define PGM_PAGE_TRANS                  0x0011
 212#define PGM_TRANS_SPEC                  0x0012
 213#define PGM_SPECIAL_OP                  0x0013
 214#define PGM_OPERAND                     0x0015
 215#define PGM_TRACE_TABLE                 0x0016
 216#define PGM_SPACE_SWITCH                0x001c
 217#define PGM_HFP_SQRT                    0x001d
 218#define PGM_PC_TRANS_SPEC               0x001f
 219#define PGM_AFX_TRANS                   0x0020
 220#define PGM_ASX_TRANS                   0x0021
 221#define PGM_LX_TRANS                    0x0022
 222#define PGM_EX_TRANS                    0x0023
 223#define PGM_PRIM_AUTH                   0x0024
 224#define PGM_SEC_AUTH                    0x0025
 225#define PGM_ALET_SPEC                   0x0028
 226#define PGM_ALEN_SPEC                   0x0029
 227#define PGM_ALE_SEQ                     0x002a
 228#define PGM_ASTE_VALID                  0x002b
 229#define PGM_ASTE_SEQ                    0x002c
 230#define PGM_EXT_AUTH                    0x002d
 231#define PGM_STACK_FULL                  0x0030
 232#define PGM_STACK_EMPTY                 0x0031
 233#define PGM_STACK_SPEC                  0x0032
 234#define PGM_STACK_TYPE                  0x0033
 235#define PGM_STACK_OP                    0x0034
 236#define PGM_ASCE_TYPE                   0x0038
 237#define PGM_REG_FIRST_TRANS             0x0039
 238#define PGM_REG_SEC_TRANS               0x003a
 239#define PGM_REG_THIRD_TRANS             0x003b
 240#define PGM_MONITOR                     0x0040
 241#define PGM_PER                         0x0080
 242#define PGM_CRYPTO                      0x0119
 243
 244/* External Interrupts */
 245#define EXT_INTERRUPT_KEY               0x0040
 246#define EXT_CLOCK_COMP                  0x1004
 247#define EXT_CPU_TIMER                   0x1005
 248#define EXT_MALFUNCTION                 0x1200
 249#define EXT_EMERGENCY                   0x1201
 250#define EXT_EXTERNAL_CALL               0x1202
 251#define EXT_ETR                         0x1406
 252#define EXT_SERVICE                     0x2401
 253#define EXT_VIRTIO                      0x2603
 254
 255/* PSW defines */
 256#undef PSW_MASK_PER
 257#undef PSW_MASK_DAT
 258#undef PSW_MASK_IO
 259#undef PSW_MASK_EXT
 260#undef PSW_MASK_KEY
 261#undef PSW_SHIFT_KEY
 262#undef PSW_MASK_MCHECK
 263#undef PSW_MASK_WAIT
 264#undef PSW_MASK_PSTATE
 265#undef PSW_MASK_ASC
 266#undef PSW_SHIFT_ASC
 267#undef PSW_MASK_CC
 268#undef PSW_MASK_PM
 269#undef PSW_SHIFT_MASK_PM
 270#undef PSW_MASK_64
 271#undef PSW_MASK_32
 272#undef PSW_MASK_ESA_ADDR
 273
 274#define PSW_MASK_PER            0x4000000000000000ULL
 275#define PSW_MASK_DAT            0x0400000000000000ULL
 276#define PSW_MASK_IO             0x0200000000000000ULL
 277#define PSW_MASK_EXT            0x0100000000000000ULL
 278#define PSW_MASK_KEY            0x00F0000000000000ULL
 279#define PSW_SHIFT_KEY           52
 280#define PSW_MASK_MCHECK         0x0004000000000000ULL
 281#define PSW_MASK_WAIT           0x0002000000000000ULL
 282#define PSW_MASK_PSTATE         0x0001000000000000ULL
 283#define PSW_MASK_ASC            0x0000C00000000000ULL
 284#define PSW_SHIFT_ASC           46
 285#define PSW_MASK_CC             0x0000300000000000ULL
 286#define PSW_MASK_PM             0x00000F0000000000ULL
 287#define PSW_SHIFT_MASK_PM       40
 288#define PSW_MASK_64             0x0000000100000000ULL
 289#define PSW_MASK_32             0x0000000080000000ULL
 290#define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 291
 292#undef PSW_ASC_PRIMARY
 293#undef PSW_ASC_ACCREG
 294#undef PSW_ASC_SECONDARY
 295#undef PSW_ASC_HOME
 296
 297#define PSW_ASC_PRIMARY         0x0000000000000000ULL
 298#define PSW_ASC_ACCREG          0x0000400000000000ULL
 299#define PSW_ASC_SECONDARY       0x0000800000000000ULL
 300#define PSW_ASC_HOME            0x0000C00000000000ULL
 301
 302/* the address space values shifted */
 303#define AS_PRIMARY              0
 304#define AS_ACCREG               1
 305#define AS_SECONDARY            2
 306#define AS_HOME                 3
 307
 308/* tb flags */
 309
 310#define FLAG_MASK_PSW_SHIFT     31
 311#define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
 312#define FLAG_MASK_DAT           (PSW_MASK_DAT    >> FLAG_MASK_PSW_SHIFT)
 313#define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
 314#define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
 315#define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
 316#define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
 317#define FLAG_MASK_PSW           (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
 318                                | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
 319
 320/* Control register 0 bits */
 321#define CR0_LOWPROT             0x0000000010000000ULL
 322#define CR0_SECONDARY           0x0000000004000000ULL
 323#define CR0_EDAT                0x0000000000800000ULL
 324#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
 325#define CR0_EXTERNAL_CALL_SC    0x0000000000002000ULL
 326#define CR0_CKC_SC              0x0000000000000800ULL
 327#define CR0_CPU_TIMER_SC        0x0000000000000400ULL
 328#define CR0_SERVICE_SC          0x0000000000000200ULL
 329
 330/* Control register 14 bits */
 331#define CR14_CHANNEL_REPORT_SC  0x0000000010000000ULL
 332
 333/* MMU */
 334#define MMU_PRIMARY_IDX         0
 335#define MMU_SECONDARY_IDX       1
 336#define MMU_HOME_IDX            2
 337#define MMU_REAL_IDX            3
 338
 339static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 340{
 341    if (!(env->psw.mask & PSW_MASK_DAT)) {
 342        return MMU_REAL_IDX;
 343    }
 344
 345    switch (env->psw.mask & PSW_MASK_ASC) {
 346    case PSW_ASC_PRIMARY:
 347        return MMU_PRIMARY_IDX;
 348    case PSW_ASC_SECONDARY:
 349        return MMU_SECONDARY_IDX;
 350    case PSW_ASC_HOME:
 351        return MMU_HOME_IDX;
 352    case PSW_ASC_ACCREG:
 353        /* Fallthrough: access register mode is not yet supported */
 354    default:
 355        abort();
 356    }
 357}
 358
 359static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 360                                        target_ulong *cs_base, uint32_t *flags)
 361{
 362    *pc = env->psw.addr;
 363    *cs_base = env->ex_value;
 364    *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
 365}
 366
 367/* PER bits from control register 9 */
 368#define PER_CR9_EVENT_BRANCH           0x80000000
 369#define PER_CR9_EVENT_IFETCH           0x40000000
 370#define PER_CR9_EVENT_STORE            0x20000000
 371#define PER_CR9_EVENT_STORE_REAL       0x08000000
 372#define PER_CR9_EVENT_NULLIFICATION    0x01000000
 373#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 374#define PER_CR9_CONTROL_ALTERATION     0x00200000
 375
 376/* PER bits from the PER CODE/ATMID/AI in lowcore */
 377#define PER_CODE_EVENT_BRANCH          0x8000
 378#define PER_CODE_EVENT_IFETCH          0x4000
 379#define PER_CODE_EVENT_STORE           0x2000
 380#define PER_CODE_EVENT_STORE_REAL      0x0800
 381#define PER_CODE_EVENT_NULLIFICATION   0x0100
 382
 383#define EXCP_EXT 1 /* external interrupt */
 384#define EXCP_SVC 2 /* supervisor call (syscall) */
 385#define EXCP_PGM 3 /* program interruption */
 386#define EXCP_RESTART 4 /* restart interrupt */
 387#define EXCP_STOP 5 /* stop interrupt */
 388#define EXCP_IO  7 /* I/O interrupt */
 389#define EXCP_MCHK 8 /* machine check */
 390
 391#define INTERRUPT_EXT_CPU_TIMER          (1 << 3)
 392#define INTERRUPT_EXT_CLOCK_COMPARATOR   (1 << 4)
 393#define INTERRUPT_EXTERNAL_CALL          (1 << 5)
 394#define INTERRUPT_EMERGENCY_SIGNAL       (1 << 6)
 395#define INTERRUPT_RESTART                (1 << 7)
 396#define INTERRUPT_STOP                   (1 << 8)
 397
 398/* Program Status Word.  */
 399#define S390_PSWM_REGNUM 0
 400#define S390_PSWA_REGNUM 1
 401/* General Purpose Registers.  */
 402#define S390_R0_REGNUM 2
 403#define S390_R1_REGNUM 3
 404#define S390_R2_REGNUM 4
 405#define S390_R3_REGNUM 5
 406#define S390_R4_REGNUM 6
 407#define S390_R5_REGNUM 7
 408#define S390_R6_REGNUM 8
 409#define S390_R7_REGNUM 9
 410#define S390_R8_REGNUM 10
 411#define S390_R9_REGNUM 11
 412#define S390_R10_REGNUM 12
 413#define S390_R11_REGNUM 13
 414#define S390_R12_REGNUM 14
 415#define S390_R13_REGNUM 15
 416#define S390_R14_REGNUM 16
 417#define S390_R15_REGNUM 17
 418/* Total Core Registers. */
 419#define S390_NUM_CORE_REGS 18
 420
 421static inline void setcc(S390CPU *cpu, uint64_t cc)
 422{
 423    CPUS390XState *env = &cpu->env;
 424
 425    env->psw.mask &= ~(3ull << 44);
 426    env->psw.mask |= (cc & 3) << 44;
 427    env->cc_op = cc;
 428}
 429
 430/* STSI */
 431#define STSI_R0_FC_MASK         0x00000000f0000000ULL
 432#define STSI_R0_FC_CURRENT      0x0000000000000000ULL
 433#define STSI_R0_FC_LEVEL_1      0x0000000010000000ULL
 434#define STSI_R0_FC_LEVEL_2      0x0000000020000000ULL
 435#define STSI_R0_FC_LEVEL_3      0x0000000030000000ULL
 436#define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 437#define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 438#define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 439#define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 440
 441/* Basic Machine Configuration */
 442typedef struct SysIB_111 {
 443    uint8_t  res1[32];
 444    uint8_t  manuf[16];
 445    uint8_t  type[4];
 446    uint8_t  res2[12];
 447    uint8_t  model[16];
 448    uint8_t  sequence[16];
 449    uint8_t  plant[4];
 450    uint8_t  res3[3996];
 451} SysIB_111;
 452QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
 453
 454/* Basic Machine CPU */
 455typedef struct SysIB_121 {
 456    uint8_t  res1[80];
 457    uint8_t  sequence[16];
 458    uint8_t  plant[4];
 459    uint8_t  res2[2];
 460    uint16_t cpu_addr;
 461    uint8_t  res3[3992];
 462} SysIB_121;
 463QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
 464
 465/* Basic Machine CPUs */
 466typedef struct SysIB_122 {
 467    uint8_t res1[32];
 468    uint32_t capability;
 469    uint16_t total_cpus;
 470    uint16_t conf_cpus;
 471    uint16_t standby_cpus;
 472    uint16_t reserved_cpus;
 473    uint16_t adjustments[2026];
 474} SysIB_122;
 475QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
 476
 477/* LPAR CPU */
 478typedef struct SysIB_221 {
 479    uint8_t  res1[80];
 480    uint8_t  sequence[16];
 481    uint8_t  plant[4];
 482    uint16_t cpu_id;
 483    uint16_t cpu_addr;
 484    uint8_t  res3[3992];
 485} SysIB_221;
 486QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
 487
 488/* LPAR CPUs */
 489typedef struct SysIB_222 {
 490    uint8_t  res1[32];
 491    uint16_t lpar_num;
 492    uint8_t  res2;
 493    uint8_t  lcpuc;
 494    uint16_t total_cpus;
 495    uint16_t conf_cpus;
 496    uint16_t standby_cpus;
 497    uint16_t reserved_cpus;
 498    uint8_t  name[8];
 499    uint32_t caf;
 500    uint8_t  res3[16];
 501    uint16_t dedicated_cpus;
 502    uint16_t shared_cpus;
 503    uint8_t  res4[4020];
 504} SysIB_222;
 505QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
 506
 507/* VM CPUs */
 508typedef struct SysIB_322 {
 509    uint8_t  res1[31];
 510    uint8_t  count;
 511    struct {
 512        uint8_t  res2[4];
 513        uint16_t total_cpus;
 514        uint16_t conf_cpus;
 515        uint16_t standby_cpus;
 516        uint16_t reserved_cpus;
 517        uint8_t  name[8];
 518        uint32_t caf;
 519        uint8_t  cpi[16];
 520        uint8_t res5[3];
 521        uint8_t ext_name_encoding;
 522        uint32_t res3;
 523        uint8_t uuid[16];
 524    } vm[8];
 525    uint8_t res4[1504];
 526    uint8_t ext_names[8][256];
 527} SysIB_322;
 528QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
 529
 530typedef union SysIB {
 531    SysIB_111 sysib_111;
 532    SysIB_121 sysib_121;
 533    SysIB_122 sysib_122;
 534    SysIB_221 sysib_221;
 535    SysIB_222 sysib_222;
 536    SysIB_322 sysib_322;
 537} SysIB;
 538QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
 539
 540/* MMU defines */
 541#define ASCE_ORIGIN           (~0xfffULL) /* segment table origin             */
 542#define ASCE_SUBSPACE         0x200       /* subspace group control           */
 543#define ASCE_PRIVATE_SPACE    0x100       /* private space control            */
 544#define ASCE_ALT_EVENT        0x80        /* storage alteration event control */
 545#define ASCE_SPACE_SWITCH     0x40        /* space switch event               */
 546#define ASCE_REAL_SPACE       0x20        /* real space control               */
 547#define ASCE_TYPE_MASK        0x0c        /* asce table type mask             */
 548#define ASCE_TYPE_REGION1     0x0c        /* region first table type          */
 549#define ASCE_TYPE_REGION2     0x08        /* region second table type         */
 550#define ASCE_TYPE_REGION3     0x04        /* region third table type          */
 551#define ASCE_TYPE_SEGMENT     0x00        /* segment table type               */
 552#define ASCE_TABLE_LENGTH     0x03        /* region table length              */
 553
 554#define REGION_ENTRY_ORIGIN   (~0xfffULL) /* region/segment table origin    */
 555#define REGION_ENTRY_RO       0x200       /* region/segment protection bit  */
 556#define REGION_ENTRY_TF       0xc0        /* region/segment table offset    */
 557#define REGION_ENTRY_INV      0x20        /* invalid region table entry     */
 558#define REGION_ENTRY_TYPE_MASK 0x0c       /* region/segment table type mask */
 559#define REGION_ENTRY_TYPE_R1  0x0c        /* region first table type        */
 560#define REGION_ENTRY_TYPE_R2  0x08        /* region second table type       */
 561#define REGION_ENTRY_TYPE_R3  0x04        /* region third table type        */
 562#define REGION_ENTRY_LENGTH   0x03        /* region third length            */
 563
 564#define SEGMENT_ENTRY_ORIGIN  (~0x7ffULL) /* segment table origin        */
 565#define SEGMENT_ENTRY_FC      0x400       /* format control              */
 566#define SEGMENT_ENTRY_RO      0x200       /* page protection bit         */
 567#define SEGMENT_ENTRY_INV     0x20        /* invalid segment table entry */
 568
 569#define VADDR_PX              0xff000     /* page index bits   */
 570
 571#define PAGE_RO               0x200       /* HW read-only bit  */
 572#define PAGE_INVALID          0x400       /* HW invalid bit    */
 573#define PAGE_RES0             0x800       /* bit must be zero  */
 574
 575#define SK_C                    (0x1 << 1)
 576#define SK_R                    (0x1 << 2)
 577#define SK_F                    (0x1 << 3)
 578#define SK_ACC_MASK             (0xf << 4)
 579
 580/* SIGP order codes */
 581#define SIGP_SENSE             0x01
 582#define SIGP_EXTERNAL_CALL     0x02
 583#define SIGP_EMERGENCY         0x03
 584#define SIGP_START             0x04
 585#define SIGP_STOP              0x05
 586#define SIGP_RESTART           0x06
 587#define SIGP_STOP_STORE_STATUS 0x09
 588#define SIGP_INITIAL_CPU_RESET 0x0b
 589#define SIGP_CPU_RESET         0x0c
 590#define SIGP_SET_PREFIX        0x0d
 591#define SIGP_STORE_STATUS_ADDR 0x0e
 592#define SIGP_SET_ARCH          0x12
 593#define SIGP_COND_EMERGENCY    0x13
 594#define SIGP_SENSE_RUNNING     0x15
 595#define SIGP_STORE_ADTL_STATUS 0x17
 596
 597/* SIGP condition codes */
 598#define SIGP_CC_ORDER_CODE_ACCEPTED 0
 599#define SIGP_CC_STATUS_STORED       1
 600#define SIGP_CC_BUSY                2
 601#define SIGP_CC_NOT_OPERATIONAL     3
 602
 603/* SIGP status bits */
 604#define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 605#define SIGP_STAT_NOT_RUNNING       0x00000400UL
 606#define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 607#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 608#define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 609#define SIGP_STAT_STOPPED           0x00000040UL
 610#define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 611#define SIGP_STAT_CHECK_STOP        0x00000010UL
 612#define SIGP_STAT_INOPERATIVE       0x00000004UL
 613#define SIGP_STAT_INVALID_ORDER     0x00000002UL
 614#define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 615
 616/* SIGP SET ARCHITECTURE modes */
 617#define SIGP_MODE_ESA_S390 0
 618#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 619#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 620
 621/* SIGP order code mask corresponding to bit positions 56-63 */
 622#define SIGP_ORDER_MASK 0x000000ff
 623
 624/* machine check interruption code */
 625
 626/* subclasses */
 627#define MCIC_SC_SD 0x8000000000000000ULL
 628#define MCIC_SC_PD 0x4000000000000000ULL
 629#define MCIC_SC_SR 0x2000000000000000ULL
 630#define MCIC_SC_CD 0x0800000000000000ULL
 631#define MCIC_SC_ED 0x0400000000000000ULL
 632#define MCIC_SC_DG 0x0100000000000000ULL
 633#define MCIC_SC_W  0x0080000000000000ULL
 634#define MCIC_SC_CP 0x0040000000000000ULL
 635#define MCIC_SC_SP 0x0020000000000000ULL
 636#define MCIC_SC_CK 0x0010000000000000ULL
 637
 638/* subclass modifiers */
 639#define MCIC_SCM_B  0x0002000000000000ULL
 640#define MCIC_SCM_DA 0x0000000020000000ULL
 641#define MCIC_SCM_AP 0x0000000000080000ULL
 642
 643/* storage errors */
 644#define MCIC_SE_SE 0x0000800000000000ULL
 645#define MCIC_SE_SC 0x0000400000000000ULL
 646#define MCIC_SE_KE 0x0000200000000000ULL
 647#define MCIC_SE_DS 0x0000100000000000ULL
 648#define MCIC_SE_IE 0x0000000080000000ULL
 649
 650/* validity bits */
 651#define MCIC_VB_WP 0x0000080000000000ULL
 652#define MCIC_VB_MS 0x0000040000000000ULL
 653#define MCIC_VB_PM 0x0000020000000000ULL
 654#define MCIC_VB_IA 0x0000010000000000ULL
 655#define MCIC_VB_FA 0x0000008000000000ULL
 656#define MCIC_VB_VR 0x0000004000000000ULL
 657#define MCIC_VB_EC 0x0000002000000000ULL
 658#define MCIC_VB_FP 0x0000001000000000ULL
 659#define MCIC_VB_GR 0x0000000800000000ULL
 660#define MCIC_VB_CR 0x0000000400000000ULL
 661#define MCIC_VB_ST 0x0000000100000000ULL
 662#define MCIC_VB_AR 0x0000000040000000ULL
 663#define MCIC_VB_GS 0x0000000008000000ULL
 664#define MCIC_VB_PR 0x0000000000200000ULL
 665#define MCIC_VB_FC 0x0000000000100000ULL
 666#define MCIC_VB_CT 0x0000000000020000ULL
 667#define MCIC_VB_CC 0x0000000000010000ULL
 668
 669static inline uint64_t s390_build_validity_mcic(void)
 670{
 671    uint64_t mcic;
 672
 673    /*
 674     * Indicate all validity bits (no damage) only. Other bits have to be
 675     * added by the caller. (storage errors, subclasses and subclass modifiers)
 676     */
 677    mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
 678           MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
 679           MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
 680    if (s390_has_feat(S390_FEAT_VECTOR)) {
 681        mcic |= MCIC_VB_VR;
 682    }
 683    if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
 684        mcic |= MCIC_VB_GS;
 685    }
 686    return mcic;
 687}
 688
 689
 690/* cpu.c */
 691int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low);
 692int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low);
 693void s390_crypto_reset(void);
 694bool s390_get_squash_mcss(void);
 695int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
 696void s390_cmma_reset(void);
 697void s390_enable_css_support(S390CPU *cpu);
 698int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
 699                                int vq, bool assign);
 700#ifndef CONFIG_USER_ONLY
 701unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 702#else
 703static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 704{
 705    return 0;
 706}
 707#endif /* CONFIG_USER_ONLY */
 708static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 709{
 710    return cpu->env.cpu_state;
 711}
 712
 713
 714/* cpu_models.c */
 715void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 716#define cpu_list s390_cpu_list
 717void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
 718                             const S390FeatInit feat_init);
 719
 720
 721/* helper.c */
 722#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
 723#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 724#define CPU_RESOLVING_TYPE TYPE_S390_CPU
 725
 726/* you can call this signal handler from your SIGBUS and SIGSEGV
 727   signal handlers to inform the virtual CPU of exceptions. non zero
 728   is returned if the signal was handled by the virtual CPU.  */
 729int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
 730#define cpu_signal_handler cpu_s390x_signal_handler
 731
 732
 733/* interrupt.c */
 734void s390_crw_mchk(void);
 735void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
 736                       uint32_t io_int_parm, uint32_t io_int_word);
 737/* automatically detect the instruction length */
 738#define ILEN_AUTO                   0xff
 739#define RA_IGNORED                  0
 740void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
 741                            uintptr_t ra);
 742/* service interrupts are floating therefore we must not pass an cpustate */
 743void s390_sclp_extint(uint32_t parm);
 744
 745/* mmu_helper.c */
 746int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 747                         int len, bool is_write);
 748#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 749        s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 750#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 751        s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 752#define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len)   \
 753        s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
 754#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 755        s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 756void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
 757
 758
 759/* sigp.c */
 760int s390_cpu_restart(S390CPU *cpu);
 761void s390_init_sigp(void);
 762
 763
 764/* outside of target/s390x/ */
 765S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 766
 767#endif
 768