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21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "internal.h"
24#include "exec/gdbstub.h"
25#include "qemu/timer.h"
26#include "exec/exec-all.h"
27#include "hw/s390x/ioinst.h"
28#include "sysemu/hw_accel.h"
29#ifndef CONFIG_USER_ONLY
30#include "sysemu/sysemu.h"
31#endif
32
33#ifndef CONFIG_USER_ONLY
34void s390x_tod_timer(void *opaque)
35{
36 cpu_inject_clock_comparator((S390CPU *) opaque);
37}
38
39void s390x_cpu_timer(void *opaque)
40{
41 cpu_inject_cpu_timer((S390CPU *) opaque);
42}
43#endif
44
45#ifndef CONFIG_USER_ONLY
46
47hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
48{
49 S390CPU *cpu = S390_CPU(cs);
50 CPUS390XState *env = &cpu->env;
51 target_ulong raddr;
52 int prot;
53 uint64_t asc = env->psw.mask & PSW_MASK_ASC;
54
55
56 if (!(env->psw.mask & PSW_MASK_64)) {
57 vaddr &= 0x7fffffff;
58 }
59
60 if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
61 return -1;
62 }
63 return raddr;
64}
65
66hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
67{
68 hwaddr phys_addr;
69 target_ulong page;
70
71 page = vaddr & TARGET_PAGE_MASK;
72 phys_addr = cpu_get_phys_page_debug(cs, page);
73 phys_addr += (vaddr & ~TARGET_PAGE_MASK);
74
75 return phys_addr;
76}
77
78static inline bool is_special_wait_psw(uint64_t psw_addr)
79{
80
81 return psw_addr == 0xfffUL;
82}
83
84void s390_handle_wait(S390CPU *cpu)
85{
86 CPUState *cs = CPU(cpu);
87
88 if (s390_cpu_halt(cpu) == 0) {
89#ifndef CONFIG_USER_ONLY
90 if (is_special_wait_psw(cpu->env.psw.addr)) {
91 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
92 } else {
93 cpu->env.crash_reason = S390_CRASH_REASON_DISABLED_WAIT;
94 qemu_system_guest_panicked(cpu_get_crash_info(cs));
95 }
96#endif
97 }
98}
99
100void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
101{
102 uint64_t old_mask = env->psw.mask;
103
104 env->psw.addr = addr;
105 env->psw.mask = mask;
106
107
108 if (!tcg_enabled()) {
109 return;
110 }
111 env->cc_op = (mask >> 44) & 3;
112
113 if ((old_mask ^ mask) & PSW_MASK_PER) {
114 s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env)));
115 }
116
117 if (mask & PSW_MASK_WAIT) {
118 s390_handle_wait(s390_env_get_cpu(env));
119 }
120}
121
122uint64_t get_psw_mask(CPUS390XState *env)
123{
124 uint64_t r = env->psw.mask;
125
126 if (tcg_enabled()) {
127 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
128 env->cc_vr);
129
130 r &= ~PSW_MASK_CC;
131 assert(!(env->cc_op & ~3));
132 r |= (uint64_t)env->cc_op << 44;
133 }
134
135 return r;
136}
137
138LowCore *cpu_map_lowcore(CPUS390XState *env)
139{
140 S390CPU *cpu = s390_env_get_cpu(env);
141 LowCore *lowcore;
142 hwaddr len = sizeof(LowCore);
143
144 lowcore = cpu_physical_memory_map(env->psa, &len, 1);
145
146 if (len < sizeof(LowCore)) {
147 cpu_abort(CPU(cpu), "Could not map lowcore\n");
148 }
149
150 return lowcore;
151}
152
153void cpu_unmap_lowcore(LowCore *lowcore)
154{
155 cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
156}
157
158void do_restart_interrupt(CPUS390XState *env)
159{
160 uint64_t mask, addr;
161 LowCore *lowcore;
162
163 lowcore = cpu_map_lowcore(env);
164
165 lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
166 lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
167 mask = be64_to_cpu(lowcore->restart_new_psw.mask);
168 addr = be64_to_cpu(lowcore->restart_new_psw.addr);
169
170 cpu_unmap_lowcore(lowcore);
171 env->pending_int &= ~INTERRUPT_RESTART;
172
173 load_psw(env, mask, addr);
174}
175
176void s390_cpu_recompute_watchpoints(CPUState *cs)
177{
178 const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
179 S390CPU *cpu = S390_CPU(cs);
180 CPUS390XState *env = &cpu->env;
181
182
183
184 cpu_watchpoint_remove_all(cs, BP_CPU);
185
186
187 if (!(env->psw.mask & PSW_MASK_PER)) {
188 return;
189 }
190
191
192 if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) {
193 return;
194 }
195
196 if (env->cregs[10] == 0 && env->cregs[11] == -1LL) {
197
198
199 cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL);
200 cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL);
201 } else if (env->cregs[10] > env->cregs[11]) {
202
203 cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10],
204 wp_flags, NULL);
205 cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL);
206
207 } else {
208
209 cpu_watchpoint_insert(cs, env->cregs[10],
210 env->cregs[11] - env->cregs[10] + 1,
211 wp_flags, NULL);
212 }
213}
214
215struct sigp_save_area {
216 uint64_t fprs[16];
217 uint64_t grs[16];
218 PSW psw;
219 uint8_t pad_0x0110[0x0118 - 0x0110];
220 uint32_t prefix;
221 uint32_t fpc;
222 uint8_t pad_0x0120[0x0124 - 0x0120];
223 uint32_t todpr;
224 uint64_t cputm;
225 uint64_t ckc;
226 uint8_t pad_0x0138[0x0140 - 0x0138];
227 uint32_t ars[16];
228 uint64_t crs[16];
229};
230QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area) != 512);
231
232int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
233{
234 static const uint8_t ar_id = 1;
235 struct sigp_save_area *sa;
236 hwaddr len = sizeof(*sa);
237 int i;
238
239 sa = cpu_physical_memory_map(addr, &len, 1);
240 if (!sa) {
241 return -EFAULT;
242 }
243 if (len != sizeof(*sa)) {
244 cpu_physical_memory_unmap(sa, len, 1, 0);
245 return -EFAULT;
246 }
247
248 if (store_arch) {
249 cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1);
250 }
251 for (i = 0; i < 16; ++i) {
252 sa->fprs[i] = cpu_to_be64(get_freg(&cpu->env, i)->ll);
253 }
254 for (i = 0; i < 16; ++i) {
255 sa->grs[i] = cpu_to_be64(cpu->env.regs[i]);
256 }
257 sa->psw.addr = cpu_to_be64(cpu->env.psw.addr);
258 sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env));
259 sa->prefix = cpu_to_be32(cpu->env.psa);
260 sa->fpc = cpu_to_be32(cpu->env.fpc);
261 sa->todpr = cpu_to_be32(cpu->env.todpr);
262 sa->cputm = cpu_to_be64(cpu->env.cputm);
263 sa->ckc = cpu_to_be64(cpu->env.ckc >> 8);
264 for (i = 0; i < 16; ++i) {
265 sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]);
266 }
267 for (i = 0; i < 16; ++i) {
268 sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]);
269 }
270
271 cpu_physical_memory_unmap(sa, len, 1, len);
272
273 return 0;
274}
275
276#define ADTL_GS_OFFSET 1024
277#define ADTL_GS_MIN_SIZE 2048
278int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
279{
280 hwaddr save = len;
281 void *mem;
282
283 mem = cpu_physical_memory_map(addr, &save, 1);
284 if (!mem) {
285 return -EFAULT;
286 }
287 if (save != len) {
288 cpu_physical_memory_unmap(mem, len, 1, 0);
289 return -EFAULT;
290 }
291
292
293 if (s390_has_feat(S390_FEAT_VECTOR)) {
294 memcpy(mem, &cpu->env.vregs, 512);
295 }
296 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
297 memcpy(mem + ADTL_GS_OFFSET, &cpu->env.gscb, 32);
298 }
299
300 cpu_physical_memory_unmap(mem, len, 1, len);
301
302 return 0;
303}
304#endif
305
306void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
307 int flags)
308{
309 S390CPU *cpu = S390_CPU(cs);
310 CPUS390XState *env = &cpu->env;
311 int i;
312
313 if (env->cc_op > 3) {
314 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
315 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
316 } else {
317 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
318 env->psw.mask, env->psw.addr, env->cc_op);
319 }
320
321 for (i = 0; i < 16; i++) {
322 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
323 if ((i % 4) == 3) {
324 cpu_fprintf(f, "\n");
325 } else {
326 cpu_fprintf(f, " ");
327 }
328 }
329
330 for (i = 0; i < 16; i++) {
331 cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
332 if ((i % 4) == 3) {
333 cpu_fprintf(f, "\n");
334 } else {
335 cpu_fprintf(f, " ");
336 }
337 }
338
339 for (i = 0; i < 32; i++) {
340 cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
341 env->vregs[i][0].ll, env->vregs[i][1].ll);
342 cpu_fprintf(f, (i % 2) ? "\n" : " ");
343 }
344
345#ifndef CONFIG_USER_ONLY
346 for (i = 0; i < 16; i++) {
347 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
348 if ((i % 4) == 3) {
349 cpu_fprintf(f, "\n");
350 } else {
351 cpu_fprintf(f, " ");
352 }
353 }
354#endif
355
356#ifdef DEBUG_INLINE_BRANCHES
357 for (i = 0; i < CC_OP_MAX; i++) {
358 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
359 inline_branch_miss[i], inline_branch_hit[i]);
360 }
361#endif
362
363 cpu_fprintf(f, "\n");
364}
365
366const char *cc_name(enum cc_op cc_op)
367{
368 static const char * const cc_names[] = {
369 [CC_OP_CONST0] = "CC_OP_CONST0",
370 [CC_OP_CONST1] = "CC_OP_CONST1",
371 [CC_OP_CONST2] = "CC_OP_CONST2",
372 [CC_OP_CONST3] = "CC_OP_CONST3",
373 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
374 [CC_OP_STATIC] = "CC_OP_STATIC",
375 [CC_OP_NZ] = "CC_OP_NZ",
376 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
377 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
378 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
379 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
380 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
381 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
382 [CC_OP_ADD_64] = "CC_OP_ADD_64",
383 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
384 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
385 [CC_OP_SUB_64] = "CC_OP_SUB_64",
386 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
387 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
388 [CC_OP_ABS_64] = "CC_OP_ABS_64",
389 [CC_OP_NABS_64] = "CC_OP_NABS_64",
390 [CC_OP_ADD_32] = "CC_OP_ADD_32",
391 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
392 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
393 [CC_OP_SUB_32] = "CC_OP_SUB_32",
394 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
395 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
396 [CC_OP_ABS_32] = "CC_OP_ABS_32",
397 [CC_OP_NABS_32] = "CC_OP_NABS_32",
398 [CC_OP_COMP_32] = "CC_OP_COMP_32",
399 [CC_OP_COMP_64] = "CC_OP_COMP_64",
400 [CC_OP_TM_32] = "CC_OP_TM_32",
401 [CC_OP_TM_64] = "CC_OP_TM_64",
402 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
403 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
404 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
405 [CC_OP_ICM] = "CC_OP_ICM",
406 [CC_OP_SLA_32] = "CC_OP_SLA_32",
407 [CC_OP_SLA_64] = "CC_OP_SLA_64",
408 [CC_OP_FLOGR] = "CC_OP_FLOGR",
409 };
410
411 return cc_names[cc_op];
412}
413
