1
2
3
4
5
6
7
8
9
10
11
12#ifndef UNICORE32_CPU_H
13#define UNICORE32_CPU_H
14
15#define TARGET_LONG_BITS 32
16#define TARGET_PAGE_BITS 12
17
18#define TARGET_PHYS_ADDR_SPACE_BITS 32
19#define TARGET_VIRT_ADDR_SPACE_BITS 32
20
21#define CPUArchState struct CPUUniCore32State
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
25#include "exec/cpu-defs.h"
26
27#define NB_MMU_MODES 2
28
29typedef struct CPUUniCore32State {
30
31 uint32_t regs[32];
32
33
34
35 uint32_t uncached_asr;
36 uint32_t bsr;
37
38
39 uint32_t banked_bsr[6];
40 uint32_t banked_r29[6];
41 uint32_t banked_r30[6];
42
43
44 uint32_t CF;
45 uint32_t VF;
46 uint32_t NF;
47 uint32_t ZF;
48
49
50 struct {
51 uint32_t c0_cpuid;
52 uint32_t c0_cachetype;
53 uint32_t c1_sys;
54 uint32_t c2_base;
55 uint32_t c3_faultstatus;
56 uint32_t c4_faultaddr;
57 uint32_t c5_cacheop;
58 uint32_t c6_tlbop;
59 } cp0;
60
61
62 struct {
63 float64 regs[16];
64 uint32_t xregs[32];
65 float_status fp_status;
66 } ucf64;
67
68 CPU_COMMON
69
70
71 uint32_t features;
72
73} CPUUniCore32State;
74
75
76
77
78
79
80
81struct UniCore32CPU {
82
83 CPUState parent_obj;
84
85
86 CPUUniCore32State env;
87};
88
89static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
90{
91 return container_of(env, UniCore32CPU, env);
92}
93
94#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
95
96#define ENV_OFFSET offsetof(UniCore32CPU, env)
97
98void uc32_cpu_do_interrupt(CPUState *cpu);
99bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
100void uc32_cpu_dump_state(CPUState *cpu, FILE *f,
101 fprintf_function cpu_fprintf, int flags);
102hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
103
104#define ASR_M (0x1f)
105#define ASR_MODE_USER (0x10)
106#define ASR_MODE_INTR (0x12)
107#define ASR_MODE_PRIV (0x13)
108#define ASR_MODE_TRAP (0x17)
109#define ASR_MODE_EXTN (0x1b)
110#define ASR_MODE_SUSR (0x1f)
111#define ASR_I (1 << 7)
112#define ASR_V (1 << 28)
113#define ASR_C (1 << 29)
114#define ASR_Z (1 << 30)
115#define ASR_N (1 << 31)
116#define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
117#define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
118
119#define UC32_EXCP_PRIV (1)
120#define UC32_EXCP_ITRAP (2)
121#define UC32_EXCP_DTRAP (3)
122#define UC32_EXCP_INTR (4)
123
124
125target_ulong cpu_asr_read(CPUUniCore32State *env1);
126
127void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
128
129
130#define UC32_UCF64_FPSCR (31)
131#define UCF64_FPSCR_MASK (0x27ffffff)
132#define UCF64_FPSCR_RND_MASK (0x7)
133#define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
134#define UCF64_FPSCR_TRAPEN_MASK (0x7f)
135#define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
136#define UCF64_FPSCR_FLAG_MASK (0x3ff)
137#define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
138#define UCF64_FPSCR_FLAG_ZERO (1 << 17)
139#define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
140#define UCF64_FPSCR_FLAG_INVALID (1 << 19)
141#define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
142#define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
143#define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
144#define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
145#define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
146#define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
147#define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
148
149#define UC32_HWCAP_CMOV 4
150#define UC32_HWCAP_UCF64 8
151
152#define cpu_signal_handler uc32_cpu_signal_handler
153
154int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
155
156
157#define MMU_MODE0_SUFFIX _kernel
158#define MMU_MODE1_SUFFIX _user
159#define MMU_USER_IDX 1
160static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
161{
162 return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
163}
164
165#include "exec/cpu-all.h"
166
167#define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU
168#define UNICORE32_CPU_TYPE_NAME(model) model UNICORE32_CPU_TYPE_SUFFIX
169#define CPU_RESOLVING_TYPE TYPE_UNICORE32_CPU
170
171static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
172 target_ulong *cs_base, uint32_t *flags)
173{
174 *pc = env->regs[31];
175 *cs_base = 0;
176 *flags = 0;
177 if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
178 *flags |= (1 << 6);
179 }
180}
181
182int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
183 int mmu_idx);
184void uc32_translate_init(void);
185void switch_mode(CPUUniCore32State *, int);
186
187#endif
188