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25#ifndef I386_TCG_TARGET_H
26#define I386_TCG_TARGET_H
27
28#define TCG_TARGET_INSN_UNIT_SIZE 1
29#define TCG_TARGET_TLB_DISPLACEMENT_BITS 31
30
31#ifdef __x86_64__
32# define TCG_TARGET_REG_BITS 64
33# define TCG_TARGET_NB_REGS 32
34#else
35# define TCG_TARGET_REG_BITS 32
36# define TCG_TARGET_NB_REGS 24
37#endif
38
39typedef enum {
40 TCG_REG_EAX = 0,
41 TCG_REG_ECX,
42 TCG_REG_EDX,
43 TCG_REG_EBX,
44 TCG_REG_ESP,
45 TCG_REG_EBP,
46 TCG_REG_ESI,
47 TCG_REG_EDI,
48
49
50
51 TCG_REG_R8,
52 TCG_REG_R9,
53 TCG_REG_R10,
54 TCG_REG_R11,
55 TCG_REG_R12,
56 TCG_REG_R13,
57 TCG_REG_R14,
58 TCG_REG_R15,
59
60 TCG_REG_XMM0,
61 TCG_REG_XMM1,
62 TCG_REG_XMM2,
63 TCG_REG_XMM3,
64 TCG_REG_XMM4,
65 TCG_REG_XMM5,
66 TCG_REG_XMM6,
67 TCG_REG_XMM7,
68
69
70 TCG_REG_XMM8,
71 TCG_REG_XMM9,
72 TCG_REG_XMM10,
73 TCG_REG_XMM11,
74 TCG_REG_XMM12,
75 TCG_REG_XMM13,
76 TCG_REG_XMM14,
77 TCG_REG_XMM15,
78
79 TCG_REG_RAX = TCG_REG_EAX,
80 TCG_REG_RCX = TCG_REG_ECX,
81 TCG_REG_RDX = TCG_REG_EDX,
82 TCG_REG_RBX = TCG_REG_EBX,
83 TCG_REG_RSP = TCG_REG_ESP,
84 TCG_REG_RBP = TCG_REG_EBP,
85 TCG_REG_RSI = TCG_REG_ESI,
86 TCG_REG_RDI = TCG_REG_EDI,
87} TCGReg;
88
89
90#define TCG_REG_CALL_STACK TCG_REG_ESP
91#define TCG_TARGET_STACK_ALIGN 16
92#if defined(_WIN64)
93#define TCG_TARGET_CALL_STACK_OFFSET 32
94#else
95#define TCG_TARGET_CALL_STACK_OFFSET 0
96#endif
97
98extern bool have_bmi1;
99extern bool have_popcnt;
100extern bool have_avx1;
101extern bool have_avx2;
102
103
104#define TCG_TARGET_HAS_div2_i32 1
105#define TCG_TARGET_HAS_rot_i32 1
106#define TCG_TARGET_HAS_ext8s_i32 1
107#define TCG_TARGET_HAS_ext16s_i32 1
108#define TCG_TARGET_HAS_ext8u_i32 1
109#define TCG_TARGET_HAS_ext16u_i32 1
110#define TCG_TARGET_HAS_bswap16_i32 1
111#define TCG_TARGET_HAS_bswap32_i32 1
112#define TCG_TARGET_HAS_neg_i32 1
113#define TCG_TARGET_HAS_not_i32 1
114#define TCG_TARGET_HAS_andc_i32 have_bmi1
115#define TCG_TARGET_HAS_orc_i32 0
116#define TCG_TARGET_HAS_eqv_i32 0
117#define TCG_TARGET_HAS_nand_i32 0
118#define TCG_TARGET_HAS_nor_i32 0
119#define TCG_TARGET_HAS_clz_i32 1
120#define TCG_TARGET_HAS_ctz_i32 1
121#define TCG_TARGET_HAS_ctpop_i32 have_popcnt
122#define TCG_TARGET_HAS_deposit_i32 1
123#define TCG_TARGET_HAS_extract_i32 1
124#define TCG_TARGET_HAS_sextract_i32 1
125#define TCG_TARGET_HAS_movcond_i32 1
126#define TCG_TARGET_HAS_add2_i32 1
127#define TCG_TARGET_HAS_sub2_i32 1
128#define TCG_TARGET_HAS_mulu2_i32 1
129#define TCG_TARGET_HAS_muls2_i32 1
130#define TCG_TARGET_HAS_muluh_i32 0
131#define TCG_TARGET_HAS_mulsh_i32 0
132#define TCG_TARGET_HAS_goto_ptr 1
133#define TCG_TARGET_HAS_direct_jump 1
134
135#if TCG_TARGET_REG_BITS == 64
136#define TCG_TARGET_HAS_extrl_i64_i32 0
137#define TCG_TARGET_HAS_extrh_i64_i32 0
138#define TCG_TARGET_HAS_div2_i64 1
139#define TCG_TARGET_HAS_rot_i64 1
140#define TCG_TARGET_HAS_ext8s_i64 1
141#define TCG_TARGET_HAS_ext16s_i64 1
142#define TCG_TARGET_HAS_ext32s_i64 1
143#define TCG_TARGET_HAS_ext8u_i64 1
144#define TCG_TARGET_HAS_ext16u_i64 1
145#define TCG_TARGET_HAS_ext32u_i64 1
146#define TCG_TARGET_HAS_bswap16_i64 1
147#define TCG_TARGET_HAS_bswap32_i64 1
148#define TCG_TARGET_HAS_bswap64_i64 1
149#define TCG_TARGET_HAS_neg_i64 1
150#define TCG_TARGET_HAS_not_i64 1
151#define TCG_TARGET_HAS_andc_i64 have_bmi1
152#define TCG_TARGET_HAS_orc_i64 0
153#define TCG_TARGET_HAS_eqv_i64 0
154#define TCG_TARGET_HAS_nand_i64 0
155#define TCG_TARGET_HAS_nor_i64 0
156#define TCG_TARGET_HAS_clz_i64 1
157#define TCG_TARGET_HAS_ctz_i64 1
158#define TCG_TARGET_HAS_ctpop_i64 have_popcnt
159#define TCG_TARGET_HAS_deposit_i64 1
160#define TCG_TARGET_HAS_extract_i64 1
161#define TCG_TARGET_HAS_sextract_i64 0
162#define TCG_TARGET_HAS_movcond_i64 1
163#define TCG_TARGET_HAS_add2_i64 1
164#define TCG_TARGET_HAS_sub2_i64 1
165#define TCG_TARGET_HAS_mulu2_i64 1
166#define TCG_TARGET_HAS_muls2_i64 1
167#define TCG_TARGET_HAS_muluh_i64 0
168#define TCG_TARGET_HAS_mulsh_i64 0
169#endif
170
171
172#define TCG_TARGET_HAS_v64 have_avx1
173#define TCG_TARGET_HAS_v128 have_avx1
174#define TCG_TARGET_HAS_v256 have_avx2
175
176#define TCG_TARGET_HAS_andc_vec 1
177#define TCG_TARGET_HAS_orc_vec 0
178#define TCG_TARGET_HAS_not_vec 0
179#define TCG_TARGET_HAS_neg_vec 0
180#define TCG_TARGET_HAS_shi_vec 1
181#define TCG_TARGET_HAS_shs_vec 0
182#define TCG_TARGET_HAS_shv_vec 0
183#define TCG_TARGET_HAS_cmp_vec 1
184#define TCG_TARGET_HAS_mul_vec 1
185
186#define TCG_TARGET_deposit_i32_valid(ofs, len) \
187 (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
188 ((ofs) == 0 && (len) == 16))
189#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
190
191
192
193#define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8)
194#define TCG_TARGET_extract_i64_valid(ofs, len) \
195 (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
196
197#if TCG_TARGET_REG_BITS == 64
198# define TCG_AREG0 TCG_REG_R14
199#else
200# define TCG_AREG0 TCG_REG_EBP
201#endif
202
203static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
204{
205}
206
207static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
208 uintptr_t jmp_addr, uintptr_t addr)
209{
210
211 atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
212
213}
214
215
216
217
218
219
220
221
222#include "tcg-mo.h"
223
224#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
225
226#ifdef CONFIG_SOFTMMU
227#define TCG_TARGET_NEED_LDST_LABELS
228#endif
229#define TCG_TARGET_NEED_POOL_LABELS
230
231#endif
232