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25#include "hw/sysbus.h"
26#include "qemu/timer.h"
27#include "hw/ptimer.h"
28#include "qemu/log.h"
29#include "qapi/qmp/qerror.h"
30#include "qemu/main-loop.h"
31
32#include "hw/stream.h"
33
34#define D(x)
35
36#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
37#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
38#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
39
40#define XILINX_AXI_DMA(obj) \
41 OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
42
43#define XILINX_AXI_DMA_DATA_STREAM(obj) \
44 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
45 TYPE_XILINX_AXI_DMA_DATA_STREAM)
46
47#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
48 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
49 TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
50
51#define R_DMACR (0x00 / 4)
52#define R_DMASR (0x04 / 4)
53#define R_CURDESC (0x08 / 4)
54#define R_TAILDESC (0x10 / 4)
55#define R_MAX (0x30 / 4)
56
57#define CONTROL_PAYLOAD_WORDS 5
58#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
59
60typedef struct XilinxAXIDMA XilinxAXIDMA;
61typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
62
63enum {
64 DMACR_RUNSTOP = 1,
65 DMACR_TAILPTR_MODE = 2,
66 DMACR_RESET = 4
67};
68
69enum {
70 DMASR_HALTED = 1,
71 DMASR_IDLE = 2,
72 DMASR_IOC_IRQ = 1 << 12,
73 DMASR_DLY_IRQ = 1 << 13,
74
75 DMASR_IRQ_MASK = 7 << 12
76};
77
78struct SDesc {
79 uint64_t nxtdesc;
80 uint64_t buffer_address;
81 uint64_t reserved;
82 uint32_t control;
83 uint32_t status;
84 uint8_t app[CONTROL_PAYLOAD_SIZE];
85};
86
87enum {
88 SDESC_CTRL_EOF = (1 << 26),
89 SDESC_CTRL_SOF = (1 << 27),
90
91 SDESC_CTRL_LEN_MASK = (1 << 23) - 1
92};
93
94enum {
95 SDESC_STATUS_EOF = (1 << 26),
96 SDESC_STATUS_SOF_BIT = 27,
97 SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
98 SDESC_STATUS_COMPLETE = (1 << 31)
99};
100
101struct Stream {
102 QEMUBH *bh;
103 ptimer_state *ptimer;
104 qemu_irq irq;
105
106 int nr;
107
108 struct SDesc desc;
109 int pos;
110 unsigned int complete_cnt;
111 uint32_t regs[R_MAX];
112 uint8_t app[20];
113};
114
115struct XilinxAXIDMAStreamSlave {
116 Object parent;
117
118 struct XilinxAXIDMA *dma;
119};
120
121struct XilinxAXIDMA {
122 SysBusDevice busdev;
123 MemoryRegion iomem;
124 uint32_t freqhz;
125 StreamSlave *tx_data_dev;
126 StreamSlave *tx_control_dev;
127 XilinxAXIDMAStreamSlave rx_data_dev;
128 XilinxAXIDMAStreamSlave rx_control_dev;
129
130 struct Stream streams[2];
131
132 StreamCanPushNotifyFn notify;
133 void *notify_opaque;
134};
135
136
137
138
139
140static inline int stream_desc_sof(struct SDesc *d)
141{
142 return d->control & SDESC_CTRL_SOF;
143}
144
145static inline int stream_desc_eof(struct SDesc *d)
146{
147 return d->control & SDESC_CTRL_EOF;
148}
149
150static inline int stream_resetting(struct Stream *s)
151{
152 return !!(s->regs[R_DMACR] & DMACR_RESET);
153}
154
155static inline int stream_running(struct Stream *s)
156{
157 return s->regs[R_DMACR] & DMACR_RUNSTOP;
158}
159
160static inline int stream_idle(struct Stream *s)
161{
162 return !!(s->regs[R_DMASR] & DMASR_IDLE);
163}
164
165static void stream_reset(struct Stream *s)
166{
167 s->regs[R_DMASR] = DMASR_HALTED;
168 s->regs[R_DMACR] = 1 << 16;
169}
170
171
172static inline int streamid_from_addr(hwaddr addr)
173{
174 int sid;
175
176 sid = addr / (0x30);
177 sid &= 1;
178 return sid;
179}
180
181#ifdef DEBUG_ENET
182static void stream_desc_show(struct SDesc *d)
183{
184 qemu_log("buffer_addr = " PRIx64 "\n", d->buffer_address);
185 qemu_log("nxtdesc = " PRIx64 "\n", d->nxtdesc);
186 qemu_log("control = %x\n", d->control);
187 qemu_log("status = %x\n", d->status);
188}
189#endif
190
191static void stream_desc_load(struct Stream *s, hwaddr addr)
192{
193 struct SDesc *d = &s->desc;
194
195 cpu_physical_memory_read(addr, d, sizeof *d);
196
197
198 d->buffer_address = le64_to_cpu(d->buffer_address);
199 d->nxtdesc = le64_to_cpu(d->nxtdesc);
200 d->control = le32_to_cpu(d->control);
201 d->status = le32_to_cpu(d->status);
202}
203
204static void stream_desc_store(struct Stream *s, hwaddr addr)
205{
206 struct SDesc *d = &s->desc;
207
208
209 d->buffer_address = cpu_to_le64(d->buffer_address);
210 d->nxtdesc = cpu_to_le64(d->nxtdesc);
211 d->control = cpu_to_le32(d->control);
212 d->status = cpu_to_le32(d->status);
213 cpu_physical_memory_write(addr, d, sizeof *d);
214}
215
216static void stream_update_irq(struct Stream *s)
217{
218 unsigned int pending, mask, irq;
219
220 pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
221 mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
222
223 irq = pending & mask;
224
225 qemu_set_irq(s->irq, !!irq);
226}
227
228static void stream_reload_complete_cnt(struct Stream *s)
229{
230 unsigned int comp_th;
231 comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
232 s->complete_cnt = comp_th;
233}
234
235static void timer_hit(void *opaque)
236{
237 struct Stream *s = opaque;
238
239 stream_reload_complete_cnt(s);
240 s->regs[R_DMASR] |= DMASR_DLY_IRQ;
241 stream_update_irq(s);
242}
243
244static void stream_complete(struct Stream *s)
245{
246 unsigned int comp_delay;
247
248
249 comp_delay = s->regs[R_DMACR] >> 24;
250 if (comp_delay) {
251 ptimer_stop(s->ptimer);
252 ptimer_set_count(s->ptimer, comp_delay);
253 ptimer_run(s->ptimer, 1);
254 }
255
256 s->complete_cnt--;
257 if (s->complete_cnt == 0) {
258
259 s->regs[R_DMASR] |= DMASR_IOC_IRQ;
260 stream_reload_complete_cnt(s);
261 }
262}
263
264static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
265 StreamSlave *tx_control_dev)
266{
267 uint32_t prev_d;
268 unsigned char txbuf[16 * 1024];
269 unsigned int txlen;
270
271 if (!stream_running(s) || stream_idle(s)) {
272 return;
273 }
274
275 while (1) {
276 stream_desc_load(s, s->regs[R_CURDESC]);
277
278 if (s->desc.status & SDESC_STATUS_COMPLETE) {
279 s->regs[R_DMASR] |= DMASR_HALTED;
280 break;
281 }
282
283 if (stream_desc_sof(&s->desc)) {
284 s->pos = 0;
285 stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app));
286 }
287
288 txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
289 if ((txlen + s->pos) > sizeof txbuf) {
290 hw_error("%s: too small internal txbuf! %d\n", __func__,
291 txlen + s->pos);
292 }
293
294 cpu_physical_memory_read(s->desc.buffer_address,
295 txbuf + s->pos, txlen);
296 s->pos += txlen;
297
298 if (stream_desc_eof(&s->desc)) {
299 stream_push(tx_data_dev, txbuf, s->pos);
300 s->pos = 0;
301 stream_complete(s);
302 }
303
304
305 s->desc.status = txlen | SDESC_STATUS_COMPLETE;
306 stream_desc_store(s, s->regs[R_CURDESC]);
307
308
309 prev_d = s->regs[R_CURDESC];
310 s->regs[R_CURDESC] = s->desc.nxtdesc;
311 if (prev_d == s->regs[R_TAILDESC]) {
312 s->regs[R_DMASR] |= DMASR_IDLE;
313 break;
314 }
315 }
316}
317
318static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
319 size_t len)
320{
321 uint32_t prev_d;
322 unsigned int rxlen;
323 size_t pos = 0;
324 int sof = 1;
325
326 if (!stream_running(s) || stream_idle(s)) {
327 return 0;
328 }
329
330 while (len) {
331 stream_desc_load(s, s->regs[R_CURDESC]);
332
333 if (s->desc.status & SDESC_STATUS_COMPLETE) {
334 s->regs[R_DMASR] |= DMASR_HALTED;
335 break;
336 }
337
338 rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
339 if (rxlen > len) {
340
341 rxlen = len;
342 }
343
344 cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
345 len -= rxlen;
346 pos += rxlen;
347
348
349 if (!len) {
350 stream_complete(s);
351 memcpy(s->desc.app, s->app, sizeof(s->desc.app));
352 s->desc.status |= SDESC_STATUS_EOF;
353 }
354
355 s->desc.status |= sof << SDESC_STATUS_SOF_BIT;
356 s->desc.status |= SDESC_STATUS_COMPLETE;
357 stream_desc_store(s, s->regs[R_CURDESC]);
358 sof = 0;
359
360
361 prev_d = s->regs[R_CURDESC];
362 s->regs[R_CURDESC] = s->desc.nxtdesc;
363 if (prev_d == s->regs[R_TAILDESC]) {
364 s->regs[R_DMASR] |= DMASR_IDLE;
365 break;
366 }
367 }
368
369 return pos;
370}
371
372static void xilinx_axidma_reset(DeviceState *dev)
373{
374 int i;
375 XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
376
377 for (i = 0; i < 2; i++) {
378 stream_reset(&s->streams[i]);
379 }
380}
381
382static size_t
383xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
384 size_t len)
385{
386 XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
387 struct Stream *s = &cs->dma->streams[1];
388
389 if (len != CONTROL_PAYLOAD_SIZE) {
390 hw_error("AXI DMA requires %d byte control stream payload\n",
391 (int)CONTROL_PAYLOAD_SIZE);
392 }
393
394 memcpy(s->app, buf, len);
395 return len;
396}
397
398static bool
399xilinx_axidma_data_stream_can_push(StreamSlave *obj,
400 StreamCanPushNotifyFn notify,
401 void *notify_opaque)
402{
403 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
404 struct Stream *s = &ds->dma->streams[1];
405
406 if (!stream_running(s) || stream_idle(s)) {
407 ds->dma->notify = notify;
408 ds->dma->notify_opaque = notify_opaque;
409 return false;
410 }
411
412 return true;
413}
414
415static size_t
416xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len)
417{
418 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
419 struct Stream *s = &ds->dma->streams[1];
420 size_t ret;
421
422 ret = stream_process_s2mem(s, buf, len);
423 stream_update_irq(s);
424 return ret;
425}
426
427static uint64_t axidma_read(void *opaque, hwaddr addr,
428 unsigned size)
429{
430 XilinxAXIDMA *d = opaque;
431 struct Stream *s;
432 uint32_t r = 0;
433 int sid;
434
435 sid = streamid_from_addr(addr);
436 s = &d->streams[sid];
437
438 addr = addr % 0x30;
439 addr >>= 2;
440 switch (addr) {
441 case R_DMACR:
442
443 s->regs[addr] &= ~DMACR_RESET;
444 r = s->regs[addr];
445 break;
446 case R_DMASR:
447 s->regs[addr] &= 0xffff;
448 s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
449 s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
450 r = s->regs[addr];
451 break;
452 default:
453 r = s->regs[addr];
454 D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
455 __func__, sid, addr * 4, r));
456 break;
457 }
458 return r;
459
460}
461
462static void axidma_write(void *opaque, hwaddr addr,
463 uint64_t value, unsigned size)
464{
465 XilinxAXIDMA *d = opaque;
466 struct Stream *s;
467 int sid;
468
469 sid = streamid_from_addr(addr);
470 s = &d->streams[sid];
471
472 addr = addr % 0x30;
473 addr >>= 2;
474 switch (addr) {
475 case R_DMACR:
476
477 value |= DMACR_TAILPTR_MODE;
478
479 value |= (s->regs[addr] & DMACR_RESET);
480 s->regs[addr] = value;
481
482 if (value & DMACR_RESET) {
483 stream_reset(s);
484 }
485
486 if ((value & 1) && !stream_resetting(s)) {
487
488 s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
489 }
490 stream_reload_complete_cnt(s);
491 break;
492
493 case R_DMASR:
494
495 value &= ~(value & DMASR_IRQ_MASK);
496 s->regs[addr] = value;
497 break;
498
499 case R_TAILDESC:
500 s->regs[addr] = value;
501 s->regs[R_DMASR] &= ~DMASR_IDLE;
502 if (!sid) {
503 stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
504 }
505 break;
506 default:
507 D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
508 __func__, sid, addr * 4, (unsigned)value));
509 s->regs[addr] = value;
510 break;
511 }
512 if (sid == 1 && d->notify) {
513 StreamCanPushNotifyFn notifytmp = d->notify;
514 d->notify = NULL;
515 notifytmp(d->notify_opaque);
516 }
517 stream_update_irq(s);
518}
519
520static const MemoryRegionOps axidma_ops = {
521 .read = axidma_read,
522 .write = axidma_write,
523 .endianness = DEVICE_NATIVE_ENDIAN,
524};
525
526static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
527{
528 XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
529 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
530 XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
531 &s->rx_control_dev);
532 Error *local_err = NULL;
533
534 object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
535 (Object **)&ds->dma,
536 object_property_allow_set_link,
537 OBJ_PROP_LINK_UNREF_ON_RELEASE,
538 &local_err);
539 object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
540 (Object **)&cs->dma,
541 object_property_allow_set_link,
542 OBJ_PROP_LINK_UNREF_ON_RELEASE,
543 &local_err);
544 if (local_err) {
545 goto xilinx_axidma_realize_fail;
546 }
547 object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_err);
548 object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_err);
549 if (local_err) {
550 goto xilinx_axidma_realize_fail;
551 }
552
553 int i;
554
555 for (i = 0; i < 2; i++) {
556 struct Stream *st = &s->streams[i];
557
558 st->nr = i;
559 st->bh = qemu_bh_new(timer_hit, st);
560 st->ptimer = ptimer_init(st->bh);
561 ptimer_set_freq(st->ptimer, s->freqhz);
562 }
563 return;
564
565xilinx_axidma_realize_fail:
566 if (!*errp) {
567 *errp = local_err;
568 }
569}
570
571static void xilinx_axidma_init(Object *obj)
572{
573 XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
574 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
575
576 object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
577 (Object **)&s->tx_data_dev,
578 qdev_prop_allow_set_link_before_realize,
579 OBJ_PROP_LINK_UNREF_ON_RELEASE,
580 &error_abort);
581 object_property_add_link(obj, "axistream-control-connected",
582 TYPE_STREAM_SLAVE,
583 (Object **)&s->tx_control_dev,
584 qdev_prop_allow_set_link_before_realize,
585 OBJ_PROP_LINK_UNREF_ON_RELEASE,
586 &error_abort);
587
588 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
589 TYPE_XILINX_AXI_DMA_DATA_STREAM);
590 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
591 TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
592 object_property_add_child(OBJECT(s), "axistream-connected-target",
593 (Object *)&s->rx_data_dev, &error_abort);
594 object_property_add_child(OBJECT(s), "axistream-control-connected-target",
595 (Object *)&s->rx_control_dev, &error_abort);
596
597 sysbus_init_irq(sbd, &s->streams[0].irq);
598 sysbus_init_irq(sbd, &s->streams[1].irq);
599
600 memory_region_init_io(&s->iomem, obj, &axidma_ops, s,
601 "xlnx.axi-dma", R_MAX * 4 * 2);
602 sysbus_init_mmio(sbd, &s->iomem);
603}
604
605static Property axidma_properties[] = {
606 DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
607 DEFINE_PROP_END_OF_LIST(),
608};
609
610static void axidma_class_init(ObjectClass *klass, void *data)
611{
612 DeviceClass *dc = DEVICE_CLASS(klass);
613
614 dc->realize = xilinx_axidma_realize,
615 dc->reset = xilinx_axidma_reset;
616 dc->props = axidma_properties;
617}
618
619static StreamSlaveClass xilinx_axidma_data_stream_class = {
620 .push = xilinx_axidma_data_stream_push,
621 .can_push = xilinx_axidma_data_stream_can_push,
622};
623
624static StreamSlaveClass xilinx_axidma_control_stream_class = {
625 .push = xilinx_axidma_control_stream_push,
626};
627
628static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
629{
630 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
631
632 ssc->push = ((StreamSlaveClass *)data)->push;
633 ssc->can_push = ((StreamSlaveClass *)data)->can_push;
634}
635
636static const TypeInfo axidma_info = {
637 .name = TYPE_XILINX_AXI_DMA,
638 .parent = TYPE_SYS_BUS_DEVICE,
639 .instance_size = sizeof(XilinxAXIDMA),
640 .class_init = axidma_class_init,
641 .instance_init = xilinx_axidma_init,
642};
643
644static const TypeInfo xilinx_axidma_data_stream_info = {
645 .name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
646 .parent = TYPE_OBJECT,
647 .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
648 .class_init = xilinx_axidma_stream_class_init,
649 .class_data = &xilinx_axidma_data_stream_class,
650 .interfaces = (InterfaceInfo[]) {
651 { TYPE_STREAM_SLAVE },
652 { }
653 }
654};
655
656static const TypeInfo xilinx_axidma_control_stream_info = {
657 .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
658 .parent = TYPE_OBJECT,
659 .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
660 .class_init = xilinx_axidma_stream_class_init,
661 .class_data = &xilinx_axidma_control_stream_class,
662 .interfaces = (InterfaceInfo[]) {
663 { TYPE_STREAM_SLAVE },
664 { }
665 }
666};
667
668static void xilinx_axidma_register_types(void)
669{
670 type_register_static(&axidma_info);
671 type_register_static(&xilinx_axidma_data_stream_info);
672 type_register_static(&xilinx_axidma_control_stream_info);
673}
674
675type_init(xilinx_axidma_register_types)
676
