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25#include "hw/hw.h"
26#include "hw/sysbus.h"
27#include "trace.h"
28#include "net/net.h"
29#include "qemu/error-report.h"
30
31#include <zlib.h>
32
33enum {
34 R_SETUP = 0,
35 R_MDIO,
36 R_STATE0,
37 R_COUNT0,
38 R_STATE1,
39 R_COUNT1,
40 R_TXCOUNT,
41 R_MAX
42};
43
44enum {
45 SETUP_PHY_RST = (1<<0),
46};
47
48enum {
49 MDIO_DO = (1<<0),
50 MDIO_DI = (1<<1),
51 MDIO_OE = (1<<2),
52 MDIO_CLK = (1<<3),
53};
54
55enum {
56 STATE_EMPTY = 0,
57 STATE_LOADED = 1,
58 STATE_PENDING = 2,
59};
60
61enum {
62 MDIO_OP_WRITE = 1,
63 MDIO_OP_READ = 2,
64};
65
66enum mdio_state {
67 MDIO_STATE_IDLE,
68 MDIO_STATE_READING,
69 MDIO_STATE_WRITING,
70};
71
72enum {
73 R_PHY_ID1 = 2,
74 R_PHY_ID2 = 3,
75 R_PHY_MAX = 32
76};
77
78#define MINIMAC2_MTU 1530
79#define MINIMAC2_BUFFER_SIZE 2048
80
81struct MilkymistMinimac2MdioState {
82 int last_clk;
83 int count;
84 uint32_t data;
85 uint16_t data_out;
86 int state;
87
88 uint8_t phy_addr;
89 uint8_t reg_addr;
90};
91typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
92
93#define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
94#define MILKYMIST_MINIMAC2(obj) \
95 OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
96
97struct MilkymistMinimac2State {
98 SysBusDevice parent_obj;
99
100 NICState *nic;
101 NICConf conf;
102 char *phy_model;
103 MemoryRegion buffers;
104 MemoryRegion regs_region;
105
106 qemu_irq rx_irq;
107 qemu_irq tx_irq;
108
109 uint32_t regs[R_MAX];
110
111 MilkymistMinimac2MdioState mdio;
112
113 uint16_t phy_regs[R_PHY_MAX];
114
115 uint8_t *rx0_buf;
116 uint8_t *rx1_buf;
117 uint8_t *tx_buf;
118};
119typedef struct MilkymistMinimac2State MilkymistMinimac2State;
120
121static const uint8_t preamble_sfd[] = {
122 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
123};
124
125static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
126 uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
127{
128 trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
129
130
131}
132
133static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
134 uint8_t phy_addr, uint8_t reg_addr)
135{
136 uint16_t r = s->phy_regs[reg_addr];
137
138 trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
139
140 return r;
141}
142
143static void minimac2_update_mdio(MilkymistMinimac2State *s)
144{
145 MilkymistMinimac2MdioState *m = &s->mdio;
146
147
148 if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
149
150 int bit = ((s->regs[R_MDIO] & MDIO_DO)
151 && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
152 m->data = (m->data << 1) | bit;
153
154
155 if (m->data == 0xffffffff) {
156 m->count = 32;
157 }
158
159 if (m->count == 16) {
160 uint8_t start = (m->data >> 14) & 0x3;
161 uint8_t op = (m->data >> 12) & 0x3;
162 uint8_t ta = (m->data) & 0x3;
163
164 if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
165 m->state = MDIO_STATE_WRITING;
166 } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
167 m->state = MDIO_STATE_READING;
168 } else {
169 m->state = MDIO_STATE_IDLE;
170 }
171
172 if (m->state != MDIO_STATE_IDLE) {
173 m->phy_addr = (m->data >> 7) & 0x1f;
174 m->reg_addr = (m->data >> 2) & 0x1f;
175 }
176
177 if (m->state == MDIO_STATE_READING) {
178 m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
179 m->reg_addr);
180 }
181 }
182
183 if (m->count < 16 && m->state == MDIO_STATE_READING) {
184 int bit = (m->data_out & 0x8000) ? 1 : 0;
185 m->data_out <<= 1;
186
187 if (bit) {
188 s->regs[R_MDIO] |= MDIO_DI;
189 } else {
190 s->regs[R_MDIO] &= ~MDIO_DI;
191 }
192 }
193
194 if (m->count == 0 && m->state) {
195 if (m->state == MDIO_STATE_WRITING) {
196 uint16_t data = m->data & 0xffff;
197 minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
198 }
199 m->state = MDIO_STATE_IDLE;
200 }
201 m->count--;
202 }
203
204 m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
205}
206
207static size_t assemble_frame(uint8_t *buf, size_t size,
208 const uint8_t *payload, size_t payload_size)
209{
210 uint32_t crc;
211
212 if (size < payload_size + 12) {
213 error_report("milkymist_minimac2: received too big ethernet frame");
214 return 0;
215 }
216
217
218 memcpy(buf, preamble_sfd, 8);
219
220
221 memcpy(buf + 8, payload, payload_size);
222
223
224 if (payload_size < 60) {
225 memset(buf + payload_size + 8, 0, 60 - payload_size);
226 payload_size = 60;
227 }
228
229
230 crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
231 memcpy(buf + payload_size + 8, &crc, 4);
232
233 return payload_size + 12;
234}
235
236static void minimac2_tx(MilkymistMinimac2State *s)
237{
238 uint32_t txcount = s->regs[R_TXCOUNT];
239 uint8_t *buf = s->tx_buf;
240
241 if (txcount < 64) {
242 error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
243 txcount, 64);
244 goto err;
245 }
246
247 if (txcount > MINIMAC2_MTU) {
248 error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
249 txcount, MINIMAC2_MTU);
250 goto err;
251 }
252
253 if (memcmp(buf, preamble_sfd, 8) != 0) {
254 error_report("milkymist_minimac2: frame doesn't contain the preamble "
255 "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
256 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
257 goto err;
258 }
259
260 trace_milkymist_minimac2_tx_frame(txcount - 12);
261
262
263 qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
264
265 s->regs[R_TXCOUNT] = 0;
266
267err:
268 trace_milkymist_minimac2_pulse_irq_tx();
269 qemu_irq_pulse(s->tx_irq);
270}
271
272static void update_rx_interrupt(MilkymistMinimac2State *s)
273{
274 if (s->regs[R_STATE0] == STATE_PENDING
275 || s->regs[R_STATE1] == STATE_PENDING) {
276 trace_milkymist_minimac2_raise_irq_rx();
277 qemu_irq_raise(s->rx_irq);
278 } else {
279 trace_milkymist_minimac2_lower_irq_rx();
280 qemu_irq_lower(s->rx_irq);
281 }
282}
283
284static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
285{
286 MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
287
288 uint32_t r_count;
289 uint32_t r_state;
290 uint8_t *rx_buf;
291
292 size_t frame_size;
293
294 trace_milkymist_minimac2_rx_frame(buf, size);
295
296
297 if (s->regs[R_STATE0] == STATE_LOADED) {
298 r_count = R_COUNT0;
299 r_state = R_STATE0;
300 rx_buf = s->rx0_buf;
301 } else if (s->regs[R_STATE1] == STATE_LOADED) {
302 r_count = R_COUNT1;
303 r_state = R_STATE1;
304 rx_buf = s->rx1_buf;
305 } else {
306 trace_milkymist_minimac2_drop_rx_frame(buf);
307 return size;
308 }
309
310
311 frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
312
313 if (frame_size == 0) {
314 return size;
315 }
316
317 trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
318
319
320 s->regs[r_count] = frame_size;
321 s->regs[r_state] = STATE_PENDING;
322
323 update_rx_interrupt(s);
324
325 return size;
326}
327
328static uint64_t
329minimac2_read(void *opaque, hwaddr addr, unsigned size)
330{
331 MilkymistMinimac2State *s = opaque;
332 uint32_t r = 0;
333
334 addr >>= 2;
335 switch (addr) {
336 case R_SETUP:
337 case R_MDIO:
338 case R_STATE0:
339 case R_COUNT0:
340 case R_STATE1:
341 case R_COUNT1:
342 case R_TXCOUNT:
343 r = s->regs[addr];
344 break;
345
346 default:
347 error_report("milkymist_minimac2: read access to unknown register 0x"
348 TARGET_FMT_plx, addr << 2);
349 break;
350 }
351
352 trace_milkymist_minimac2_memory_read(addr << 2, r);
353
354 return r;
355}
356
357static void
358minimac2_write(void *opaque, hwaddr addr, uint64_t value,
359 unsigned size)
360{
361 MilkymistMinimac2State *s = opaque;
362
363 trace_milkymist_minimac2_memory_write(addr, value);
364
365 addr >>= 2;
366 switch (addr) {
367 case R_MDIO:
368 {
369
370 int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
371 s->regs[R_MDIO] = value;
372 if (mdio_di) {
373 s->regs[R_MDIO] |= mdio_di;
374 } else {
375 s->regs[R_MDIO] &= ~mdio_di;
376 }
377
378 minimac2_update_mdio(s);
379 } break;
380 case R_TXCOUNT:
381 s->regs[addr] = value;
382 if (value > 0) {
383 minimac2_tx(s);
384 }
385 break;
386 case R_STATE0:
387 case R_STATE1:
388 s->regs[addr] = value;
389 update_rx_interrupt(s);
390 break;
391 case R_SETUP:
392 case R_COUNT0:
393 case R_COUNT1:
394 s->regs[addr] = value;
395 break;
396
397 default:
398 error_report("milkymist_minimac2: write access to unknown register 0x"
399 TARGET_FMT_plx, addr << 2);
400 break;
401 }
402}
403
404static const MemoryRegionOps minimac2_ops = {
405 .read = minimac2_read,
406 .write = minimac2_write,
407 .valid = {
408 .min_access_size = 4,
409 .max_access_size = 4,
410 },
411 .endianness = DEVICE_NATIVE_ENDIAN,
412};
413
414static int minimac2_can_rx(NetClientState *nc)
415{
416 MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
417
418 if (s->regs[R_STATE0] == STATE_LOADED) {
419 return 1;
420 }
421 if (s->regs[R_STATE1] == STATE_LOADED) {
422 return 1;
423 }
424
425 return 0;
426}
427
428static void minimac2_cleanup(NetClientState *nc)
429{
430 MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
431
432 s->nic = NULL;
433}
434
435static void milkymist_minimac2_reset(DeviceState *d)
436{
437 MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
438 int i;
439
440 for (i = 0; i < R_MAX; i++) {
441 s->regs[i] = 0;
442 }
443 for (i = 0; i < R_PHY_MAX; i++) {
444 s->phy_regs[i] = 0;
445 }
446
447
448 s->phy_regs[R_PHY_ID1] = 0x0022;
449 s->phy_regs[R_PHY_ID2] = 0x161a;
450}
451
452static NetClientInfo net_milkymist_minimac2_info = {
453 .type = NET_CLIENT_OPTIONS_KIND_NIC,
454 .size = sizeof(NICState),
455 .can_receive = minimac2_can_rx,
456 .receive = minimac2_rx,
457 .cleanup = minimac2_cleanup,
458};
459
460static int milkymist_minimac2_init(SysBusDevice *sbd)
461{
462 DeviceState *dev = DEVICE(sbd);
463 MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
464 size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
465
466 sysbus_init_irq(sbd, &s->rx_irq);
467 sysbus_init_irq(sbd, &s->tx_irq);
468
469 memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
470 "milkymist-minimac2", R_MAX * 4);
471 sysbus_init_mmio(sbd, &s->regs_region);
472
473
474 memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
475 buffers_size, &error_abort);
476 vmstate_register_ram_global(&s->buffers);
477 s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
478 s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
479 s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
480
481 sysbus_init_mmio(sbd, &s->buffers);
482
483 qemu_macaddr_default_if_unset(&s->conf.macaddr);
484 s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
485 object_get_typename(OBJECT(dev)), dev->id, s);
486 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
487
488 return 0;
489}
490
491static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
492 .name = "milkymist-minimac2-mdio",
493 .version_id = 1,
494 .minimum_version_id = 1,
495 .fields = (VMStateField[]) {
496 VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
497 VMSTATE_INT32(count, MilkymistMinimac2MdioState),
498 VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
499 VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
500 VMSTATE_INT32(state, MilkymistMinimac2MdioState),
501 VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
502 VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
503 VMSTATE_END_OF_LIST()
504 }
505};
506
507static const VMStateDescription vmstate_milkymist_minimac2 = {
508 .name = "milkymist-minimac2",
509 .version_id = 1,
510 .minimum_version_id = 1,
511 .fields = (VMStateField[]) {
512 VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
513 VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
514 VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
515 vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
516 VMSTATE_END_OF_LIST()
517 }
518};
519
520static Property milkymist_minimac2_properties[] = {
521 DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
522 DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
523 DEFINE_PROP_END_OF_LIST(),
524};
525
526static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
527{
528 DeviceClass *dc = DEVICE_CLASS(klass);
529 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
530
531 k->init = milkymist_minimac2_init;
532 dc->reset = milkymist_minimac2_reset;
533 dc->vmsd = &vmstate_milkymist_minimac2;
534 dc->props = milkymist_minimac2_properties;
535}
536
537static const TypeInfo milkymist_minimac2_info = {
538 .name = TYPE_MILKYMIST_MINIMAC2,
539 .parent = TYPE_SYS_BUS_DEVICE,
540 .instance_size = sizeof(MilkymistMinimac2State),
541 .class_init = milkymist_minimac2_class_init,
542};
543
544static void milkymist_minimac2_register_types(void)
545{
546 type_register_static(&milkymist_minimac2_info);
547}
548
549type_init(milkymist_minimac2_register_types)
550
