LXR qemu/hw/pci/msi.c

   1/*
   2 * msi.c
   3 *
   4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5 *                    VA Linux Systems Japan K.K.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "hw/pci/msi.h"
  22#include "qemu/range.h"
  23
  24/* Eventually those constants should go to Linux pci_regs.h */
  25#define PCI_MSI_PENDING_32      0x10
  26#define PCI_MSI_PENDING_64      0x14
  27
  28/* PCI_MSI_ADDRESS_LO */
  29#define PCI_MSI_ADDRESS_LO_MASK         (~0x3)
  30
  31/* If we get rid of cap allocator, we won't need those. */
  32#define PCI_MSI_32_SIZEOF       0x0a
  33#define PCI_MSI_64_SIZEOF       0x0e
  34#define PCI_MSI_32M_SIZEOF      0x14
  35#define PCI_MSI_64M_SIZEOF      0x18
  36
  37#define PCI_MSI_VECTORS_MAX     32
  38
  39/* Flag for interrupt controller to declare MSI/MSI-X support */
  40bool msi_supported;
  41
  42/* If we get rid of cap allocator, we won't need this. */
  43static inline uint8_t msi_cap_sizeof(uint16_t flags)
  44{
  45    switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
  46    case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
  47        return PCI_MSI_64M_SIZEOF;
  48    case PCI_MSI_FLAGS_64BIT:
  49        return PCI_MSI_64_SIZEOF;
  50    case PCI_MSI_FLAGS_MASKBIT:
  51        return PCI_MSI_32M_SIZEOF;
  52    case 0:
  53        return PCI_MSI_32_SIZEOF;
  54    default:
  55        abort();
  56        break;
  57    }
  58    return 0;
  59}
  60
  61//#define MSI_DEBUG
  62
  63#ifdef MSI_DEBUG
  64# define MSI_DPRINTF(fmt, ...)                                          \
  65    fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  66#else
  67# define MSI_DPRINTF(fmt, ...)  do { } while (0)
  68#endif
  69#define MSI_DEV_PRINTF(dev, fmt, ...)                                   \
  70    MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  71
  72static inline unsigned int msi_nr_vectors(uint16_t flags)
  73{
  74    return 1U <<
  75        ((flags & PCI_MSI_FLAGS_QSIZE) >> (ffs(PCI_MSI_FLAGS_QSIZE) - 1));
  76}
  77
  78static inline uint8_t msi_flags_off(const PCIDevice* dev)
  79{
  80    return dev->msi_cap + PCI_MSI_FLAGS;
  81}
  82
  83static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
  84{
  85    return dev->msi_cap + PCI_MSI_ADDRESS_LO;
  86}
  87
  88static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
  89{
  90    return dev->msi_cap + PCI_MSI_ADDRESS_HI;
  91}
  92
  93static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
  94{
  95    return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
  96}
  97
  98static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
  99{
 100    return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
 101}
 102
 103static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
 104{
 105    return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
 106}
 107
 108/*
 109 * Special API for POWER to configure the vectors through
 110 * a side channel. Should never be used by devices.
 111 */
 112void msi_set_message(PCIDevice *dev, MSIMessage msg)
 113{
 114    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 115    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 116
 117    if (msi64bit) {
 118        pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
 119    } else {
 120        pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
 121    }
 122    pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
 123}
 124
 125MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector)
 126{
 127    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 128    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 129    unsigned int nr_vectors = msi_nr_vectors(flags);
 130    MSIMessage msg;
 131
 132    assert(vector < nr_vectors);
 133
 134    if (msi64bit) {
 135        msg.address = pci_get_quad(dev->config + msi_address_lo_off(dev));
 136    } else {
 137        msg.address = pci_get_long(dev->config + msi_address_lo_off(dev));
 138    }
 139
 140    /* upper bit 31:16 is zero */
 141    msg.data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
 142    if (nr_vectors > 1) {
 143        msg.data &= ~(nr_vectors - 1);
 144        msg.data |= vector;
 145    }
 146
 147    return msg;
 148}
 149
 150bool msi_enabled(const PCIDevice *dev)
 151{
 152    return msi_present(dev) &&
 153        (pci_get_word(dev->config + msi_flags_off(dev)) &
 154         PCI_MSI_FLAGS_ENABLE);
 155}
 156
 157int msi_init(struct PCIDevice *dev, uint8_t offset,
 158             unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
 159{
 160    unsigned int vectors_order;
 161    uint16_t flags;
 162    uint8_t cap_size;
 163    int config_offset;
 164
 165    if (!msi_supported) {
 166        return -ENOTSUP;
 167    }
 168
 169    MSI_DEV_PRINTF(dev,
 170                   "init offset: 0x%"PRIx8" vector: %"PRId8
 171                   " 64bit %d mask %d\n",
 172                   offset, nr_vectors, msi64bit, msi_per_vector_mask);
 173
 174    assert(!(nr_vectors & (nr_vectors - 1)));   /* power of 2 */
 175    assert(nr_vectors > 0);
 176    assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
 177    /* the nr of MSI vectors is up to 32 */
 178    vectors_order = ffs(nr_vectors) - 1;
 179
 180    flags = vectors_order << (ffs(PCI_MSI_FLAGS_QMASK) - 1);
 181    if (msi64bit) {
 182        flags |= PCI_MSI_FLAGS_64BIT;
 183    }
 184    if (msi_per_vector_mask) {
 185        flags |= PCI_MSI_FLAGS_MASKBIT;
 186    }
 187
 188    cap_size = msi_cap_sizeof(flags);
 189    config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
 190    if (config_offset < 0) {
 191        return config_offset;
 192    }
 193
 194    dev->msi_cap = config_offset;
 195    dev->cap_present |= QEMU_PCI_CAP_MSI;
 196
 197    pci_set_word(dev->config + msi_flags_off(dev), flags);
 198    pci_set_word(dev->wmask + msi_flags_off(dev),
 199                 PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 200    pci_set_long(dev->wmask + msi_address_lo_off(dev),
 201                 PCI_MSI_ADDRESS_LO_MASK);
 202    if (msi64bit) {
 203        pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
 204    }
 205    pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
 206
 207    if (msi_per_vector_mask) {
 208        /* Make mask bits 0 to nr_vectors - 1 writable. */
 209        pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
 210                     0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
 211    }
 212    return config_offset;
 213}
 214
 215void msi_uninit(struct PCIDevice *dev)
 216{
 217    uint16_t flags;
 218    uint8_t cap_size;
 219
 220    if (!msi_present(dev)) {
 221        return;
 222    }
 223    flags = pci_get_word(dev->config + msi_flags_off(dev));
 224    cap_size = msi_cap_sizeof(flags);
 225    pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
 226    dev->cap_present &= ~QEMU_PCI_CAP_MSI;
 227
 228    MSI_DEV_PRINTF(dev, "uninit\n");
 229}
 230
 231void msi_reset(PCIDevice *dev)
 232{
 233    uint16_t flags;
 234    bool msi64bit;
 235
 236    if (!msi_present(dev)) {
 237        return;
 238    }
 239
 240    flags = pci_get_word(dev->config + msi_flags_off(dev));
 241    flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 242    msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 243
 244    pci_set_word(dev->config + msi_flags_off(dev), flags);
 245    pci_set_long(dev->config + msi_address_lo_off(dev), 0);
 246    if (msi64bit) {
 247        pci_set_long(dev->config + msi_address_hi_off(dev), 0);
 248    }
 249    pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
 250    if (flags & PCI_MSI_FLAGS_MASKBIT) {
 251        pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
 252        pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
 253    }
 254    MSI_DEV_PRINTF(dev, "reset\n");
 255}
 256
 257static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
 258{
 259    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 260    uint32_t mask;
 261    assert(vector < PCI_MSI_VECTORS_MAX);
 262
 263    if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
 264        return false;
 265    }
 266
 267    mask = pci_get_long(dev->config +
 268                        msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
 269    return mask & (1U << vector);
 270}
 271
 272void msi_notify(PCIDevice *dev, unsigned int vector)
 273{
 274    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 275    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 276    unsigned int nr_vectors = msi_nr_vectors(flags);
 277    MSIMessage msg;
 278
 279    assert(vector < nr_vectors);
 280    if (msi_is_masked(dev, vector)) {
 281        assert(flags & PCI_MSI_FLAGS_MASKBIT);
 282        pci_long_test_and_set_mask(
 283            dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 284        MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
 285        return;
 286    }
 287
 288    msg = msi_get_message(dev, vector);
 289
 290    MSI_DEV_PRINTF(dev,
 291                   "notify vector 0x%x"
 292                   " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
 293                   vector, msg.address, msg.data);
 294    stl_le_phys(&dev->bus_master_as, msg.address, msg.data);
 295}
 296
 297/* Normally called by pci_default_write_config(). */
 298void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
 299{
 300    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 301    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 302    bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
 303    unsigned int nr_vectors;
 304    uint8_t log_num_vecs;
 305    uint8_t log_max_vecs;
 306    unsigned int vector;
 307    uint32_t pending;
 308
 309    if (!msi_present(dev) ||
 310        !ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
 311        return;
 312    }
 313
 314#ifdef MSI_DEBUG
 315    MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
 316                   addr, val, len);
 317    MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
 318                   flags,
 319                   pci_get_long(dev->config + msi_address_lo_off(dev)));
 320    if (msi64bit) {
 321        fprintf(stderr, " address-hi: 0x%"PRIx32,
 322                pci_get_long(dev->config + msi_address_hi_off(dev)));
 323    }
 324    fprintf(stderr, " data: 0x%"PRIx16,
 325            pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
 326    if (flags & PCI_MSI_FLAGS_MASKBIT) {
 327        fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
 328                pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
 329                pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
 330    }
 331    fprintf(stderr, "\n");
 332#endif
 333
 334    if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
 335        return;
 336    }
 337
 338    /*
 339     * Now MSI is enabled, clear INTx# interrupts.
 340     * the driver is prohibited from writing enable bit to mask
 341     * a service request. But the guest OS could do this.
 342     * So we just discard the interrupts as moderate fallback.
 343     *
 344     * 6.8.3.3. Enabling Operation
 345     *   While enabled for MSI or MSI-X operation, a function is prohibited
 346     *   from using its INTx# pin (if implemented) to request
 347     *   service (MSI, MSI-X, and INTx# are mutually exclusive).
 348     */
 349    pci_device_deassert_intx(dev);
 350
 351    /*
 352     * nr_vectors might be set bigger than capable. So clamp it.
 353     * This is not legal by spec, so we can do anything we like,
 354     * just don't crash the host
 355     */
 356    log_num_vecs =
 357        (flags & PCI_MSI_FLAGS_QSIZE) >> (ffs(PCI_MSI_FLAGS_QSIZE) - 1);
 358    log_max_vecs =
 359        (flags & PCI_MSI_FLAGS_QMASK) >> (ffs(PCI_MSI_FLAGS_QMASK) - 1);
 360    if (log_num_vecs > log_max_vecs) {
 361        flags &= ~PCI_MSI_FLAGS_QSIZE;
 362        flags |= log_max_vecs << (ffs(PCI_MSI_FLAGS_QSIZE) - 1);
 363        pci_set_word(dev->config + msi_flags_off(dev), flags);
 364    }
 365
 366    if (!msi_per_vector_mask) {
 367        /* if per vector masking isn't supported,
 368           there is no pending interrupt. */
 369        return;
 370    }
 371
 372    nr_vectors = msi_nr_vectors(flags);
 373
 374    /* This will discard pending interrupts, if any. */
 375    pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
 376    pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
 377    pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
 378
 379    /* deliver pending interrupts which are unmasked */
 380    for (vector = 0; vector < nr_vectors; ++vector) {
 381        if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
 382            continue;
 383        }
 384
 385        pci_long_test_and_clear_mask(
 386            dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 387        msi_notify(dev, vector);
 388    }
 389}
 390
 391unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
 392{
 393    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 394    return msi_nr_vectors(flags);
 395}
 396