LXR qemu/target-sparc/cpu.h

   1#ifndef CPU_SPARC_H
   2#define CPU_SPARC_H
   3
   4#include "config.h"
   5#include "qemu-common.h"
   6#include "qemu/bswap.h"
   7
   8#define ALIGNED_ONLY
   9
  10#if !defined(TARGET_SPARC64)
  11#define TARGET_LONG_BITS 32
  12#define TARGET_DPREGS 16
  13#define TARGET_PAGE_BITS 12 /* 4k */
  14#define TARGET_PHYS_ADDR_SPACE_BITS 36
  15#define TARGET_VIRT_ADDR_SPACE_BITS 32
  16#else
  17#define TARGET_LONG_BITS 64
  18#define TARGET_DPREGS 32
  19#define TARGET_PAGE_BITS 13 /* 8k */
  20#define TARGET_PHYS_ADDR_SPACE_BITS 41
  21# ifdef TARGET_ABI32
  22#  define TARGET_VIRT_ADDR_SPACE_BITS 32
  23# else
  24#  define TARGET_VIRT_ADDR_SPACE_BITS 44
  25# endif
  26#endif
  27
  28#define CPUArchState struct CPUSPARCState
  29
  30#include "exec/cpu-defs.h"
  31
  32#include "fpu/softfloat.h"
  33
  34#define TARGET_HAS_ICE 1
  35
  36#if !defined(TARGET_SPARC64)
  37#define ELF_MACHINE     EM_SPARC
  38#else
  39#define ELF_MACHINE     EM_SPARCV9
  40#endif
  41
  42/*#define EXCP_INTERRUPT 0x100*/
  43
  44/* trap definitions */
  45#ifndef TARGET_SPARC64
  46#define TT_TFAULT   0x01
  47#define TT_ILL_INSN 0x02
  48#define TT_PRIV_INSN 0x03
  49#define TT_NFPU_INSN 0x04
  50#define TT_WIN_OVF  0x05
  51#define TT_WIN_UNF  0x06
  52#define TT_UNALIGNED 0x07
  53#define TT_FP_EXCP  0x08
  54#define TT_DFAULT   0x09
  55#define TT_TOVF     0x0a
  56#define TT_EXTINT   0x10
  57#define TT_CODE_ACCESS 0x21
  58#define TT_UNIMP_FLUSH 0x25
  59#define TT_DATA_ACCESS 0x29
  60#define TT_DIV_ZERO 0x2a
  61#define TT_NCP_INSN 0x24
  62#define TT_TRAP     0x80
  63#else
  64#define TT_POWER_ON_RESET 0x01
  65#define TT_TFAULT   0x08
  66#define TT_CODE_ACCESS 0x0a
  67#define TT_ILL_INSN 0x10
  68#define TT_UNIMP_FLUSH TT_ILL_INSN
  69#define TT_PRIV_INSN 0x11
  70#define TT_NFPU_INSN 0x20
  71#define TT_FP_EXCP  0x21
  72#define TT_TOVF     0x23
  73#define TT_CLRWIN   0x24
  74#define TT_DIV_ZERO 0x28
  75#define TT_DFAULT   0x30
  76#define TT_DATA_ACCESS 0x32
  77#define TT_UNALIGNED 0x34
  78#define TT_PRIV_ACT 0x37
  79#define TT_EXTINT   0x40
  80#define TT_IVEC     0x60
  81#define TT_TMISS    0x64
  82#define TT_DMISS    0x68
  83#define TT_DPROT    0x6c
  84#define TT_SPILL    0x80
  85#define TT_FILL     0xc0
  86#define TT_WOTHER   (1 << 5)
  87#define TT_TRAP     0x100
  88#endif
  89
  90#define PSR_NEG_SHIFT 23
  91#define PSR_NEG   (1 << PSR_NEG_SHIFT)
  92#define PSR_ZERO_SHIFT 22
  93#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  94#define PSR_OVF_SHIFT 21
  95#define PSR_OVF   (1 << PSR_OVF_SHIFT)
  96#define PSR_CARRY_SHIFT 20
  97#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  98#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  99#if !defined(TARGET_SPARC64)
 100#define PSR_EF    (1<<12)
 101#define PSR_PIL   0xf00
 102#define PSR_S     (1<<7)
 103#define PSR_PS    (1<<6)
 104#define PSR_ET    (1<<5)
 105#define PSR_CWP   0x1f
 106#endif
 107
 108#define CC_SRC (env->cc_src)
 109#define CC_SRC2 (env->cc_src2)
 110#define CC_DST (env->cc_dst)
 111#define CC_OP  (env->cc_op)
 112
 113enum {
 114    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 115    CC_OP_FLAGS,   /* all cc are back in status register */
 116    CC_OP_DIV,     /* modify N, Z and V, C = 0*/
 117    CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 118    CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 119    CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 120    CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 121    CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 122    CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 123    CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 124    CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 125    CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
 126    CC_OP_NB,
 127};
 128
 129/* Trap base register */
 130#define TBR_BASE_MASK 0xfffff000
 131
 132#if defined(TARGET_SPARC64)
 133#define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
 134#define PS_IG    (1<<11) /* v9, zero on UA2007 */
 135#define PS_MG    (1<<10) /* v9, zero on UA2007 */
 136#define PS_CLE   (1<<9) /* UA2007 */
 137#define PS_TLE   (1<<8) /* UA2007 */
 138#define PS_RMO   (1<<7)
 139#define PS_RED   (1<<5) /* v9, zero on UA2007 */
 140#define PS_PEF   (1<<4) /* enable fpu */
 141#define PS_AM    (1<<3) /* address mask */
 142#define PS_PRIV  (1<<2)
 143#define PS_IE    (1<<1)
 144#define PS_AG    (1<<0) /* v9, zero on UA2007 */
 145
 146#define FPRS_FEF (1<<2)
 147
 148#define HS_PRIV  (1<<2)
 149#endif
 150
 151/* Fcc */
 152#define FSR_RD1        (1ULL << 31)
 153#define FSR_RD0        (1ULL << 30)
 154#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 155#define FSR_RD_NEAREST 0
 156#define FSR_RD_ZERO    FSR_RD0
 157#define FSR_RD_POS     FSR_RD1
 158#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 159
 160#define FSR_NVM   (1ULL << 27)
 161#define FSR_OFM   (1ULL << 26)
 162#define FSR_UFM   (1ULL << 25)
 163#define FSR_DZM   (1ULL << 24)
 164#define FSR_NXM   (1ULL << 23)
 165#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 166
 167#define FSR_NVA   (1ULL << 9)
 168#define FSR_OFA   (1ULL << 8)
 169#define FSR_UFA   (1ULL << 7)
 170#define FSR_DZA   (1ULL << 6)
 171#define FSR_NXA   (1ULL << 5)
 172#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 173
 174#define FSR_NVC   (1ULL << 4)
 175#define FSR_OFC   (1ULL << 3)
 176#define FSR_UFC   (1ULL << 2)
 177#define FSR_DZC   (1ULL << 1)
 178#define FSR_NXC   (1ULL << 0)
 179#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 180
 181#define FSR_FTT2   (1ULL << 16)
 182#define FSR_FTT1   (1ULL << 15)
 183#define FSR_FTT0   (1ULL << 14)
 184//gcc warns about constant overflow for ~FSR_FTT_MASK
 185//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 186#ifdef TARGET_SPARC64
 187#define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 188#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 189#define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 190#define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 191#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 192#else
 193#define FSR_FTT_NMASK      0xfffe3fffULL
 194#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 195#define FSR_LDFSR_OLDMASK  0x000fc000ULL
 196#endif
 197#define FSR_LDFSR_MASK     0xcfc00fffULL
 198#define FSR_FTT_IEEE_EXCP (1ULL << 14)
 199#define FSR_FTT_UNIMPFPOP (3ULL << 14)
 200#define FSR_FTT_SEQ_ERROR (4ULL << 14)
 201#define FSR_FTT_INVAL_FPR (6ULL << 14)
 202
 203#define FSR_FCC1_SHIFT 11
 204#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 205#define FSR_FCC0_SHIFT 10
 206#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 207
 208/* MMU */
 209#define MMU_E     (1<<0)
 210#define MMU_NF    (1<<1)
 211
 212#define PTE_ENTRYTYPE_MASK 3
 213#define PTE_ACCESS_MASK    0x1c
 214#define PTE_ACCESS_SHIFT   2
 215#define PTE_PPN_SHIFT      7
 216#define PTE_ADDR_MASK      0xffffff00
 217
 218#define PG_ACCESSED_BIT 5
 219#define PG_MODIFIED_BIT 6
 220#define PG_CACHE_BIT    7
 221
 222#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 223#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 224#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 225
 226/* 3 <= NWINDOWS <= 32. */
 227#define MIN_NWINDOWS 3
 228#define MAX_NWINDOWS 32
 229
 230#if !defined(TARGET_SPARC64)
 231#define NB_MMU_MODES 2
 232#else
 233#define NB_MMU_MODES 6
 234typedef struct trap_state {
 235    uint64_t tpc;
 236    uint64_t tnpc;
 237    uint64_t tstate;
 238    uint32_t tt;
 239} trap_state;
 240#endif
 241
 242typedef struct sparc_def_t {
 243    const char *name;
 244    target_ulong iu_version;
 245    uint32_t fpu_version;
 246    uint32_t mmu_version;
 247    uint32_t mmu_bm;
 248    uint32_t mmu_ctpr_mask;
 249    uint32_t mmu_cxr_mask;
 250    uint32_t mmu_sfsr_mask;
 251    uint32_t mmu_trcr_mask;
 252    uint32_t mxcc_version;
 253    uint32_t features;
 254    uint32_t nwindows;
 255    uint32_t maxtl;
 256} sparc_def_t;
 257
 258#define CPU_FEATURE_FLOAT        (1 << 0)
 259#define CPU_FEATURE_FLOAT128     (1 << 1)
 260#define CPU_FEATURE_SWAP         (1 << 2)
 261#define CPU_FEATURE_MUL          (1 << 3)
 262#define CPU_FEATURE_DIV          (1 << 4)
 263#define CPU_FEATURE_FLUSH        (1 << 5)
 264#define CPU_FEATURE_FSQRT        (1 << 6)
 265#define CPU_FEATURE_FMUL         (1 << 7)
 266#define CPU_FEATURE_VIS1         (1 << 8)
 267#define CPU_FEATURE_VIS2         (1 << 9)
 268#define CPU_FEATURE_FSMULD       (1 << 10)
 269#define CPU_FEATURE_HYPV         (1 << 11)
 270#define CPU_FEATURE_CMT          (1 << 12)
 271#define CPU_FEATURE_GL           (1 << 13)
 272#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
 273#define CPU_FEATURE_ASR17        (1 << 15)
 274#define CPU_FEATURE_CACHE_CTRL   (1 << 16)
 275#define CPU_FEATURE_POWERDOWN    (1 << 17)
 276#define CPU_FEATURE_CASA         (1 << 18)
 277
 278#ifndef TARGET_SPARC64
 279#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 280                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 281                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 282                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 283#else
 284#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 285                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 286                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 287                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 288                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
 289                              CPU_FEATURE_CASA)
 290enum {
 291    mmu_us_12, // Ultrasparc < III (64 entry TLB)
 292    mmu_us_3,  // Ultrasparc III (512 entry TLB)
 293    mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 294    mmu_sun4v, // T1, T2
 295};
 296#endif
 297
 298#define TTE_VALID_BIT       (1ULL << 63)
 299#define TTE_NFO_BIT         (1ULL << 60)
 300#define TTE_USED_BIT        (1ULL << 41)
 301#define TTE_LOCKED_BIT      (1ULL <<  6)
 302#define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
 303#define TTE_PRIV_BIT        (1ULL <<  2)
 304#define TTE_W_OK_BIT        (1ULL <<  1)
 305#define TTE_GLOBAL_BIT      (1ULL <<  0)
 306
 307#define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 308#define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)
 309#define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
 310#define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 311#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
 312#define TTE_IS_PRIV(tte)    ((tte) & TTE_PRIV_BIT)
 313#define TTE_IS_W_OK(tte)    ((tte) & TTE_W_OK_BIT)
 314#define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
 315
 316#define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
 317#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
 318
 319#define TTE_PGSIZE(tte)     (((tte) >> 61) & 3ULL)
 320#define TTE_PA(tte)         ((tte) & 0x1ffffffe000ULL)
 321
 322#define SFSR_NF_BIT         (1ULL << 24)   /* JPS1 NoFault */
 323#define SFSR_TM_BIT         (1ULL << 15)   /* JPS1 TLB Miss */
 324#define SFSR_FT_VA_IMMU_BIT (1ULL << 13)   /* USIIi VA out of range (IMMU) */
 325#define SFSR_FT_VA_DMMU_BIT (1ULL << 12)   /* USIIi VA out of range (DMMU) */
 326#define SFSR_FT_NFO_BIT     (1ULL << 11)   /* NFO page access */
 327#define SFSR_FT_ILL_BIT     (1ULL << 10)   /* illegal LDA/STA ASI */
 328#define SFSR_FT_ATOMIC_BIT  (1ULL <<  9)   /* atomic op on noncacheable area */
 329#define SFSR_FT_NF_E_BIT    (1ULL <<  8)   /* NF access on side effect area */
 330#define SFSR_FT_PRIV_BIT    (1ULL <<  7)   /* privilege violation */
 331#define SFSR_PR_BIT         (1ULL <<  3)   /* privilege mode */
 332#define SFSR_WRITE_BIT      (1ULL <<  2)   /* write access mode */
 333#define SFSR_OW_BIT         (1ULL <<  1)   /* status overwritten */
 334#define SFSR_VALID_BIT      (1ULL <<  0)   /* status valid */
 335
 336#define SFSR_ASI_SHIFT      16             /* 23:16 ASI value */
 337#define SFSR_ASI_MASK       (0xffULL << SFSR_ASI_SHIFT)
 338#define SFSR_CT_PRIMARY     (0ULL <<  4)   /* 5:4 context type */
 339#define SFSR_CT_SECONDARY   (1ULL <<  4)
 340#define SFSR_CT_NUCLEUS     (2ULL <<  4)
 341#define SFSR_CT_NOTRANS     (3ULL <<  4)
 342#define SFSR_CT_MASK        (3ULL <<  4)
 343
 344/* Leon3 cache control */
 345
 346/* Cache control: emulate the behavior of cache control registers but without
 347   any effect on the emulated */
 348
 349#define CACHE_STATE_MASK 0x3
 350#define CACHE_DISABLED   0x0
 351#define CACHE_FROZEN     0x1
 352#define CACHE_ENABLED    0x3
 353
 354/* Cache Control register fields */
 355
 356#define CACHE_CTRL_IF (1 <<  4)  /* Instruction Cache Freeze on Interrupt */
 357#define CACHE_CTRL_DF (1 <<  5)  /* Data Cache Freeze on Interrupt */
 358#define CACHE_CTRL_DP (1 << 14)  /* Data cache flush pending */
 359#define CACHE_CTRL_IP (1 << 15)  /* Instruction cache flush pending */
 360#define CACHE_CTRL_IB (1 << 16)  /* Instruction burst fetch */
 361#define CACHE_CTRL_FI (1 << 21)  /* Flush Instruction cache (Write only) */
 362#define CACHE_CTRL_FD (1 << 22)  /* Flush Data cache (Write only) */
 363#define CACHE_CTRL_DS (1 << 23)  /* Data cache snoop enable */
 364
 365typedef struct SparcTLBEntry {
 366    uint64_t tag;
 367    uint64_t tte;
 368} SparcTLBEntry;
 369
 370struct CPUTimer
 371{
 372    const char *name;
 373    uint32_t    frequency;
 374    uint32_t    disabled;
 375    uint64_t    disabled_mask;
 376    int64_t     clock_offset;
 377    QEMUTimer  *qtimer;
 378};
 379
 380typedef struct CPUTimer CPUTimer;
 381
 382struct QEMUFile;
 383void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
 384void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
 385
 386typedef struct CPUSPARCState CPUSPARCState;
 387
 388struct CPUSPARCState {
 389    target_ulong gregs[8]; /* general registers */
 390    target_ulong *regwptr; /* pointer to current register window */
 391    target_ulong pc;       /* program counter */
 392    target_ulong npc;      /* next program counter */
 393    target_ulong y;        /* multiply/divide register */
 394
 395    /* emulator internal flags handling */
 396    target_ulong cc_src, cc_src2;
 397    target_ulong cc_dst;
 398    uint32_t cc_op;
 399
 400    target_ulong cond; /* conditional branch result (XXX: save it in a
 401                          temporary register when possible) */
 402
 403    uint32_t psr;      /* processor state register */
 404    target_ulong fsr;      /* FPU state register */
 405    CPU_DoubleU fpr[TARGET_DPREGS];  /* floating point registers */
 406    uint32_t cwp;      /* index of current register window (extracted
 407                          from PSR) */
 408#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 409    uint32_t wim;      /* window invalid mask */
 410#endif
 411    target_ulong tbr;  /* trap base register */
 412#if !defined(TARGET_SPARC64)
 413    int      psrs;     /* supervisor mode (extracted from PSR) */
 414    int      psrps;    /* previous supervisor mode */
 415    int      psret;    /* enable traps */
 416#endif
 417    uint32_t psrpil;   /* interrupt blocking level */
 418    uint32_t pil_in;   /* incoming interrupt level bitmap */
 419#if !defined(TARGET_SPARC64)
 420    int      psref;    /* enable fpu */
 421#endif
 422    int interrupt_index;
 423    /* NOTE: we allow 8 more registers to handle wrapping */
 424    target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 425
 426    CPU_COMMON
 427
 428    /* Fields from here on are preserved across CPU reset. */
 429    target_ulong version;
 430    uint32_t nwindows;
 431
 432    /* MMU regs */
 433#if defined(TARGET_SPARC64)
 434    uint64_t lsu;
 435#define DMMU_E 0x8
 436#define IMMU_E 0x4
 437    //typedef struct SparcMMU
 438    union {
 439        uint64_t immuregs[16];
 440        struct {
 441            uint64_t tsb_tag_target;
 442            uint64_t unused_mmu_primary_context;   // use DMMU
 443            uint64_t unused_mmu_secondary_context; // use DMMU
 444            uint64_t sfsr;
 445            uint64_t sfar;
 446            uint64_t tsb;
 447            uint64_t tag_access;
 448        } immu;
 449    };
 450    union {
 451        uint64_t dmmuregs[16];
 452        struct {
 453            uint64_t tsb_tag_target;
 454            uint64_t mmu_primary_context;
 455            uint64_t mmu_secondary_context;
 456            uint64_t sfsr;
 457            uint64_t sfar;
 458            uint64_t tsb;
 459            uint64_t tag_access;
 460        } dmmu;
 461    };
 462    SparcTLBEntry itlb[64];
 463    SparcTLBEntry dtlb[64];
 464    uint32_t mmu_version;
 465#else
 466    uint32_t mmuregs[32];
 467    uint64_t mxccdata[4];
 468    uint64_t mxccregs[8];
 469    uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
 470    uint64_t mmubpaction;
 471    uint64_t mmubpregs[4];
 472    uint64_t prom_addr;
 473#endif
 474    /* temporary float registers */
 475    float128 qt0, qt1;
 476    float_status fp_status;
 477#if defined(TARGET_SPARC64)
 478#define MAXTL_MAX 8
 479#define MAXTL_MASK (MAXTL_MAX - 1)
 480    trap_state ts[MAXTL_MAX];
 481    uint32_t xcc;               /* Extended integer condition codes */
 482    uint32_t asi;
 483    uint32_t pstate;
 484    uint32_t tl;
 485    uint32_t maxtl;
 486    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 487    uint64_t agregs[8]; /* alternate general registers */
 488    uint64_t bgregs[8]; /* backup for normal global registers */
 489    uint64_t igregs[8]; /* interrupt general registers */
 490    uint64_t mgregs[8]; /* mmu general registers */
 491    uint64_t fprs;
 492    uint64_t tick_cmpr, stick_cmpr;
 493    CPUTimer *tick, *stick;
 494#define TICK_NPT_MASK        0x8000000000000000ULL
 495#define TICK_INT_DIS         0x8000000000000000ULL
 496    uint64_t gsr;
 497    uint32_t gl; // UA2005
 498    /* UA 2005 hyperprivileged registers */
 499    uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 500    CPUTimer *hstick; // UA 2005
 501    /* Interrupt vector registers */
 502    uint64_t ivec_status;
 503    uint64_t ivec_data[3];
 504    uint32_t softint;
 505#define SOFTINT_TIMER   1
 506#define SOFTINT_STIMER  (1 << 16)
 507#define SOFTINT_INTRMASK (0xFFFE)
 508#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
 509#endif
 510    sparc_def_t *def;
 511
 512    void *irq_manager;
 513    void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
 514
 515    /* Leon3 cache control */
 516    uint32_t cache_control;
 517};
 518
 519#include "cpu-qom.h"
 520
 521#ifndef NO_CPU_IO_DEFS
 522/* cpu_init.c */
 523SPARCCPU *cpu_sparc_init(const char *cpu_model);
 524void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 525void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 526/* mmu_helper.c */
 527int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 528                               int mmu_idx);
 529target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 530void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
 531
 532#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 533int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 534                              uint8_t *buf, int len, bool is_write);
 535#endif
 536
 537
 538/* translate.c */
 539void gen_intermediate_code_init(CPUSPARCState *env);
 540
 541/* cpu-exec.c */
 542int cpu_sparc_exec(CPUSPARCState *s);
 543
 544/* win_helper.c */
 545target_ulong cpu_get_psr(CPUSPARCState *env1);
 546void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
 547#ifdef TARGET_SPARC64
 548target_ulong cpu_get_ccr(CPUSPARCState *env1);
 549void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
 550target_ulong cpu_get_cwp64(CPUSPARCState *env1);
 551void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
 552void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
 553#endif
 554int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
 555int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
 556void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 557
 558/* int_helper.c */
 559void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
 560
 561/* sun4m.c, sun4u.c */
 562void cpu_check_irqs(CPUSPARCState *env);
 563
 564/* leon3.c */
 565void leon3_irq_ack(void *irq_manager, int intno);
 566
 567#if defined (TARGET_SPARC64)
 568
 569static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
 570{
 571    return (x & mask) == (y & mask);
 572}
 573
 574#define MMU_CONTEXT_BITS 13
 575#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
 576
 577static inline int tlb_compare_context(const SparcTLBEntry *tlb,
 578                                      uint64_t context)
 579{
 580    return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
 581}
 582
 583#endif
 584#endif
 585
 586/* cpu-exec.c */
 587#if !defined(CONFIG_USER_ONLY)
 588void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 589                                 bool is_write, bool is_exec, int is_asi,
 590                                 unsigned size);
 591#if defined(TARGET_SPARC64)
 592hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 593                                           int mmu_idx);
 594#endif
 595#endif
 596int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 597
 598#ifndef NO_CPU_IO_DEFS
 599static inline CPUSPARCState *cpu_init(const char *cpu_model)
 600{
 601    SPARCCPU *cpu = cpu_sparc_init(cpu_model);
 602    if (cpu == NULL) {
 603        return NULL;
 604    }
 605    return &cpu->env;
 606}
 607#endif
 608
 609#define cpu_exec cpu_sparc_exec
 610#define cpu_gen_code cpu_sparc_gen_code
 611#define cpu_signal_handler cpu_sparc_signal_handler
 612#define cpu_list sparc_cpu_list
 613
 614#define CPU_SAVE_VERSION 7
 615
 616/* MMU modes definitions */
 617#if defined (TARGET_SPARC64)
 618#define MMU_USER_IDX   0
 619#define MMU_MODE0_SUFFIX _user
 620#define MMU_USER_SECONDARY_IDX   1
 621#define MMU_MODE1_SUFFIX _user_secondary
 622#define MMU_KERNEL_IDX 2
 623#define MMU_MODE2_SUFFIX _kernel
 624#define MMU_KERNEL_SECONDARY_IDX 3
 625#define MMU_MODE3_SUFFIX _kernel_secondary
 626#define MMU_NUCLEUS_IDX 4
 627#define MMU_MODE4_SUFFIX _nucleus
 628#define MMU_HYPV_IDX   5
 629#define MMU_MODE5_SUFFIX _hypv
 630#else
 631#define MMU_USER_IDX   0
 632#define MMU_MODE0_SUFFIX _user
 633#define MMU_KERNEL_IDX 1
 634#define MMU_MODE1_SUFFIX _kernel
 635#endif
 636
 637#if defined (TARGET_SPARC64)
 638static inline int cpu_has_hypervisor(CPUSPARCState *env1)
 639{
 640    return env1->def->features & CPU_FEATURE_HYPV;
 641}
 642
 643static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
 644{
 645    return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
 646}
 647
 648static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 649{
 650    return env1->pstate & PS_PRIV;
 651}
 652#endif
 653
 654static inline int cpu_mmu_index(CPUSPARCState *env1)
 655{
 656#if defined(CONFIG_USER_ONLY)
 657    return MMU_USER_IDX;
 658#elif !defined(TARGET_SPARC64)
 659    return env1->psrs;
 660#else
 661    if (env1->tl > 0) {
 662        return MMU_NUCLEUS_IDX;
 663    } else if (cpu_hypervisor_mode(env1)) {
 664        return MMU_HYPV_IDX;
 665    } else if (cpu_supervisor_mode(env1)) {
 666        return MMU_KERNEL_IDX;
 667    } else {
 668        return MMU_USER_IDX;
 669    }
 670#endif
 671}
 672
 673static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
 674{
 675#if !defined (TARGET_SPARC64)
 676    if (env1->psret != 0)
 677        return 1;
 678#else
 679    if (env1->pstate & PS_IE)
 680        return 1;
 681#endif
 682
 683    return 0;
 684}
 685
 686static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 687{
 688#if !defined(TARGET_SPARC64)
 689    /* level 15 is non-maskable on sparc v8 */
 690    return pil == 15 || pil > env1->psrpil;
 691#else
 692    return pil > env1->psrpil;
 693#endif
 694}
 695
 696#include "exec/cpu-all.h"
 697
 698#ifdef TARGET_SPARC64
 699/* sun4u.c */
 700void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
 701uint64_t cpu_tick_get_count(CPUTimer *timer);
 702void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
 703trap_state* cpu_tsptr(CPUSPARCState* env);
 704#endif
 705
 706#define TB_FLAG_FPU_ENABLED (1 << 4)
 707#define TB_FLAG_AM_ENABLED (1 << 5)
 708
 709static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
 710                                        target_ulong *cs_base, int *flags)
 711{
 712    *pc = env->pc;
 713    *cs_base = env->npc;
 714#ifdef TARGET_SPARC64
 715    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
 716    *flags = (env->pstate & PS_PRIV)               /* 2 */
 717        | ((env->lsu & (DMMU_E | IMMU_E)) >> 2)    /* 1, 0 */
 718        | ((env->tl & 0xff) << 8)
 719        | (env->dmmu.mmu_primary_context << 16);   /* 16... */
 720    if (env->pstate & PS_AM) {
 721        *flags |= TB_FLAG_AM_ENABLED;
 722    }
 723    if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
 724        && (env->fprs & FPRS_FEF)) {
 725        *flags |= TB_FLAG_FPU_ENABLED;
 726    }
 727#else
 728    // FPU enable . Supervisor
 729    *flags = env->psrs;
 730    if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
 731        *flags |= TB_FLAG_FPU_ENABLED;
 732    }
 733#endif
 734}
 735
 736static inline bool tb_fpu_enabled(int tb_flags)
 737{
 738#if defined(CONFIG_USER_ONLY)
 739    return true;
 740#else
 741    return tb_flags & TB_FLAG_FPU_ENABLED;
 742#endif
 743}
 744
 745static inline bool tb_am_enabled(int tb_flags)
 746{
 747#ifndef TARGET_SPARC64
 748    return false;
 749#else
 750    return tb_flags & TB_FLAG_AM_ENABLED;
 751#endif
 752}
 753
 754#include "exec/exec-all.h"
 755
 756#endif
 757