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26#include "hw/char/serial.h"
27#include "sysemu/char.h"
28#include "qemu/timer.h"
29#include "exec/address-spaces.h"
30#include "qemu/error-report.h"
31
32
33
34#define UART_LCR_DLAB 0x80
35
36#define UART_IER_MSI 0x08
37#define UART_IER_RLSI 0x04
38#define UART_IER_THRI 0x02
39#define UART_IER_RDI 0x01
40
41#define UART_IIR_NO_INT 0x01
42#define UART_IIR_ID 0x06
43
44#define UART_IIR_MSI 0x00
45#define UART_IIR_THRI 0x02
46#define UART_IIR_RDI 0x04
47#define UART_IIR_RLSI 0x06
48#define UART_IIR_CTI 0x0C
49
50#define UART_IIR_FENF 0x80
51#define UART_IIR_FE 0xC0
52
53
54
55
56#define UART_MCR_LOOP 0x10
57#define UART_MCR_OUT2 0x08
58#define UART_MCR_OUT1 0x04
59#define UART_MCR_RTS 0x02
60#define UART_MCR_DTR 0x01
61
62
63
64
65#define UART_MSR_DCD 0x80
66#define UART_MSR_RI 0x40
67#define UART_MSR_DSR 0x20
68#define UART_MSR_CTS 0x10
69#define UART_MSR_DDCD 0x08
70#define UART_MSR_TERI 0x04
71#define UART_MSR_DDSR 0x02
72#define UART_MSR_DCTS 0x01
73#define UART_MSR_ANY_DELTA 0x0F
74
75#define UART_LSR_TEMT 0x40
76#define UART_LSR_THRE 0x20
77#define UART_LSR_BI 0x10
78#define UART_LSR_FE 0x08
79#define UART_LSR_PE 0x04
80#define UART_LSR_OE 0x02
81#define UART_LSR_DR 0x01
82#define UART_LSR_INT_ANY 0x1E
83
84
85
86#define UART_FCR_ITL_1 0x00
87#define UART_FCR_ITL_2 0x40
88#define UART_FCR_ITL_3 0x80
89#define UART_FCR_ITL_4 0xC0
90
91#define UART_FCR_DMS 0x08
92#define UART_FCR_XFR 0x04
93#define UART_FCR_RFR 0x02
94#define UART_FCR_FE 0x01
95
96#define MAX_XMIT_RETRY 4
97
98#ifdef DEBUG_SERIAL
99#define DPRINTF(fmt, ...) \
100do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
101#else
102#define DPRINTF(fmt, ...) \
103do {} while (0)
104#endif
105
106static void serial_receive1(void *opaque, const uint8_t *buf, int size);
107
108static inline void recv_fifo_put(SerialState *s, uint8_t chr)
109{
110
111 if (!fifo8_is_full(&s->recv_fifo)) {
112 fifo8_push(&s->recv_fifo, chr);
113 } else {
114 s->lsr |= UART_LSR_OE;
115 }
116}
117
118static void serial_update_irq(SerialState *s)
119{
120 uint8_t tmp_iir = UART_IIR_NO_INT;
121
122 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
123 tmp_iir = UART_IIR_RLSI;
124 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
125
126
127
128 tmp_iir = UART_IIR_CTI;
129 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
130 (!(s->fcr & UART_FCR_FE) ||
131 s->recv_fifo.num >= s->recv_fifo_itl)) {
132 tmp_iir = UART_IIR_RDI;
133 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
134 tmp_iir = UART_IIR_THRI;
135 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
136 tmp_iir = UART_IIR_MSI;
137 }
138
139 s->iir = tmp_iir | (s->iir & 0xF0);
140
141 if (tmp_iir != UART_IIR_NO_INT) {
142 qemu_irq_raise(s->irq);
143 } else {
144 qemu_irq_lower(s->irq);
145 }
146}
147
148static void serial_update_parameters(SerialState *s)
149{
150 int speed, parity, data_bits, stop_bits, frame_size;
151 QEMUSerialSetParams ssp;
152
153 if (s->divider == 0)
154 return;
155
156
157 frame_size = 1;
158 if (s->lcr & 0x08) {
159
160 frame_size++;
161 if (s->lcr & 0x10)
162 parity = 'E';
163 else
164 parity = 'O';
165 } else {
166 parity = 'N';
167 }
168 if (s->lcr & 0x04)
169 stop_bits = 2;
170 else
171 stop_bits = 1;
172
173 data_bits = (s->lcr & 0x03) + 5;
174 frame_size += data_bits + stop_bits;
175 speed = s->baudbase / s->divider;
176 ssp.speed = speed;
177 ssp.parity = parity;
178 ssp.data_bits = data_bits;
179 ssp.stop_bits = stop_bits;
180 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
181 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
182
183 DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
184 speed, parity, data_bits, stop_bits);
185}
186
187static void serial_update_msl(SerialState *s)
188{
189 uint8_t omsr;
190 int flags;
191
192 timer_del(s->modem_status_poll);
193
194 if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
195 s->poll_msl = -1;
196 return;
197 }
198
199 omsr = s->msr;
200
201 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
202 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
203 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
204 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
205
206 if (s->msr != omsr) {
207
208 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
209
210 if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
211 s->msr &= ~UART_MSR_TERI;
212 serial_update_irq(s);
213 }
214
215
216
217
218 if (s->poll_msl)
219 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 100);
220}
221
222static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
223{
224 SerialState *s = opaque;
225
226 do {
227 if (s->tsr_retry <= 0) {
228 if (s->fcr & UART_FCR_FE) {
229 if (fifo8_is_empty(&s->xmit_fifo)) {
230 return FALSE;
231 }
232 s->tsr = fifo8_pop(&s->xmit_fifo);
233 if (!s->xmit_fifo.num) {
234 s->lsr |= UART_LSR_THRE;
235 }
236 } else if ((s->lsr & UART_LSR_THRE)) {
237 return FALSE;
238 } else {
239 s->tsr = s->thr;
240 s->lsr |= UART_LSR_THRE;
241 s->lsr &= ~UART_LSR_TEMT;
242 }
243 }
244
245 if (s->mcr & UART_MCR_LOOP) {
246
247 serial_receive1(s, &s->tsr, 1);
248 } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
249 if (s->tsr_retry >= 0 && s->tsr_retry < MAX_XMIT_RETRY &&
250 qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
251 serial_xmit, s) > 0) {
252 s->tsr_retry++;
253 return FALSE;
254 }
255 s->tsr_retry = 0;
256 } else {
257 s->tsr_retry = 0;
258 }
259
260
261 } while ((s->fcr & UART_FCR_FE) && !fifo8_is_empty(&s->xmit_fifo));
262
263 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
264
265 if (s->lsr & UART_LSR_THRE) {
266 s->lsr |= UART_LSR_TEMT;
267 s->thr_ipending = 1;
268 serial_update_irq(s);
269 }
270
271 return FALSE;
272}
273
274
275
276
277
278static void serial_write_fcr(SerialState *s, uint8_t val)
279{
280
281 s->fcr = val;
282
283 if (val & UART_FCR_FE) {
284 s->iir |= UART_IIR_FE;
285
286 switch (val & 0xC0) {
287 case UART_FCR_ITL_1:
288 s->recv_fifo_itl = 1;
289 break;
290 case UART_FCR_ITL_2:
291 s->recv_fifo_itl = 4;
292 break;
293 case UART_FCR_ITL_3:
294 s->recv_fifo_itl = 8;
295 break;
296 case UART_FCR_ITL_4:
297 s->recv_fifo_itl = 14;
298 break;
299 }
300 } else {
301 s->iir &= ~UART_IIR_FE;
302 }
303}
304
305static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
306 unsigned size)
307{
308 SerialState *s = opaque;
309
310 addr &= 7;
311 DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
312 switch(addr) {
313 default:
314 case 0:
315 if (s->lcr & UART_LCR_DLAB) {
316 s->divider = (s->divider & 0xff00) | val;
317 serial_update_parameters(s);
318 } else {
319 s->thr = (uint8_t) val;
320 if(s->fcr & UART_FCR_FE) {
321
322 if (fifo8_is_full(&s->xmit_fifo)) {
323 fifo8_pop(&s->xmit_fifo);
324 }
325 fifo8_push(&s->xmit_fifo, s->thr);
326 s->lsr &= ~UART_LSR_TEMT;
327 }
328 s->thr_ipending = 0;
329 s->lsr &= ~UART_LSR_THRE;
330 serial_update_irq(s);
331 if (s->tsr_retry <= 0) {
332 serial_xmit(NULL, G_IO_OUT, s);
333 }
334 }
335 break;
336 case 1:
337 if (s->lcr & UART_LCR_DLAB) {
338 s->divider = (s->divider & 0x00ff) | (val << 8);
339 serial_update_parameters(s);
340 } else {
341 s->ier = val & 0x0f;
342
343
344 if (s->poll_msl >= 0) {
345 if (s->ier & UART_IER_MSI) {
346 s->poll_msl = 1;
347 serial_update_msl(s);
348 } else {
349 timer_del(s->modem_status_poll);
350 s->poll_msl = 0;
351 }
352 }
353
354
355
356
357
358
359
360
361
362
363
364
365 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
366 s->thr_ipending = 1;
367 } else {
368 s->thr_ipending = 0;
369 }
370 serial_update_irq(s);
371 }
372 break;
373 case 2:
374
375 if ((val ^ s->fcr) & UART_FCR_FE) {
376 val |= UART_FCR_XFR | UART_FCR_RFR;
377 }
378
379
380
381 if (val & UART_FCR_RFR) {
382 timer_del(s->fifo_timeout_timer);
383 s->timeout_ipending = 0;
384 fifo8_reset(&s->recv_fifo);
385 }
386
387 if (val & UART_FCR_XFR) {
388 fifo8_reset(&s->xmit_fifo);
389 }
390
391 serial_write_fcr(s, val & 0xC9);
392 serial_update_irq(s);
393 break;
394 case 3:
395 {
396 int break_enable;
397 s->lcr = val;
398 serial_update_parameters(s);
399 break_enable = (val >> 6) & 1;
400 if (break_enable != s->last_break_enable) {
401 s->last_break_enable = break_enable;
402 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
403 &break_enable);
404 }
405 }
406 break;
407 case 4:
408 {
409 int flags;
410 int old_mcr = s->mcr;
411 s->mcr = val & 0x1f;
412 if (val & UART_MCR_LOOP)
413 break;
414
415 if (s->poll_msl >= 0 && old_mcr != s->mcr) {
416
417 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
418
419 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
420
421 if (val & UART_MCR_RTS)
422 flags |= CHR_TIOCM_RTS;
423 if (val & UART_MCR_DTR)
424 flags |= CHR_TIOCM_DTR;
425
426 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
427
428
429 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
430 }
431 }
432 break;
433 case 5:
434 break;
435 case 6:
436 break;
437 case 7:
438 s->scr = val;
439 break;
440 }
441}
442
443static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
444{
445 SerialState *s = opaque;
446 uint32_t ret;
447
448 addr &= 7;
449 switch(addr) {
450 default:
451 case 0:
452 if (s->lcr & UART_LCR_DLAB) {
453 ret = s->divider & 0xff;
454 } else {
455 if(s->fcr & UART_FCR_FE) {
456 ret = fifo8_is_empty(&s->recv_fifo) ?
457 0 : fifo8_pop(&s->recv_fifo);
458 if (s->recv_fifo.num == 0) {
459 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
460 } else {
461 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
462 }
463 s->timeout_ipending = 0;
464 } else {
465 ret = s->rbr;
466 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
467 }
468 serial_update_irq(s);
469 if (!(s->mcr & UART_MCR_LOOP)) {
470
471 qemu_chr_accept_input(s->chr);
472 }
473 }
474 break;
475 case 1:
476 if (s->lcr & UART_LCR_DLAB) {
477 ret = (s->divider >> 8) & 0xff;
478 } else {
479 ret = s->ier;
480 }
481 break;
482 case 2:
483 ret = s->iir;
484 if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
485 s->thr_ipending = 0;
486 serial_update_irq(s);
487 }
488 break;
489 case 3:
490 ret = s->lcr;
491 break;
492 case 4:
493 ret = s->mcr;
494 break;
495 case 5:
496 ret = s->lsr;
497
498 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
499 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
500 serial_update_irq(s);
501 }
502 break;
503 case 6:
504 if (s->mcr & UART_MCR_LOOP) {
505
506
507 ret = (s->mcr & 0x0c) << 4;
508 ret |= (s->mcr & 0x02) << 3;
509 ret |= (s->mcr & 0x01) << 5;
510 } else {
511 if (s->poll_msl >= 0)
512 serial_update_msl(s);
513 ret = s->msr;
514
515 if (s->msr & UART_MSR_ANY_DELTA) {
516 s->msr &= 0xF0;
517 serial_update_irq(s);
518 }
519 }
520 break;
521 case 7:
522 ret = s->scr;
523 break;
524 }
525 DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
526 return ret;
527}
528
529static int serial_can_receive(SerialState *s)
530{
531 if(s->fcr & UART_FCR_FE) {
532 if (s->recv_fifo.num < UART_FIFO_LENGTH) {
533
534
535
536
537
538
539
540 return (s->recv_fifo.num <= s->recv_fifo_itl) ?
541 s->recv_fifo_itl - s->recv_fifo.num : 1;
542 } else {
543 return 0;
544 }
545 } else {
546 return !(s->lsr & UART_LSR_DR);
547 }
548}
549
550static void serial_receive_break(SerialState *s)
551{
552 s->rbr = 0;
553
554 recv_fifo_put(s, '\0');
555 s->lsr |= UART_LSR_BI | UART_LSR_DR;
556 serial_update_irq(s);
557}
558
559
560static void fifo_timeout_int (void *opaque) {
561 SerialState *s = opaque;
562 if (s->recv_fifo.num) {
563 s->timeout_ipending = 1;
564 serial_update_irq(s);
565 }
566}
567
568static int serial_can_receive1(void *opaque)
569{
570 SerialState *s = opaque;
571 return serial_can_receive(s);
572}
573
574static void serial_receive1(void *opaque, const uint8_t *buf, int size)
575{
576 SerialState *s = opaque;
577
578 if (s->wakeup) {
579 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
580 }
581 if(s->fcr & UART_FCR_FE) {
582 int i;
583 for (i = 0; i < size; i++) {
584 recv_fifo_put(s, buf[i]);
585 }
586 s->lsr |= UART_LSR_DR;
587
588 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
589 } else {
590 if (s->lsr & UART_LSR_DR)
591 s->lsr |= UART_LSR_OE;
592 s->rbr = buf[0];
593 s->lsr |= UART_LSR_DR;
594 }
595 serial_update_irq(s);
596}
597
598static void serial_event(void *opaque, int event)
599{
600 SerialState *s = opaque;
601 DPRINTF("event %x\n", event);
602 if (event == CHR_EVENT_BREAK)
603 serial_receive_break(s);
604}
605
606static void serial_pre_save(void *opaque)
607{
608 SerialState *s = opaque;
609 s->fcr_vmstate = s->fcr;
610}
611
612static int serial_pre_load(void *opaque)
613{
614 SerialState *s = opaque;
615 s->thr_ipending = -1;
616 s->poll_msl = -1;
617 return 0;
618}
619
620static int serial_post_load(void *opaque, int version_id)
621{
622 SerialState *s = opaque;
623
624 if (version_id < 3) {
625 s->fcr_vmstate = 0;
626 }
627 if (s->thr_ipending == -1) {
628 s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
629 }
630 s->last_break_enable = (s->lcr >> 6) & 1;
631
632 serial_write_fcr(s, s->fcr_vmstate);
633 serial_update_parameters(s);
634 return 0;
635}
636
637static bool serial_thr_ipending_needed(void *opaque)
638{
639 SerialState *s = opaque;
640
641 if (s->ier & UART_IER_THRI) {
642 bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
643 return s->thr_ipending != expected_value;
644 } else {
645
646
647
648
649 return false;
650 }
651}
652
653const VMStateDescription vmstate_serial_thr_ipending = {
654 .name = "serial/thr_ipending",
655 .version_id = 1,
656 .minimum_version_id = 1,
657 .fields = (VMStateField[]) {
658 VMSTATE_INT32(thr_ipending, SerialState),
659 VMSTATE_END_OF_LIST()
660 }
661};
662
663static bool serial_tsr_needed(void *opaque)
664{
665 SerialState *s = (SerialState *)opaque;
666 return s->tsr_retry != 0;
667}
668
669const VMStateDescription vmstate_serial_tsr = {
670 .name = "serial/tsr",
671 .version_id = 1,
672 .minimum_version_id = 1,
673 .fields = (VMStateField[]) {
674 VMSTATE_INT32(tsr_retry, SerialState),
675 VMSTATE_UINT8(thr, SerialState),
676 VMSTATE_UINT8(tsr, SerialState),
677 VMSTATE_END_OF_LIST()
678 }
679};
680
681static bool serial_recv_fifo_needed(void *opaque)
682{
683 SerialState *s = (SerialState *)opaque;
684 return !fifo8_is_empty(&s->recv_fifo);
685
686}
687
688const VMStateDescription vmstate_serial_recv_fifo = {
689 .name = "serial/recv_fifo",
690 .version_id = 1,
691 .minimum_version_id = 1,
692 .fields = (VMStateField[]) {
693 VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
694 VMSTATE_END_OF_LIST()
695 }
696};
697
698static bool serial_xmit_fifo_needed(void *opaque)
699{
700 SerialState *s = (SerialState *)opaque;
701 return !fifo8_is_empty(&s->xmit_fifo);
702}
703
704const VMStateDescription vmstate_serial_xmit_fifo = {
705 .name = "serial/xmit_fifo",
706 .version_id = 1,
707 .minimum_version_id = 1,
708 .fields = (VMStateField[]) {
709 VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
710 VMSTATE_END_OF_LIST()
711 }
712};
713
714static bool serial_fifo_timeout_timer_needed(void *opaque)
715{
716 SerialState *s = (SerialState *)opaque;
717 return timer_pending(s->fifo_timeout_timer);
718}
719
720const VMStateDescription vmstate_serial_fifo_timeout_timer = {
721 .name = "serial/fifo_timeout_timer",
722 .version_id = 1,
723 .minimum_version_id = 1,
724 .fields = (VMStateField[]) {
725 VMSTATE_TIMER(fifo_timeout_timer, SerialState),
726 VMSTATE_END_OF_LIST()
727 }
728};
729
730static bool serial_timeout_ipending_needed(void *opaque)
731{
732 SerialState *s = (SerialState *)opaque;
733 return s->timeout_ipending != 0;
734}
735
736const VMStateDescription vmstate_serial_timeout_ipending = {
737 .name = "serial/timeout_ipending",
738 .version_id = 1,
739 .minimum_version_id = 1,
740 .fields = (VMStateField[]) {
741 VMSTATE_INT32(timeout_ipending, SerialState),
742 VMSTATE_END_OF_LIST()
743 }
744};
745
746static bool serial_poll_needed(void *opaque)
747{
748 SerialState *s = (SerialState *)opaque;
749 return s->poll_msl >= 0;
750}
751
752const VMStateDescription vmstate_serial_poll = {
753 .name = "serial/poll",
754 .version_id = 1,
755 .minimum_version_id = 1,
756 .fields = (VMStateField[]) {
757 VMSTATE_INT32(poll_msl, SerialState),
758 VMSTATE_TIMER(modem_status_poll, SerialState),
759 VMSTATE_END_OF_LIST()
760 }
761};
762
763const VMStateDescription vmstate_serial = {
764 .name = "serial",
765 .version_id = 3,
766 .minimum_version_id = 2,
767 .pre_save = serial_pre_save,
768 .pre_load = serial_pre_load,
769 .post_load = serial_post_load,
770 .fields = (VMStateField[]) {
771 VMSTATE_UINT16_V(divider, SerialState, 2),
772 VMSTATE_UINT8(rbr, SerialState),
773 VMSTATE_UINT8(ier, SerialState),
774 VMSTATE_UINT8(iir, SerialState),
775 VMSTATE_UINT8(lcr, SerialState),
776 VMSTATE_UINT8(mcr, SerialState),
777 VMSTATE_UINT8(lsr, SerialState),
778 VMSTATE_UINT8(msr, SerialState),
779 VMSTATE_UINT8(scr, SerialState),
780 VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
781 VMSTATE_END_OF_LIST()
782 },
783 .subsections = (VMStateSubsection[]) {
784 {
785 .vmsd = &vmstate_serial_thr_ipending,
786 .needed = &serial_thr_ipending_needed,
787 } , {
788 .vmsd = &vmstate_serial_tsr,
789 .needed = &serial_tsr_needed,
790 } , {
791 .vmsd = &vmstate_serial_recv_fifo,
792 .needed = &serial_recv_fifo_needed,
793 } , {
794 .vmsd = &vmstate_serial_xmit_fifo,
795 .needed = &serial_xmit_fifo_needed,
796 } , {
797 .vmsd = &vmstate_serial_fifo_timeout_timer,
798 .needed = &serial_fifo_timeout_timer_needed,
799 } , {
800 .vmsd = &vmstate_serial_timeout_ipending,
801 .needed = &serial_timeout_ipending_needed,
802 } , {
803 .vmsd = &vmstate_serial_poll,
804 .needed = &serial_poll_needed,
805 } , {
806
807 }
808 }
809};
810
811static void serial_reset(void *opaque)
812{
813 SerialState *s = opaque;
814
815 s->rbr = 0;
816 s->ier = 0;
817 s->iir = UART_IIR_NO_INT;
818 s->lcr = 0;
819 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
820 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
821
822 s->divider = 0x0C;
823 s->mcr = UART_MCR_OUT2;
824 s->scr = 0;
825 s->tsr_retry = 0;
826 s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
827 s->poll_msl = 0;
828
829 s->timeout_ipending = 0;
830 timer_del(s->fifo_timeout_timer);
831 timer_del(s->modem_status_poll);
832
833 fifo8_reset(&s->recv_fifo);
834 fifo8_reset(&s->xmit_fifo);
835
836 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
837
838 s->thr_ipending = 0;
839 s->last_break_enable = 0;
840 qemu_irq_lower(s->irq);
841
842 serial_update_msl(s);
843 s->msr &= ~UART_MSR_ANY_DELTA;
844}
845
846void serial_realize_core(SerialState *s, Error **errp)
847{
848 if (!s->chr) {
849 error_setg(errp, "Can't create serial device, empty char device");
850 return;
851 }
852
853 s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
854
855 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
856 qemu_register_reset(serial_reset, s);
857
858 qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
859 serial_event, s);
860 fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
861 fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
862 serial_reset(s);
863}
864
865void serial_exit_core(SerialState *s)
866{
867 qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL);
868 qemu_unregister_reset(serial_reset, s);
869}
870
871
872void serial_set_frequency(SerialState *s, uint32_t frequency)
873{
874 s->baudbase = frequency;
875 serial_update_parameters(s);
876}
877
878const MemoryRegionOps serial_io_ops = {
879 .read = serial_ioport_read,
880 .write = serial_ioport_write,
881 .impl = {
882 .min_access_size = 1,
883 .max_access_size = 1,
884 },
885 .endianness = DEVICE_LITTLE_ENDIAN,
886};
887
888SerialState *serial_init(int base, qemu_irq irq, int baudbase,
889 CharDriverState *chr, MemoryRegion *system_io)
890{
891 SerialState *s;
892 Error *err = NULL;
893
894 s = g_malloc0(sizeof(SerialState));
895
896 s->irq = irq;
897 s->baudbase = baudbase;
898 s->chr = chr;
899 serial_realize_core(s, &err);
900 if (err != NULL) {
901 error_report("%s", error_get_pretty(err));
902 error_free(err);
903 exit(1);
904 }
905
906 vmstate_register(NULL, base, &vmstate_serial, s);
907
908 memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
909 memory_region_add_subregion(system_io, base, &s->io);
910
911 return s;
912}
913
914
915static uint64_t serial_mm_read(void *opaque, hwaddr addr,
916 unsigned size)
917{
918 SerialState *s = opaque;
919 return serial_ioport_read(s, addr >> s->it_shift, 1);
920}
921
922static void serial_mm_write(void *opaque, hwaddr addr,
923 uint64_t value, unsigned size)
924{
925 SerialState *s = opaque;
926 value &= ~0u >> (32 - (size * 8));
927 serial_ioport_write(s, addr >> s->it_shift, value, 1);
928}
929
930static const MemoryRegionOps serial_mm_ops[3] = {
931 [DEVICE_NATIVE_ENDIAN] = {
932 .read = serial_mm_read,
933 .write = serial_mm_write,
934 .endianness = DEVICE_NATIVE_ENDIAN,
935 },
936 [DEVICE_LITTLE_ENDIAN] = {
937 .read = serial_mm_read,
938 .write = serial_mm_write,
939 .endianness = DEVICE_LITTLE_ENDIAN,
940 },
941 [DEVICE_BIG_ENDIAN] = {
942 .read = serial_mm_read,
943 .write = serial_mm_write,
944 .endianness = DEVICE_BIG_ENDIAN,
945 },
946};
947
948SerialState *serial_mm_init(MemoryRegion *address_space,
949 hwaddr base, int it_shift,
950 qemu_irq irq, int baudbase,
951 CharDriverState *chr, enum device_endian end)
952{
953 SerialState *s;
954 Error *err = NULL;
955
956 s = g_malloc0(sizeof(SerialState));
957
958 s->it_shift = it_shift;
959 s->irq = irq;
960 s->baudbase = baudbase;
961 s->chr = chr;
962
963 serial_realize_core(s, &err);
964 if (err != NULL) {
965 error_report("%s", error_get_pretty(err));
966 error_free(err);
967 exit(1);
968 }
969 vmstate_register(NULL, base, &vmstate_serial, s);
970
971 memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
972 "serial", 8 << it_shift);
973 memory_region_add_subregion(address_space, base, &s->io);
974 return s;
975}
976