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21#include <zlib.h>
22#include <stdint.h>
23
24#include "qemu-common.h"
25#include "qemu/timer.h"
26#include "qemu/queue.h"
27#include "qemu/atomic.h"
28#include "monitor/monitor.h"
29#include "sysemu/sysemu.h"
30#include "trace.h"
31
32#include "qxl.h"
33
34
35
36
37
38
39
40#undef SPICE_RING_PROD_ITEM
41#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
43 if (prod >= ARRAY_SIZE((r)->items)) { \
44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
46 ret = NULL; \
47 } else { \
48 ret = &(r)->items[prod].el; \
49 } \
50 }
51
52#undef SPICE_RING_CONS_ITEM
53#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
55 if (cons >= ARRAY_SIZE((r)->items)) { \
56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
58 ret = NULL; \
59 } else { \
60 ret = &(r)->items[cons].el; \
61 } \
62 }
63
64#undef ALIGN
65#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
66
67#define PIXEL_SIZE 0.2936875
68
69#define QXL_MODE(_x, _y, _b, _o) \
70 { .x_res = _x, \
71 .y_res = _y, \
72 .bits = _b, \
73 .stride = (_x) * (_b) / 8, \
74 .x_mili = PIXEL_SIZE * (_x), \
75 .y_mili = PIXEL_SIZE * (_y), \
76 .orientation = _o, \
77 }
78
79#define QXL_MODE_16_32(x_res, y_res, orientation) \
80 QXL_MODE(x_res, y_res, 16, orientation), \
81 QXL_MODE(x_res, y_res, 32, orientation)
82
83#define QXL_MODE_EX(x_res, y_res) \
84 QXL_MODE_16_32(x_res, y_res, 0), \
85 QXL_MODE_16_32(x_res, y_res, 1)
86
87static QXLMode qxl_modes[] = {
88 QXL_MODE_EX(640, 480),
89 QXL_MODE_EX(800, 480),
90 QXL_MODE_EX(800, 600),
91 QXL_MODE_EX(832, 624),
92 QXL_MODE_EX(960, 640),
93 QXL_MODE_EX(1024, 600),
94 QXL_MODE_EX(1024, 768),
95 QXL_MODE_EX(1152, 864),
96 QXL_MODE_EX(1152, 870),
97 QXL_MODE_EX(1280, 720),
98 QXL_MODE_EX(1280, 760),
99 QXL_MODE_EX(1280, 768),
100 QXL_MODE_EX(1280, 800),
101 QXL_MODE_EX(1280, 960),
102 QXL_MODE_EX(1280, 1024),
103 QXL_MODE_EX(1360, 768),
104 QXL_MODE_EX(1366, 768),
105 QXL_MODE_EX(1400, 1050),
106 QXL_MODE_EX(1440, 900),
107 QXL_MODE_EX(1600, 900),
108 QXL_MODE_EX(1600, 1200),
109 QXL_MODE_EX(1680, 1050),
110 QXL_MODE_EX(1920, 1080),
111
112 QXL_MODE_EX(1920, 1200),
113 QXL_MODE_EX(1920, 1440),
114 QXL_MODE_EX(2000, 2000),
115 QXL_MODE_EX(2048, 1536),
116 QXL_MODE_EX(2048, 2048),
117 QXL_MODE_EX(2560, 1440),
118 QXL_MODE_EX(2560, 1600),
119
120 QXL_MODE_EX(2560, 2048),
121 QXL_MODE_EX(2800, 2100),
122 QXL_MODE_EX(3200, 2400),
123 QXL_MODE_EX(3840, 2160),
124 QXL_MODE_EX(4096, 2160),
125 QXL_MODE_EX(7680, 4320),
126 QXL_MODE_EX(8192, 4320),
127};
128
129static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
130static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
131static void qxl_reset_memslots(PCIQXLDevice *d);
132static void qxl_reset_surfaces(PCIQXLDevice *d);
133static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
134
135static void qxl_hw_update(void *opaque);
136
137void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
138{
139 trace_qxl_set_guest_bug(qxl->id);
140 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
141 qxl->guest_bug = 1;
142 if (qxl->guestdebug) {
143 va_list ap;
144 va_start(ap, msg);
145 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
146 vfprintf(stderr, msg, ap);
147 fprintf(stderr, "\n");
148 va_end(ap);
149 }
150}
151
152static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
153{
154 qxl->guest_bug = 0;
155}
156
157void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
158 struct QXLRect *area, struct QXLRect *dirty_rects,
159 uint32_t num_dirty_rects,
160 uint32_t clear_dirty_region,
161 qxl_async_io async, struct QXLCookie *cookie)
162{
163 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
164 area->top, area->bottom);
165 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
166 clear_dirty_region);
167 if (async == QXL_SYNC) {
168 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
169 dirty_rects, num_dirty_rects, clear_dirty_region);
170 } else {
171 assert(cookie != NULL);
172 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
173 clear_dirty_region, (uintptr_t)cookie);
174 }
175}
176
177static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
178 uint32_t id)
179{
180 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
181 qemu_mutex_lock(&qxl->track_lock);
182 qxl->guest_surfaces.cmds[id] = 0;
183 qxl->guest_surfaces.count--;
184 qemu_mutex_unlock(&qxl->track_lock);
185}
186
187static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
188 qxl_async_io async)
189{
190 QXLCookie *cookie;
191
192 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
193 if (async) {
194 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
195 QXL_IO_DESTROY_SURFACE_ASYNC);
196 cookie->u.surface_id = id;
197 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
198 } else {
199 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
200 qxl_spice_destroy_surface_wait_complete(qxl, id);
201 }
202}
203
204static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
205{
206 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
207 qxl->num_free_res);
208 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
209 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
210 QXL_IO_FLUSH_SURFACES_ASYNC));
211}
212
213void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
214 uint32_t count)
215{
216 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
217 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
218}
219
220void qxl_spice_oom(PCIQXLDevice *qxl)
221{
222 trace_qxl_spice_oom(qxl->id);
223 spice_qxl_oom(&qxl->ssd.qxl);
224}
225
226void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
227{
228 trace_qxl_spice_reset_memslots(qxl->id);
229 spice_qxl_reset_memslots(&qxl->ssd.qxl);
230}
231
232static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
233{
234 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
235 qemu_mutex_lock(&qxl->track_lock);
236 memset(qxl->guest_surfaces.cmds, 0,
237 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
238 qxl->guest_surfaces.count = 0;
239 qemu_mutex_unlock(&qxl->track_lock);
240}
241
242static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
243{
244 trace_qxl_spice_destroy_surfaces(qxl->id, async);
245 if (async) {
246 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
247 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
248 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
249 } else {
250 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
251 qxl_spice_destroy_surfaces_complete(qxl);
252 }
253}
254
255static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
256{
257 trace_qxl_spice_monitors_config(qxl->id);
258 if (replay) {
259
260
261
262
263
264
265 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
266 qxl->guest_monitors_config,
267 MEMSLOT_GROUP_GUEST,
268 (uintptr_t)qxl_cookie_new(
269 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
270 0));
271 } else {
272 qxl->guest_monitors_config = qxl->ram->monitors_config;
273 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
274 qxl->ram->monitors_config,
275 MEMSLOT_GROUP_GUEST,
276 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
277 QXL_IO_MONITORS_CONFIG_ASYNC));
278 }
279}
280
281void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
282{
283 trace_qxl_spice_reset_image_cache(qxl->id);
284 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
285}
286
287void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
288{
289 trace_qxl_spice_reset_cursor(qxl->id);
290 spice_qxl_reset_cursor(&qxl->ssd.qxl);
291 qemu_mutex_lock(&qxl->track_lock);
292 qxl->guest_cursor = 0;
293 qemu_mutex_unlock(&qxl->track_lock);
294 if (qxl->ssd.cursor) {
295 cursor_put(qxl->ssd.cursor);
296 }
297 qxl->ssd.cursor = cursor_builtin_hidden();
298}
299
300
301static inline uint32_t msb_mask(uint32_t val)
302{
303 uint32_t mask;
304
305 do {
306 mask = ~(val - 1) & val;
307 val &= ~mask;
308 } while (mask < val);
309
310 return mask;
311}
312
313static ram_addr_t qxl_rom_size(void)
314{
315 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
316 sizeof(qxl_modes);
317 uint32_t rom_size = 8192;
318
319 QEMU_BUILD_BUG_ON(required_rom_size > rom_size);
320 return rom_size;
321}
322
323static void init_qxl_rom(PCIQXLDevice *d)
324{
325 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
326 QXLModes *modes = (QXLModes *)(rom + 1);
327 uint32_t ram_header_size;
328 uint32_t surface0_area_size;
329 uint32_t num_pages;
330 uint32_t fb;
331 int i, n;
332
333 memset(rom, 0, d->rom_size);
334
335 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
336 rom->id = cpu_to_le32(d->id);
337 rom->log_level = cpu_to_le32(d->guestdebug);
338 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
339
340 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
341 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
342 rom->slots_start = 1;
343 rom->slots_end = NUM_MEMSLOTS - 1;
344 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
345
346 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
347 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
348 if (fb > d->vgamem_size) {
349 continue;
350 }
351 modes->modes[n].id = cpu_to_le32(i);
352 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
353 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
354 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
355 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
356 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
357 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
358 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
359 n++;
360 }
361 modes->n_modes = cpu_to_le32(n);
362
363 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
364 surface0_area_size = ALIGN(d->vgamem_size, 4096);
365 num_pages = d->vga.vram_size;
366 num_pages -= ram_header_size;
367 num_pages -= surface0_area_size;
368 num_pages = num_pages / QXL_PAGE_SIZE;
369
370 rom->draw_area_offset = cpu_to_le32(0);
371 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
372 rom->pages_offset = cpu_to_le32(surface0_area_size);
373 rom->num_pages = cpu_to_le32(num_pages);
374 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
375
376 d->shadow_rom = *rom;
377 d->rom = rom;
378 d->modes = modes;
379}
380
381static void init_qxl_ram(PCIQXLDevice *d)
382{
383 uint8_t *buf;
384 uint64_t *item;
385
386 buf = d->vga.vram_ptr;
387 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
388 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
389 d->ram->int_pending = cpu_to_le32(0);
390 d->ram->int_mask = cpu_to_le32(0);
391 d->ram->update_surface = 0;
392 d->ram->monitors_config = 0;
393 SPICE_RING_INIT(&d->ram->cmd_ring);
394 SPICE_RING_INIT(&d->ram->cursor_ring);
395 SPICE_RING_INIT(&d->ram->release_ring);
396 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
397 assert(item);
398 *item = 0;
399 qxl_ring_set_dirty(d);
400}
401
402
403static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
404{
405 memory_region_set_dirty(mr, addr, end - addr);
406}
407
408static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
409{
410 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
411}
412
413
414static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
415{
416 void *base = qxl->vga.vram_ptr;
417 intptr_t offset;
418
419 offset = ptr - base;
420 assert(offset < qxl->vga.vram_size);
421 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
422}
423
424
425static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
426{
427 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
428 ram_addr_t end = qxl->vga.vram_size;
429 qxl_set_dirty(&qxl->vga.vram, addr, end);
430}
431
432
433
434
435
436static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
437{
438 switch (le32_to_cpu(ext->cmd.type)) {
439 case QXL_CMD_SURFACE:
440 {
441 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
442
443 if (!cmd) {
444 return 1;
445 }
446 uint32_t id = le32_to_cpu(cmd->surface_id);
447
448 if (id >= qxl->ssd.num_surfaces) {
449 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
450 qxl->ssd.num_surfaces);
451 return 1;
452 }
453 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
454 (cmd->u.surface_create.stride & 0x03) != 0) {
455 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
456 cmd->u.surface_create.stride);
457 return 1;
458 }
459 qemu_mutex_lock(&qxl->track_lock);
460 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
461 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
462 qxl->guest_surfaces.count++;
463 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
464 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
465 }
466 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
467 qxl->guest_surfaces.cmds[id] = 0;
468 qxl->guest_surfaces.count--;
469 }
470 qemu_mutex_unlock(&qxl->track_lock);
471 break;
472 }
473 case QXL_CMD_CURSOR:
474 {
475 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
476
477 if (!cmd) {
478 return 1;
479 }
480 if (cmd->type == QXL_CURSOR_SET) {
481 qemu_mutex_lock(&qxl->track_lock);
482 qxl->guest_cursor = ext->cmd.data;
483 qemu_mutex_unlock(&qxl->track_lock);
484 }
485 break;
486 }
487 }
488 return 0;
489}
490
491
492
493static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
494{
495 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
496
497 trace_qxl_interface_attach_worker(qxl->id);
498 qxl->ssd.worker = qxl_worker;
499}
500
501static void interface_set_compression_level(QXLInstance *sin, int level)
502{
503 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
504
505 trace_qxl_interface_set_compression_level(qxl->id, level);
506 qxl->shadow_rom.compression_level = cpu_to_le32(level);
507 qxl->rom->compression_level = cpu_to_le32(level);
508 qxl_rom_set_dirty(qxl);
509}
510
511static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
512{
513 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
514
515 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
516 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
517 qxl->rom->mm_clock = cpu_to_le32(mm_time);
518 qxl_rom_set_dirty(qxl);
519}
520
521static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
522{
523 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
524
525 trace_qxl_interface_get_init_info(qxl->id);
526 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
527 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
528 info->num_memslots = NUM_MEMSLOTS;
529 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
530 info->internal_groupslot_id = 0;
531 info->qxl_ram_size =
532 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
533 info->n_surfaces = qxl->ssd.num_surfaces;
534}
535
536static const char *qxl_mode_to_string(int mode)
537{
538 switch (mode) {
539 case QXL_MODE_COMPAT:
540 return "compat";
541 case QXL_MODE_NATIVE:
542 return "native";
543 case QXL_MODE_UNDEFINED:
544 return "undefined";
545 case QXL_MODE_VGA:
546 return "vga";
547 }
548 return "INVALID";
549}
550
551static const char *io_port_to_string(uint32_t io_port)
552{
553 if (io_port >= QXL_IO_RANGE_SIZE) {
554 return "out of range";
555 }
556 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
557 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
558 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
559 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
560 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
561 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
562 [QXL_IO_RESET] = "QXL_IO_RESET",
563 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
564 [QXL_IO_LOG] = "QXL_IO_LOG",
565 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
566 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
567 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
568 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
569 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
570 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
571 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
572 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
573 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
574 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
575 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
576 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
577 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
578 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
579 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
580 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
581 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
582 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
583 };
584 return io_port_to_string[io_port];
585}
586
587
588static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
589{
590 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
591 SimpleSpiceUpdate *update;
592 QXLCommandRing *ring;
593 QXLCommand *cmd;
594 int notify, ret;
595
596 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
597
598 switch (qxl->mode) {
599 case QXL_MODE_VGA:
600 ret = false;
601 qemu_mutex_lock(&qxl->ssd.lock);
602 update = QTAILQ_FIRST(&qxl->ssd.updates);
603 if (update != NULL) {
604 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
605 *ext = update->ext;
606 ret = true;
607 }
608 qemu_mutex_unlock(&qxl->ssd.lock);
609 if (ret) {
610 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
611 qxl_log_command(qxl, "vga", ext);
612 }
613 return ret;
614 case QXL_MODE_COMPAT:
615 case QXL_MODE_NATIVE:
616 case QXL_MODE_UNDEFINED:
617 ring = &qxl->ram->cmd_ring;
618 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
619 return false;
620 }
621 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
622 if (!cmd) {
623 return false;
624 }
625 ext->cmd = *cmd;
626 ext->group_id = MEMSLOT_GROUP_GUEST;
627 ext->flags = qxl->cmdflags;
628 SPICE_RING_POP(ring, notify);
629 qxl_ring_set_dirty(qxl);
630 if (notify) {
631 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
632 }
633 qxl->guest_primary.commands++;
634 qxl_track_command(qxl, ext);
635 qxl_log_command(qxl, "cmd", ext);
636 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
637 return true;
638 default:
639 return false;
640 }
641}
642
643
644static int interface_req_cmd_notification(QXLInstance *sin)
645{
646 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
647 int wait = 1;
648
649 trace_qxl_ring_command_req_notification(qxl->id);
650 switch (qxl->mode) {
651 case QXL_MODE_COMPAT:
652 case QXL_MODE_NATIVE:
653 case QXL_MODE_UNDEFINED:
654 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
655 qxl_ring_set_dirty(qxl);
656 break;
657 default:
658
659 break;
660 }
661 return wait;
662}
663
664
665static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
666{
667 QXLReleaseRing *ring = &d->ram->release_ring;
668 uint64_t *item;
669 int notify;
670
671#define QXL_FREE_BUNCH_SIZE 32
672
673 if (ring->prod - ring->cons + 1 == ring->num_items) {
674
675 return;
676 }
677 if (!flush && d->oom_running) {
678
679 return;
680 }
681 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
682
683 return;
684 }
685
686 SPICE_RING_PUSH(ring, notify);
687 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
688 d->guest_surfaces.count, d->num_free_res,
689 d->last_release, notify ? "yes" : "no");
690 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
691 ring->num_items, ring->prod, ring->cons);
692 if (notify) {
693 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
694 }
695 SPICE_RING_PROD_ITEM(d, ring, item);
696 if (!item) {
697 return;
698 }
699 *item = 0;
700 d->num_free_res = 0;
701 d->last_release = NULL;
702 qxl_ring_set_dirty(d);
703}
704
705
706static void interface_release_resource(QXLInstance *sin,
707 struct QXLReleaseInfoExt ext)
708{
709 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
710 QXLReleaseRing *ring;
711 uint64_t *item, id;
712
713 if (ext.group_id == MEMSLOT_GROUP_HOST) {
714
715 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
716 SimpleSpiceUpdate *update;
717 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
718 update = container_of(cmdext, SimpleSpiceUpdate, ext);
719 qemu_spice_destroy_update(&qxl->ssd, update);
720 return;
721 }
722
723
724
725
726
727 ring = &qxl->ram->release_ring;
728 SPICE_RING_PROD_ITEM(qxl, ring, item);
729 if (!item) {
730 return;
731 }
732 if (*item == 0) {
733
734 id = ext.info->id;
735 ext.info->next = 0;
736 qxl_ram_set_dirty(qxl, &ext.info->next);
737 *item = id;
738 qxl_ring_set_dirty(qxl);
739 } else {
740
741 qxl->last_release->next = ext.info->id;
742 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
743 ext.info->next = 0;
744 qxl_ram_set_dirty(qxl, &ext.info->next);
745 }
746 qxl->last_release = ext.info;
747 qxl->num_free_res++;
748 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
749 qxl_push_free_res(qxl, 0);
750}
751
752
753static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
754{
755 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
756 QXLCursorRing *ring;
757 QXLCommand *cmd;
758 int notify;
759
760 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
761
762 switch (qxl->mode) {
763 case QXL_MODE_COMPAT:
764 case QXL_MODE_NATIVE:
765 case QXL_MODE_UNDEFINED:
766 ring = &qxl->ram->cursor_ring;
767 if (SPICE_RING_IS_EMPTY(ring)) {
768 return false;
769 }
770 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
771 if (!cmd) {
772 return false;
773 }
774 ext->cmd = *cmd;
775 ext->group_id = MEMSLOT_GROUP_GUEST;
776 ext->flags = qxl->cmdflags;
777 SPICE_RING_POP(ring, notify);
778 qxl_ring_set_dirty(qxl);
779 if (notify) {
780 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
781 }
782 qxl->guest_primary.commands++;
783 qxl_track_command(qxl, ext);
784 qxl_log_command(qxl, "csr", ext);
785 if (qxl->id == 0) {
786 qxl_render_cursor(qxl, ext);
787 }
788 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
789 return true;
790 default:
791 return false;
792 }
793}
794
795
796static int interface_req_cursor_notification(QXLInstance *sin)
797{
798 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
799 int wait = 1;
800
801 trace_qxl_ring_cursor_req_notification(qxl->id);
802 switch (qxl->mode) {
803 case QXL_MODE_COMPAT:
804 case QXL_MODE_NATIVE:
805 case QXL_MODE_UNDEFINED:
806 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
807 qxl_ring_set_dirty(qxl);
808 break;
809 default:
810
811 break;
812 }
813 return wait;
814}
815
816
817static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
818{
819
820
821
822
823
824
825 fprintf(stderr, "%s: deprecated\n", __func__);
826}
827
828
829static int interface_flush_resources(QXLInstance *sin)
830{
831 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
832 int ret;
833
834 ret = qxl->num_free_res;
835 if (ret) {
836 qxl_push_free_res(qxl, 1);
837 }
838 return ret;
839}
840
841static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
842
843
844static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
845{
846 uint32_t current_async;
847
848 qemu_mutex_lock(&qxl->async_lock);
849 current_async = qxl->current_async;
850 qxl->current_async = QXL_UNDEFINED_IO;
851 qemu_mutex_unlock(&qxl->async_lock);
852
853 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
854 if (!cookie) {
855 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
856 return;
857 }
858 if (cookie && current_async != cookie->io) {
859 fprintf(stderr,
860 "qxl: %s: error: current_async = %d != %"
861 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
862 }
863 switch (current_async) {
864 case QXL_IO_MEMSLOT_ADD_ASYNC:
865 case QXL_IO_DESTROY_PRIMARY_ASYNC:
866 case QXL_IO_UPDATE_AREA_ASYNC:
867 case QXL_IO_FLUSH_SURFACES_ASYNC:
868 case QXL_IO_MONITORS_CONFIG_ASYNC:
869 break;
870 case QXL_IO_CREATE_PRIMARY_ASYNC:
871 qxl_create_guest_primary_complete(qxl);
872 break;
873 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
874 qxl_spice_destroy_surfaces_complete(qxl);
875 break;
876 case QXL_IO_DESTROY_SURFACE_ASYNC:
877 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
878 break;
879 default:
880 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
881 current_async);
882 }
883 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
884}
885
886
887static void interface_update_area_complete(QXLInstance *sin,
888 uint32_t surface_id,
889 QXLRect *dirty, uint32_t num_updated_rects)
890{
891 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
892 int i;
893 int qxl_i;
894
895 qemu_mutex_lock(&qxl->ssd.lock);
896 if (surface_id != 0 || !qxl->render_update_cookie_num) {
897 qemu_mutex_unlock(&qxl->ssd.lock);
898 return;
899 }
900 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
901 dirty->right, dirty->top, dirty->bottom);
902 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
903 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
904
905
906
907 trace_qxl_interface_update_area_complete_overflow(qxl->id,
908 QXL_NUM_DIRTY_RECTS);
909 qxl->guest_primary.resized = 1;
910 }
911 if (qxl->guest_primary.resized) {
912
913
914
915
916 qemu_mutex_unlock(&qxl->ssd.lock);
917 return;
918 }
919 qxl_i = qxl->num_dirty_rects;
920 for (i = 0; i < num_updated_rects; i++) {
921 qxl->dirty[qxl_i++] = dirty[i];
922 }
923 qxl->num_dirty_rects += num_updated_rects;
924 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
925 qxl->num_dirty_rects);
926 qemu_bh_schedule(qxl->update_area_bh);
927 qemu_mutex_unlock(&qxl->ssd.lock);
928}
929
930
931static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
932{
933 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
934 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
935
936 switch (cookie->type) {
937 case QXL_COOKIE_TYPE_IO:
938 interface_async_complete_io(qxl, cookie);
939 g_free(cookie);
940 break;
941 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
942 qxl_render_update_area_done(qxl, cookie);
943 break;
944 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
945 break;
946 default:
947 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
948 __func__, cookie->type);
949 g_free(cookie);
950 }
951}
952
953
954static void interface_set_client_capabilities(QXLInstance *sin,
955 uint8_t client_present,
956 uint8_t caps[58])
957{
958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
959
960 if (qxl->revision < 4) {
961 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
962 qxl->revision);
963 return;
964 }
965
966 if (runstate_check(RUN_STATE_INMIGRATE) ||
967 runstate_check(RUN_STATE_POSTMIGRATE)) {
968 return;
969 }
970
971 qxl->shadow_rom.client_present = client_present;
972 memcpy(qxl->shadow_rom.client_capabilities, caps,
973 sizeof(qxl->shadow_rom.client_capabilities));
974 qxl->rom->client_present = client_present;
975 memcpy(qxl->rom->client_capabilities, caps,
976 sizeof(qxl->rom->client_capabilities));
977 qxl_rom_set_dirty(qxl);
978
979 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
980}
981
982static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
983{
984
985
986
987
988
989 return crc32(0xffffffff, p, len) ^ 0xffffffff;
990}
991
992
993static int interface_client_monitors_config(QXLInstance *sin,
994 VDAgentMonitorsConfig *monitors_config)
995{
996 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
997 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
998 int i;
999
1000 if (qxl->revision < 4) {
1001 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1002 qxl->revision);
1003 return 0;
1004 }
1005
1006
1007
1008
1009
1010
1011 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1012 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1013 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1014 qxl->ram->int_mask,
1015 monitors_config);
1016 return 0;
1017 }
1018 if (!monitors_config) {
1019 return 1;
1020 }
1021 memset(&rom->client_monitors_config, 0,
1022 sizeof(rom->client_monitors_config));
1023 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1024
1025 if (rom->client_monitors_config.count >=
1026 ARRAY_SIZE(rom->client_monitors_config.heads)) {
1027 trace_qxl_client_monitors_config_capped(qxl->id,
1028 monitors_config->num_of_monitors,
1029 ARRAY_SIZE(rom->client_monitors_config.heads));
1030 rom->client_monitors_config.count =
1031 ARRAY_SIZE(rom->client_monitors_config.heads);
1032 }
1033 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1034 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1035 QXLURect *rect = &rom->client_monitors_config.heads[i];
1036
1037 rect->left = monitor->x;
1038 rect->top = monitor->y;
1039 rect->right = monitor->x + monitor->width;
1040 rect->bottom = monitor->y + monitor->height;
1041 }
1042 rom->client_monitors_config_crc = qxl_crc32(
1043 (const uint8_t *)&rom->client_monitors_config,
1044 sizeof(rom->client_monitors_config));
1045 trace_qxl_client_monitors_config_crc(qxl->id,
1046 sizeof(rom->client_monitors_config),
1047 rom->client_monitors_config_crc);
1048
1049 trace_qxl_interrupt_client_monitors_config(qxl->id,
1050 rom->client_monitors_config.count,
1051 rom->client_monitors_config.heads);
1052 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1053 return 1;
1054}
1055
1056static const QXLInterface qxl_interface = {
1057 .base.type = SPICE_INTERFACE_QXL,
1058 .base.description = "qxl gpu",
1059 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1060 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1061
1062 .attache_worker = interface_attach_worker,
1063 .set_compression_level = interface_set_compression_level,
1064 .set_mm_time = interface_set_mm_time,
1065 .get_init_info = interface_get_init_info,
1066
1067
1068 .get_command = interface_get_command,
1069 .req_cmd_notification = interface_req_cmd_notification,
1070 .release_resource = interface_release_resource,
1071 .get_cursor_command = interface_get_cursor_command,
1072 .req_cursor_notification = interface_req_cursor_notification,
1073 .notify_update = interface_notify_update,
1074 .flush_resources = interface_flush_resources,
1075 .async_complete = interface_async_complete,
1076 .update_area_complete = interface_update_area_complete,
1077 .set_client_capabilities = interface_set_client_capabilities,
1078 .client_monitors_config = interface_client_monitors_config,
1079};
1080
1081static const GraphicHwOps qxl_ops = {
1082 .gfx_update = qxl_hw_update,
1083};
1084
1085static void qxl_enter_vga_mode(PCIQXLDevice *d)
1086{
1087 if (d->mode == QXL_MODE_VGA) {
1088 return;
1089 }
1090 trace_qxl_enter_vga_mode(d->id);
1091#if SPICE_SERVER_VERSION >= 0x000c03
1092 spice_qxl_driver_unload(&d->ssd.qxl);
1093#endif
1094 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1095 qemu_spice_create_host_primary(&d->ssd);
1096 d->mode = QXL_MODE_VGA;
1097 vga_dirty_log_start(&d->vga);
1098 graphic_hw_update(d->vga.con);
1099}
1100
1101static void qxl_exit_vga_mode(PCIQXLDevice *d)
1102{
1103 if (d->mode != QXL_MODE_VGA) {
1104 return;
1105 }
1106 trace_qxl_exit_vga_mode(d->id);
1107 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1108 vga_dirty_log_stop(&d->vga);
1109 qxl_destroy_primary(d, QXL_SYNC);
1110}
1111
1112static void qxl_update_irq(PCIQXLDevice *d)
1113{
1114 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1115 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1116 int level = !!(pending & mask);
1117 pci_set_irq(&d->pci, level);
1118 qxl_ring_set_dirty(d);
1119}
1120
1121static void qxl_check_state(PCIQXLDevice *d)
1122{
1123 QXLRam *ram = d->ram;
1124 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1125
1126 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1127 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1128}
1129
1130static void qxl_reset_state(PCIQXLDevice *d)
1131{
1132 QXLRom *rom = d->rom;
1133
1134 qxl_check_state(d);
1135 d->shadow_rom.update_id = cpu_to_le32(0);
1136 *rom = d->shadow_rom;
1137 qxl_rom_set_dirty(d);
1138 init_qxl_ram(d);
1139 d->num_free_res = 0;
1140 d->last_release = NULL;
1141 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1142 qxl_update_irq(d);
1143}
1144
1145static void qxl_soft_reset(PCIQXLDevice *d)
1146{
1147 trace_qxl_soft_reset(d->id);
1148 qxl_check_state(d);
1149 qxl_clear_guest_bug(d);
1150 d->current_async = QXL_UNDEFINED_IO;
1151
1152 if (d->id == 0) {
1153 qxl_enter_vga_mode(d);
1154 } else {
1155 d->mode = QXL_MODE_UNDEFINED;
1156 }
1157}
1158
1159static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1160{
1161 bool startstop = qemu_spice_display_is_running(&d->ssd);
1162
1163 trace_qxl_hard_reset(d->id, loadvm);
1164
1165 if (startstop) {
1166 qemu_spice_display_stop();
1167 }
1168
1169 qxl_spice_reset_cursor(d);
1170 qxl_spice_reset_image_cache(d);
1171 qxl_reset_surfaces(d);
1172 qxl_reset_memslots(d);
1173
1174
1175
1176
1177 if (!loadvm) {
1178 qxl_reset_state(d);
1179 }
1180 qemu_spice_create_host_memslot(&d->ssd);
1181 qxl_soft_reset(d);
1182
1183 if (startstop) {
1184 qemu_spice_display_start();
1185 }
1186}
1187
1188static void qxl_reset_handler(DeviceState *dev)
1189{
1190 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
1191
1192 qxl_hard_reset(d, 0);
1193}
1194
1195static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1196{
1197 VGACommonState *vga = opaque;
1198 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1199
1200 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1201 if (qxl->mode != QXL_MODE_VGA) {
1202 qxl_destroy_primary(qxl, QXL_SYNC);
1203 qxl_soft_reset(qxl);
1204 }
1205 vga_ioport_write(opaque, addr, val);
1206}
1207
1208static const MemoryRegionPortio qxl_vga_portio_list[] = {
1209 { 0x04, 2, 1, .read = vga_ioport_read,
1210 .write = qxl_vga_ioport_write },
1211 { 0x0a, 1, 1, .read = vga_ioport_read,
1212 .write = qxl_vga_ioport_write },
1213 { 0x10, 16, 1, .read = vga_ioport_read,
1214 .write = qxl_vga_ioport_write },
1215 { 0x24, 2, 1, .read = vga_ioport_read,
1216 .write = qxl_vga_ioport_write },
1217 { 0x2a, 1, 1, .read = vga_ioport_read,
1218 .write = qxl_vga_ioport_write },
1219 PORTIO_END_OF_LIST(),
1220};
1221
1222static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1223 qxl_async_io async)
1224{
1225 static const int regions[] = {
1226 QXL_RAM_RANGE_INDEX,
1227 QXL_VRAM_RANGE_INDEX,
1228 QXL_VRAM64_RANGE_INDEX,
1229 };
1230 uint64_t guest_start;
1231 uint64_t guest_end;
1232 int pci_region;
1233 pcibus_t pci_start;
1234 pcibus_t pci_end;
1235 intptr_t virt_start;
1236 QXLDevMemSlot memslot;
1237 int i;
1238
1239 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1240 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1241
1242 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1243
1244 if (slot_id >= NUM_MEMSLOTS) {
1245 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1246 slot_id, NUM_MEMSLOTS);
1247 return 1;
1248 }
1249 if (guest_start > guest_end) {
1250 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1251 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1252 return 1;
1253 }
1254
1255 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1256 pci_region = regions[i];
1257 pci_start = d->pci.io_regions[pci_region].addr;
1258 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1259
1260 if (pci_start == -1) {
1261 continue;
1262 }
1263
1264 if (guest_start < pci_start || guest_start > pci_end) {
1265 continue;
1266 }
1267
1268 if (guest_end > pci_end) {
1269 continue;
1270 }
1271
1272 break;
1273 }
1274 if (i == ARRAY_SIZE(regions)) {
1275 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1276 return 1;
1277 }
1278
1279 switch (pci_region) {
1280 case QXL_RAM_RANGE_INDEX:
1281 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1282 break;
1283 case QXL_VRAM_RANGE_INDEX:
1284 case 4 :
1285 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1286 break;
1287 default:
1288
1289 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1290 return 1;
1291 }
1292
1293 memslot.slot_id = slot_id;
1294 memslot.slot_group_id = MEMSLOT_GROUP_GUEST;
1295 memslot.virt_start = virt_start + (guest_start - pci_start);
1296 memslot.virt_end = virt_start + (guest_end - pci_start);
1297 memslot.addr_delta = memslot.virt_start - delta;
1298 memslot.generation = d->rom->slot_generation = 0;
1299 qxl_rom_set_dirty(d);
1300
1301 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1302 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1303 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1304 d->guest_slots[slot_id].delta = delta;
1305 d->guest_slots[slot_id].active = 1;
1306 return 0;
1307}
1308
1309static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1310{
1311 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1312 d->guest_slots[slot_id].active = 0;
1313}
1314
1315static void qxl_reset_memslots(PCIQXLDevice *d)
1316{
1317 qxl_spice_reset_memslots(d);
1318 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1319}
1320
1321static void qxl_reset_surfaces(PCIQXLDevice *d)
1322{
1323 trace_qxl_reset_surfaces(d->id);
1324 d->mode = QXL_MODE_UNDEFINED;
1325 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1326}
1327
1328
1329void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1330{
1331 uint64_t phys = le64_to_cpu(pqxl);
1332 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1333 uint64_t offset = phys & 0xffffffffffff;
1334
1335 switch (group_id) {
1336 case MEMSLOT_GROUP_HOST:
1337 return (void *)(intptr_t)offset;
1338 case MEMSLOT_GROUP_GUEST:
1339 if (slot >= NUM_MEMSLOTS) {
1340 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1341 NUM_MEMSLOTS);
1342 return NULL;
1343 }
1344 if (!qxl->guest_slots[slot].active) {
1345 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1346 return NULL;
1347 }
1348 if (offset < qxl->guest_slots[slot].delta) {
1349 qxl_set_guest_bug(qxl,
1350 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1351 slot, offset, qxl->guest_slots[slot].delta);
1352 return NULL;
1353 }
1354 offset -= qxl->guest_slots[slot].delta;
1355 if (offset > qxl->guest_slots[slot].size) {
1356 qxl_set_guest_bug(qxl,
1357 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1358 slot, offset, qxl->guest_slots[slot].size);
1359 return NULL;
1360 }
1361 return qxl->guest_slots[slot].ptr + offset;
1362 }
1363 return NULL;
1364}
1365
1366static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1367{
1368
1369 qxl_render_resize(qxl);
1370}
1371
1372static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1373 qxl_async_io async)
1374{
1375 QXLDevSurfaceCreate surface;
1376 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1377 uint32_t requested_height = le32_to_cpu(sc->height);
1378 int requested_stride = le32_to_cpu(sc->stride);
1379
1380 if (requested_stride == INT32_MIN ||
1381 abs(requested_stride) * (uint64_t)requested_height
1382 > qxl->vgamem_size) {
1383 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1384 " stride %d x height %" PRIu32 " > %" PRIu32,
1385 __func__, requested_stride, requested_height,
1386 qxl->vgamem_size);
1387 return;
1388 }
1389
1390 if (qxl->mode == QXL_MODE_NATIVE) {
1391 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1392 __func__);
1393 }
1394 qxl_exit_vga_mode(qxl);
1395
1396 surface.format = le32_to_cpu(sc->format);
1397 surface.height = le32_to_cpu(sc->height);
1398 surface.mem = le64_to_cpu(sc->mem);
1399 surface.position = le32_to_cpu(sc->position);
1400 surface.stride = le32_to_cpu(sc->stride);
1401 surface.width = le32_to_cpu(sc->width);
1402 surface.type = le32_to_cpu(sc->type);
1403 surface.flags = le32_to_cpu(sc->flags);
1404 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1405 sc->format, sc->position);
1406 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1407 sc->flags);
1408
1409 if ((surface.stride & 0x3) != 0) {
1410 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1411 surface.stride);
1412 return;
1413 }
1414
1415 surface.mouse_mode = true;
1416 surface.group_id = MEMSLOT_GROUP_GUEST;
1417 if (loadvm) {
1418 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1419 }
1420
1421 qxl->mode = QXL_MODE_NATIVE;
1422 qxl->cmdflags = 0;
1423 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1424
1425 if (async == QXL_SYNC) {
1426 qxl_create_guest_primary_complete(qxl);
1427 }
1428}
1429
1430
1431
1432static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1433{
1434 if (d->mode == QXL_MODE_UNDEFINED) {
1435 return 0;
1436 }
1437 trace_qxl_destroy_primary(d->id);
1438 d->mode = QXL_MODE_UNDEFINED;
1439 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1440 qxl_spice_reset_cursor(d);
1441 return 1;
1442}
1443
1444static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1445{
1446 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1447 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1448 QXLMode *mode = d->modes->modes + modenr;
1449 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1450 QXLMemSlot slot = {
1451 .mem_start = start,
1452 .mem_end = end
1453 };
1454
1455 if (modenr >= d->modes->n_modes) {
1456 qxl_set_guest_bug(d, "mode number out of range");
1457 return;
1458 }
1459
1460 QXLSurfaceCreate surface = {
1461 .width = mode->x_res,
1462 .height = mode->y_res,
1463 .stride = -mode->x_res * 4,
1464 .format = SPICE_SURFACE_FMT_32_xRGB,
1465 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1466 .mouse_mode = true,
1467 .mem = devmem + d->shadow_rom.draw_area_offset,
1468 };
1469
1470 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1471 devmem);
1472 if (!loadvm) {
1473 qxl_hard_reset(d, 0);
1474 }
1475
1476 d->guest_slots[0].slot = slot;
1477 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1478
1479 d->guest_primary.surface = surface;
1480 qxl_create_guest_primary(d, 0, QXL_SYNC);
1481
1482 d->mode = QXL_MODE_COMPAT;
1483 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1484 if (mode->bits == 16) {
1485 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1486 }
1487 d->shadow_rom.mode = cpu_to_le32(modenr);
1488 d->rom->mode = cpu_to_le32(modenr);
1489 qxl_rom_set_dirty(d);
1490}
1491
1492static void ioport_write(void *opaque, hwaddr addr,
1493 uint64_t val, unsigned size)
1494{
1495 PCIQXLDevice *d = opaque;
1496 uint32_t io_port = addr;
1497 qxl_async_io async = QXL_SYNC;
1498 uint32_t orig_io_port = io_port;
1499
1500 if (d->guest_bug && io_port != QXL_IO_RESET) {
1501 return;
1502 }
1503
1504 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1505 io_port > QXL_IO_FLUSH_RELEASE) {
1506 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1507 io_port, d->revision);
1508 return;
1509 }
1510
1511 switch (io_port) {
1512 case QXL_IO_RESET:
1513 case QXL_IO_SET_MODE:
1514 case QXL_IO_MEMSLOT_ADD:
1515 case QXL_IO_MEMSLOT_DEL:
1516 case QXL_IO_CREATE_PRIMARY:
1517 case QXL_IO_UPDATE_IRQ:
1518 case QXL_IO_LOG:
1519 case QXL_IO_MEMSLOT_ADD_ASYNC:
1520 case QXL_IO_CREATE_PRIMARY_ASYNC:
1521 break;
1522 default:
1523 if (d->mode != QXL_MODE_VGA) {
1524 break;
1525 }
1526 trace_qxl_io_unexpected_vga_mode(d->id,
1527 addr, val, io_port_to_string(io_port));
1528
1529 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1530 io_port < QXL_IO_RANGE_SIZE) {
1531 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1532 }
1533 return;
1534 }
1535
1536
1537 orig_io_port = io_port;
1538 switch (io_port) {
1539 case QXL_IO_UPDATE_AREA_ASYNC:
1540 io_port = QXL_IO_UPDATE_AREA;
1541 goto async_common;
1542 case QXL_IO_MEMSLOT_ADD_ASYNC:
1543 io_port = QXL_IO_MEMSLOT_ADD;
1544 goto async_common;
1545 case QXL_IO_CREATE_PRIMARY_ASYNC:
1546 io_port = QXL_IO_CREATE_PRIMARY;
1547 goto async_common;
1548 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1549 io_port = QXL_IO_DESTROY_PRIMARY;
1550 goto async_common;
1551 case QXL_IO_DESTROY_SURFACE_ASYNC:
1552 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1553 goto async_common;
1554 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1555 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1556 goto async_common;
1557 case QXL_IO_FLUSH_SURFACES_ASYNC:
1558 case QXL_IO_MONITORS_CONFIG_ASYNC:
1559async_common:
1560 async = QXL_ASYNC;
1561 qemu_mutex_lock(&d->async_lock);
1562 if (d->current_async != QXL_UNDEFINED_IO) {
1563 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1564 io_port, d->current_async);
1565 qemu_mutex_unlock(&d->async_lock);
1566 return;
1567 }
1568 d->current_async = orig_io_port;
1569 qemu_mutex_unlock(&d->async_lock);
1570 break;
1571 default:
1572 break;
1573 }
1574 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1575 addr, io_port_to_string(addr),
1576 val, size, async);
1577
1578 switch (io_port) {
1579 case QXL_IO_UPDATE_AREA:
1580 {
1581 QXLCookie *cookie = NULL;
1582 QXLRect update = d->ram->update_area;
1583
1584 if (d->ram->update_surface > d->ssd.num_surfaces) {
1585 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1586 d->ram->update_surface);
1587 break;
1588 }
1589 if (update.left >= update.right || update.top >= update.bottom ||
1590 update.left < 0 || update.top < 0) {
1591 qxl_set_guest_bug(d,
1592 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1593 update.left, update.top, update.right, update.bottom);
1594 if (update.left == update.right || update.top == update.bottom) {
1595
1596 qxl_clear_guest_bug(d);
1597 goto cancel_async;
1598 }
1599 break;
1600 }
1601 if (async == QXL_ASYNC) {
1602 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1603 QXL_IO_UPDATE_AREA_ASYNC);
1604 cookie->u.area = update;
1605 }
1606 qxl_spice_update_area(d, d->ram->update_surface,
1607 cookie ? &cookie->u.area : &update,
1608 NULL, 0, 0, async, cookie);
1609 break;
1610 }
1611 case QXL_IO_NOTIFY_CMD:
1612 qemu_spice_wakeup(&d->ssd);
1613 break;
1614 case QXL_IO_NOTIFY_CURSOR:
1615 qemu_spice_wakeup(&d->ssd);
1616 break;
1617 case QXL_IO_UPDATE_IRQ:
1618 qxl_update_irq(d);
1619 break;
1620 case QXL_IO_NOTIFY_OOM:
1621 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1622 break;
1623 }
1624 d->oom_running = 1;
1625 qxl_spice_oom(d);
1626 d->oom_running = 0;
1627 break;
1628 case QXL_IO_SET_MODE:
1629 qxl_set_mode(d, val, 0);
1630 break;
1631 case QXL_IO_LOG:
1632 trace_qxl_io_log(d->id, d->ram->log_buf);
1633 if (d->guestdebug) {
1634 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1635 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
1636 }
1637 break;
1638 case QXL_IO_RESET:
1639 qxl_hard_reset(d, 0);
1640 break;
1641 case QXL_IO_MEMSLOT_ADD:
1642 if (val >= NUM_MEMSLOTS) {
1643 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1644 break;
1645 }
1646 if (d->guest_slots[val].active) {
1647 qxl_set_guest_bug(d,
1648 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1649 break;
1650 }
1651 d->guest_slots[val].slot = d->ram->mem_slot;
1652 qxl_add_memslot(d, val, 0, async);
1653 break;
1654 case QXL_IO_MEMSLOT_DEL:
1655 if (val >= NUM_MEMSLOTS) {
1656 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1657 break;
1658 }
1659 qxl_del_memslot(d, val);
1660 break;
1661 case QXL_IO_CREATE_PRIMARY:
1662 if (val != 0) {
1663 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1664 async);
1665 goto cancel_async;
1666 }
1667 d->guest_primary.surface = d->ram->create_surface;
1668 qxl_create_guest_primary(d, 0, async);
1669 break;
1670 case QXL_IO_DESTROY_PRIMARY:
1671 if (val != 0) {
1672 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1673 async);
1674 goto cancel_async;
1675 }
1676 if (!qxl_destroy_primary(d, async)) {
1677 trace_qxl_io_destroy_primary_ignored(d->id,
1678 qxl_mode_to_string(d->mode));
1679 goto cancel_async;
1680 }
1681 break;
1682 case QXL_IO_DESTROY_SURFACE_WAIT:
1683 if (val >= d->ssd.num_surfaces) {
1684 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1685 "%" PRIu64 " >= NUM_SURFACES", async, val);
1686 goto cancel_async;
1687 }
1688 qxl_spice_destroy_surface_wait(d, val, async);
1689 break;
1690 case QXL_IO_FLUSH_RELEASE: {
1691 QXLReleaseRing *ring = &d->ram->release_ring;
1692 if (ring->prod - ring->cons + 1 == ring->num_items) {
1693 fprintf(stderr,
1694 "ERROR: no flush, full release ring [p%d,%dc]\n",
1695 ring->prod, ring->cons);
1696 }
1697 qxl_push_free_res(d, 1 );
1698 break;
1699 }
1700 case QXL_IO_FLUSH_SURFACES_ASYNC:
1701 qxl_spice_flush_surfaces_async(d);
1702 break;
1703 case QXL_IO_DESTROY_ALL_SURFACES:
1704 d->mode = QXL_MODE_UNDEFINED;
1705 qxl_spice_destroy_surfaces(d, async);
1706 break;
1707 case QXL_IO_MONITORS_CONFIG_ASYNC:
1708 qxl_spice_monitors_config_async(d, 0);
1709 break;
1710 default:
1711 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1712 }
1713 return;
1714cancel_async:
1715 if (async) {
1716 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1717 qemu_mutex_lock(&d->async_lock);
1718 d->current_async = QXL_UNDEFINED_IO;
1719 qemu_mutex_unlock(&d->async_lock);
1720 }
1721}
1722
1723static uint64_t ioport_read(void *opaque, hwaddr addr,
1724 unsigned size)
1725{
1726 PCIQXLDevice *qxl = opaque;
1727
1728 trace_qxl_io_read_unexpected(qxl->id);
1729 return 0xff;
1730}
1731
1732static const MemoryRegionOps qxl_io_ops = {
1733 .read = ioport_read,
1734 .write = ioport_write,
1735 .valid = {
1736 .min_access_size = 1,
1737 .max_access_size = 1,
1738 },
1739};
1740
1741static void qxl_update_irq_bh(void *opaque)
1742{
1743 PCIQXLDevice *d = opaque;
1744 qxl_update_irq(d);
1745}
1746
1747static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1748{
1749 uint32_t old_pending;
1750 uint32_t le_events = cpu_to_le32(events);
1751
1752 trace_qxl_send_events(d->id, events);
1753 if (!qemu_spice_display_is_running(&d->ssd)) {
1754
1755 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1756 __func__);
1757 trace_qxl_send_events_vm_stopped(d->id, events);
1758 return;
1759 }
1760 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
1761 if ((old_pending & le_events) == le_events) {
1762 return;
1763 }
1764 qemu_bh_schedule(d->update_irq);
1765}
1766
1767
1768
1769static void qxl_hw_update(void *opaque)
1770{
1771 PCIQXLDevice *qxl = opaque;
1772
1773 qxl_render_update(qxl);
1774}
1775
1776static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1777{
1778 uintptr_t vram_start;
1779 int i;
1780
1781 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1782 return;
1783 }
1784
1785
1786 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1787 qxl->shadow_rom.surface0_area_size);
1788
1789 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1790
1791
1792 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1793 QXLSurfaceCmd *cmd;
1794 intptr_t surface_offset;
1795 int surface_size;
1796
1797 if (qxl->guest_surfaces.cmds[i] == 0) {
1798 continue;
1799 }
1800
1801 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1802 MEMSLOT_GROUP_GUEST);
1803 assert(cmd);
1804 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1805 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1806 cmd->u.surface_create.data,
1807 MEMSLOT_GROUP_GUEST);
1808 assert(surface_offset);
1809 surface_offset -= vram_start;
1810 surface_size = cmd->u.surface_create.height *
1811 abs(cmd->u.surface_create.stride);
1812 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1813 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1814 }
1815}
1816
1817static void qxl_vm_change_state_handler(void *opaque, int running,
1818 RunState state)
1819{
1820 PCIQXLDevice *qxl = opaque;
1821
1822 if (running) {
1823
1824
1825
1826
1827
1828 qxl_update_irq(qxl);
1829 } else {
1830
1831 qxl_dirty_surfaces(qxl);
1832 }
1833}
1834
1835
1836
1837static void display_update(DisplayChangeListener *dcl,
1838 int x, int y, int w, int h)
1839{
1840 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1841
1842 if (qxl->mode == QXL_MODE_VGA) {
1843 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
1844 }
1845}
1846
1847static void display_switch(DisplayChangeListener *dcl,
1848 struct DisplaySurface *surface)
1849{
1850 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1851
1852 qxl->ssd.ds = surface;
1853 if (qxl->mode == QXL_MODE_VGA) {
1854 qemu_spice_display_switch(&qxl->ssd, surface);
1855 }
1856}
1857
1858static void display_refresh(DisplayChangeListener *dcl)
1859{
1860 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1861
1862 if (qxl->mode == QXL_MODE_VGA) {
1863 qemu_spice_display_refresh(&qxl->ssd);
1864 } else {
1865 qemu_mutex_lock(&qxl->ssd.lock);
1866 qemu_spice_cursor_refresh_unlocked(&qxl->ssd);
1867 qemu_mutex_unlock(&qxl->ssd.lock);
1868 }
1869}
1870
1871static DisplayChangeListenerOps display_listener_ops = {
1872 .dpy_name = "spice/qxl",
1873 .dpy_gfx_update = display_update,
1874 .dpy_gfx_switch = display_switch,
1875 .dpy_refresh = display_refresh,
1876};
1877
1878static void qxl_init_ramsize(PCIQXLDevice *qxl)
1879{
1880
1881 if (qxl->vgamem_size_mb < 8) {
1882 qxl->vgamem_size_mb = 8;
1883 }
1884 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1885
1886
1887 if (qxl->ram_size_mb != -1) {
1888 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1889 }
1890 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1891 qxl->vga.vram_size = qxl->vgamem_size * 2;
1892 }
1893
1894
1895 if (qxl->vram32_size_mb != -1) {
1896 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1897 }
1898 if (qxl->vram32_size < 4096) {
1899 qxl->vram32_size = 4096;
1900 }
1901
1902
1903 if (qxl->vram_size_mb != -1) {
1904 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1905 }
1906 if (qxl->vram_size < qxl->vram32_size) {
1907 qxl->vram_size = qxl->vram32_size;
1908 }
1909
1910 if (qxl->revision == 1) {
1911 qxl->vram32_size = 4096;
1912 qxl->vram_size = 4096;
1913 }
1914 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
1915 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1916 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1917 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1918}
1919
1920static int qxl_init_common(PCIQXLDevice *qxl)
1921{
1922 uint8_t* config = qxl->pci.config;
1923 uint32_t pci_device_rev;
1924 uint32_t io_size;
1925
1926 qxl->mode = QXL_MODE_UNDEFINED;
1927 qxl->generation = 1;
1928 qxl->num_memslots = NUM_MEMSLOTS;
1929 qemu_mutex_init(&qxl->track_lock);
1930 qemu_mutex_init(&qxl->async_lock);
1931 qxl->current_async = QXL_UNDEFINED_IO;
1932 qxl->guest_bug = 0;
1933
1934 switch (qxl->revision) {
1935 case 1:
1936 pci_device_rev = QXL_REVISION_STABLE_V04;
1937 io_size = 8;
1938 break;
1939 case 2:
1940 pci_device_rev = QXL_REVISION_STABLE_V06;
1941 io_size = 16;
1942 break;
1943 case 3:
1944 pci_device_rev = QXL_REVISION_STABLE_V10;
1945 io_size = 32;
1946 break;
1947 case 4:
1948 pci_device_rev = QXL_REVISION_STABLE_V12;
1949 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1950 break;
1951 default:
1952 error_report("Invalid revision %d for qxl device (max %d)",
1953 qxl->revision, QXL_DEFAULT_REVISION);
1954 return -1;
1955 }
1956
1957 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1958 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1959
1960 qxl->rom_size = qxl_rom_size();
1961 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
1962 qxl->rom_size, &error_abort);
1963 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1964 init_qxl_rom(qxl);
1965 init_qxl_ram(qxl);
1966
1967 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
1968 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
1969 qxl->vram_size, &error_abort);
1970 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1971 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
1972 &qxl->vram_bar, 0, qxl->vram32_size);
1973
1974 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
1975 "qxl-ioports", io_size);
1976 if (qxl->id == 0) {
1977 vga_dirty_log_start(&qxl->vga);
1978 }
1979 memory_region_set_flush_coalesced(&qxl->io_bar);
1980
1981
1982 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1983 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1984
1985 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1986 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1987
1988 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1989 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1990
1991 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1992 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
1993
1994 if (qxl->vram32_size < qxl->vram_size) {
1995
1996
1997
1998
1999 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2000 PCI_BASE_ADDRESS_SPACE_MEMORY |
2001 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2002 PCI_BASE_ADDRESS_MEM_PREFETCH,
2003 &qxl->vram_bar);
2004 }
2005
2006
2007 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2008 qxl->id == 0 ? "pri" : "sec",
2009 qxl->vga.vram_size / (1024*1024));
2010 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2011 qxl->vram32_size / (1024*1024));
2012 dprint(qxl, 1, "vram/64: %d MB %s\n",
2013 qxl->vram_size / (1024*1024),
2014 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2015
2016 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2017 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2018 error_report("qxl interface %d.%d not supported by spice-server",
2019 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2020 return -1;
2021 }
2022 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2023
2024 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2025 qxl_reset_state(qxl);
2026
2027 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2028
2029 return 0;
2030}
2031
2032static int qxl_init_primary(PCIDevice *dev)
2033{
2034 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2035 VGACommonState *vga = &qxl->vga;
2036 int rc;
2037
2038 qxl->id = 0;
2039 qxl_init_ramsize(qxl);
2040 vga->vbe_size = qxl->vgamem_size;
2041 vga->vram_size_mb = qxl->vga.vram_size >> 20;
2042 vga_common_init(vga, OBJECT(dev), true);
2043 vga_init(vga, OBJECT(dev),
2044 pci_address_space(dev), pci_address_space_io(dev), false);
2045 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2046 vga, "vga");
2047 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2048 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2049
2050 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2051 qemu_spice_display_init_common(&qxl->ssd);
2052
2053 rc = qxl_init_common(qxl);
2054 if (rc != 0) {
2055 return rc;
2056 }
2057
2058 qxl->ssd.dcl.ops = &display_listener_ops;
2059 qxl->ssd.dcl.con = vga->con;
2060 register_displaychangelistener(&qxl->ssd.dcl);
2061 return rc;
2062}
2063
2064static int qxl_init_secondary(PCIDevice *dev)
2065{
2066 static int device_id = 1;
2067 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2068
2069 qxl->id = device_id++;
2070 qxl_init_ramsize(qxl);
2071 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2072 qxl->vga.vram_size, &error_abort);
2073 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
2074 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2075 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2076
2077 return qxl_init_common(qxl);
2078}
2079
2080static void qxl_pre_save(void *opaque)
2081{
2082 PCIQXLDevice* d = opaque;
2083 uint8_t *ram_start = d->vga.vram_ptr;
2084
2085 trace_qxl_pre_save(d->id);
2086 if (d->last_release == NULL) {
2087 d->last_release_offset = 0;
2088 } else {
2089 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2090 }
2091 assert(d->last_release_offset < d->vga.vram_size);
2092}
2093
2094static int qxl_pre_load(void *opaque)
2095{
2096 PCIQXLDevice* d = opaque;
2097
2098 trace_qxl_pre_load(d->id);
2099 qxl_hard_reset(d, 1);
2100 qxl_exit_vga_mode(d);
2101 return 0;
2102}
2103
2104static void qxl_create_memslots(PCIQXLDevice *d)
2105{
2106 int i;
2107
2108 for (i = 0; i < NUM_MEMSLOTS; i++) {
2109 if (!d->guest_slots[i].active) {
2110 continue;
2111 }
2112 qxl_add_memslot(d, i, 0, QXL_SYNC);
2113 }
2114}
2115
2116static int qxl_post_load(void *opaque, int version)
2117{
2118 PCIQXLDevice* d = opaque;
2119 uint8_t *ram_start = d->vga.vram_ptr;
2120 QXLCommandExt *cmds;
2121 int in, out, newmode;
2122
2123 assert(d->last_release_offset < d->vga.vram_size);
2124 if (d->last_release_offset == 0) {
2125 d->last_release = NULL;
2126 } else {
2127 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2128 }
2129
2130 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2131
2132 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2133 newmode = d->mode;
2134 d->mode = QXL_MODE_UNDEFINED;
2135
2136 switch (newmode) {
2137 case QXL_MODE_UNDEFINED:
2138 qxl_create_memslots(d);
2139 break;
2140 case QXL_MODE_VGA:
2141 qxl_create_memslots(d);
2142 qxl_enter_vga_mode(d);
2143 break;
2144 case QXL_MODE_NATIVE:
2145 qxl_create_memslots(d);
2146 qxl_create_guest_primary(d, 1, QXL_SYNC);
2147
2148
2149 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2150 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2151 if (d->guest_surfaces.cmds[in] == 0) {
2152 continue;
2153 }
2154 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2155 cmds[out].cmd.type = QXL_CMD_SURFACE;
2156 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2157 out++;
2158 }
2159 if (d->guest_cursor) {
2160 cmds[out].cmd.data = d->guest_cursor;
2161 cmds[out].cmd.type = QXL_CMD_CURSOR;
2162 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2163 out++;
2164 }
2165 qxl_spice_loadvm_commands(d, cmds, out);
2166 g_free(cmds);
2167 if (d->guest_monitors_config) {
2168 qxl_spice_monitors_config_async(d, 1);
2169 }
2170 break;
2171 case QXL_MODE_COMPAT:
2172
2173
2174 qxl_set_mode(d, d->shadow_rom.mode, 1);
2175 break;
2176 }
2177 return 0;
2178}
2179
2180#define QXL_SAVE_VERSION 21
2181
2182static bool qxl_monitors_config_needed(void *opaque)
2183{
2184 PCIQXLDevice *qxl = opaque;
2185
2186 return qxl->guest_monitors_config != 0;
2187}
2188
2189
2190static VMStateDescription qxl_memslot = {
2191 .name = "qxl-memslot",
2192 .version_id = QXL_SAVE_VERSION,
2193 .minimum_version_id = QXL_SAVE_VERSION,
2194 .fields = (VMStateField[]) {
2195 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2196 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2197 VMSTATE_UINT32(active, struct guest_slots),
2198 VMSTATE_END_OF_LIST()
2199 }
2200};
2201
2202static VMStateDescription qxl_surface = {
2203 .name = "qxl-surface",
2204 .version_id = QXL_SAVE_VERSION,
2205 .minimum_version_id = QXL_SAVE_VERSION,
2206 .fields = (VMStateField[]) {
2207 VMSTATE_UINT32(width, QXLSurfaceCreate),
2208 VMSTATE_UINT32(height, QXLSurfaceCreate),
2209 VMSTATE_INT32(stride, QXLSurfaceCreate),
2210 VMSTATE_UINT32(format, QXLSurfaceCreate),
2211 VMSTATE_UINT32(position, QXLSurfaceCreate),
2212 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2213 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2214 VMSTATE_UINT32(type, QXLSurfaceCreate),
2215 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2216 VMSTATE_END_OF_LIST()
2217 }
2218};
2219
2220static VMStateDescription qxl_vmstate_monitors_config = {
2221 .name = "qxl/monitors-config",
2222 .version_id = 1,
2223 .minimum_version_id = 1,
2224 .fields = (VMStateField[]) {
2225 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2226 VMSTATE_END_OF_LIST()
2227 },
2228};
2229
2230static VMStateDescription qxl_vmstate = {
2231 .name = "qxl",
2232 .version_id = QXL_SAVE_VERSION,
2233 .minimum_version_id = QXL_SAVE_VERSION,
2234 .pre_save = qxl_pre_save,
2235 .pre_load = qxl_pre_load,
2236 .post_load = qxl_post_load,
2237 .fields = (VMStateField[]) {
2238 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2239 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2240 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2241 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2242 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2243 VMSTATE_UINT32(mode, PCIQXLDevice),
2244 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2245 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2246 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2247 qxl_memslot, struct guest_slots),
2248 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2249 qxl_surface, QXLSurfaceCreate),
2250 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2251 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2252 ssd.num_surfaces, 0,
2253 vmstate_info_uint64, uint64_t),
2254 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2255 VMSTATE_END_OF_LIST()
2256 },
2257 .subsections = (VMStateSubsection[]) {
2258 {
2259 .vmsd = &qxl_vmstate_monitors_config,
2260 .needed = qxl_monitors_config_needed,
2261 }, {
2262
2263 }
2264 }
2265};
2266
2267static Property qxl_properties[] = {
2268 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2269 64 * 1024 * 1024),
2270 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
2271 64 * 1024 * 1024),
2272 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2273 QXL_DEFAULT_REVISION),
2274 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2275 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2276 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2277 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2278 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2279 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2280 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2281 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2282 DEFINE_PROP_END_OF_LIST(),
2283};
2284
2285static void qxl_primary_class_init(ObjectClass *klass, void *data)
2286{
2287 DeviceClass *dc = DEVICE_CLASS(klass);
2288 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2289
2290 k->init = qxl_init_primary;
2291 k->romfile = "vgabios-qxl.bin";
2292 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2293 k->device_id = QXL_DEVICE_ID_STABLE;
2294 k->class_id = PCI_CLASS_DISPLAY_VGA;
2295 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2296 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2297 dc->reset = qxl_reset_handler;
2298 dc->vmsd = &qxl_vmstate;
2299 dc->props = qxl_properties;
2300 dc->hotpluggable = false;
2301}
2302
2303static const TypeInfo qxl_primary_info = {
2304 .name = "qxl-vga",
2305 .parent = TYPE_PCI_DEVICE,
2306 .instance_size = sizeof(PCIQXLDevice),
2307 .class_init = qxl_primary_class_init,
2308};
2309
2310static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2311{
2312 DeviceClass *dc = DEVICE_CLASS(klass);
2313 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2314
2315 k->init = qxl_init_secondary;
2316 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2317 k->device_id = QXL_DEVICE_ID_STABLE;
2318 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2319 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2320 dc->desc = "Spice QXL GPU (secondary)";
2321 dc->reset = qxl_reset_handler;
2322 dc->vmsd = &qxl_vmstate;
2323 dc->props = qxl_properties;
2324}
2325
2326static const TypeInfo qxl_secondary_info = {
2327 .name = "qxl",
2328 .parent = TYPE_PCI_DEVICE,
2329 .instance_size = sizeof(PCIQXLDevice),
2330 .class_init = qxl_secondary_class_init,
2331};
2332
2333static void qxl_register_types(void)
2334{
2335 type_register_static(&qxl_primary_info);
2336 type_register_static(&qxl_secondary_info);
2337}
2338
2339type_init(qxl_register_types)
2340