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31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec/exec-all.h"
35#include "disas/disas.h"
36#include "tcg-op.h"
37#include "qemu/log.h"
38#include "sysemu/sysemu.h"
39#include "exec/cpu_ldst.h"
40
41#include "exec/helper-proto.h"
42#include "exec/helper-gen.h"
43
44#include "trace-tcg.h"
45
46
47typedef struct DisasContext {
48 const XtensaConfig *config;
49 TranslationBlock *tb;
50 uint32_t pc;
51 uint32_t next_pc;
52 int cring;
53 int ring;
54 uint32_t lbeg;
55 uint32_t lend;
56 TCGv_i32 litbase;
57 int is_jmp;
58 int singlestep_enabled;
59
60 bool sar_5bit;
61 bool sar_m32_5bit;
62 bool sar_m32_allocated;
63 TCGv_i32 sar_m32;
64
65 uint32_t ccount_delta;
66 unsigned used_window;
67
68 bool debug;
69 bool icount;
70 TCGv_i32 next_icount;
71
72 unsigned cpenable;
73} DisasContext;
74
75static TCGv_ptr cpu_env;
76static TCGv_i32 cpu_pc;
77static TCGv_i32 cpu_R[16];
78static TCGv_i32 cpu_FR[16];
79static TCGv_i32 cpu_SR[256];
80static TCGv_i32 cpu_UR[256];
81
82#include "exec/gen-icount.h"
83
84typedef struct XtensaReg {
85 const char *name;
86 uint64_t opt_bits;
87 enum {
88 SR_R = 1,
89 SR_W = 2,
90 SR_X = 4,
91 SR_RW = 3,
92 SR_RWX = 7,
93 } access;
94} XtensaReg;
95
96#define XTENSA_REG_ACCESS(regname, opt, acc) { \
97 .name = (regname), \
98 .opt_bits = XTENSA_OPTION_BIT(opt), \
99 .access = (acc), \
100 }
101
102#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
103
104#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
105 .name = (regname), \
106 .opt_bits = (opt), \
107 .access = (acc), \
108 }
109
110#define XTENSA_REG_BITS(regname, opt) \
111 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
112
113static const XtensaReg sregnames[256] = {
114 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
115 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
116 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
117 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
118 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
119 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
120 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
121 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
122 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
123 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
124 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
125 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
126 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
127 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
128 [WINDOW_START] = XTENSA_REG("WINDOW_START",
129 XTENSA_OPTION_WINDOWED_REGISTER),
130 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
131 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
132 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
133 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
134 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
135 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
136 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
137 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
138 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
139 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
140 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
141 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
142 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
143 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
144 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
145 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
146 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
152 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
153 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
159 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
160 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
161 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
162 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
163 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
164 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
165 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
166 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
168 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
169 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
170 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
172 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
173 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
174 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
175 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
176 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
177 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
178 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
179 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
180 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
181 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
182 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
183 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
184 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
185 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
186 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
187 XTENSA_OPTION_TIMER_INTERRUPT),
188 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
189 XTENSA_OPTION_TIMER_INTERRUPT),
190 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
191 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
192 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
193 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
194};
195
196static const XtensaReg uregnames[256] = {
197 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
198 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
199 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
200};
201
202void xtensa_translate_init(void)
203{
204 static const char * const regnames[] = {
205 "ar0", "ar1", "ar2", "ar3",
206 "ar4", "ar5", "ar6", "ar7",
207 "ar8", "ar9", "ar10", "ar11",
208 "ar12", "ar13", "ar14", "ar15",
209 };
210 static const char * const fregnames[] = {
211 "f0", "f1", "f2", "f3",
212 "f4", "f5", "f6", "f7",
213 "f8", "f9", "f10", "f11",
214 "f12", "f13", "f14", "f15",
215 };
216 int i;
217
218 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
219 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
220 offsetof(CPUXtensaState, pc), "pc");
221
222 for (i = 0; i < 16; i++) {
223 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
224 offsetof(CPUXtensaState, regs[i]),
225 regnames[i]);
226 }
227
228 for (i = 0; i < 16; i++) {
229 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
230 offsetof(CPUXtensaState, fregs[i]),
231 fregnames[i]);
232 }
233
234 for (i = 0; i < 256; ++i) {
235 if (sregnames[i].name) {
236 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
237 offsetof(CPUXtensaState, sregs[i]),
238 sregnames[i].name);
239 }
240 }
241
242 for (i = 0; i < 256; ++i) {
243 if (uregnames[i].name) {
244 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
245 offsetof(CPUXtensaState, uregs[i]),
246 uregnames[i].name);
247 }
248 }
249}
250
251static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
252{
253 return xtensa_option_bits_enabled(dc->config, opt);
254}
255
256static inline bool option_enabled(DisasContext *dc, int opt)
257{
258 return xtensa_option_enabled(dc->config, opt);
259}
260
261static void init_litbase(DisasContext *dc)
262{
263 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
264 dc->litbase = tcg_temp_local_new_i32();
265 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
266 }
267}
268
269static void reset_litbase(DisasContext *dc)
270{
271 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
272 tcg_temp_free(dc->litbase);
273 }
274}
275
276static void init_sar_tracker(DisasContext *dc)
277{
278 dc->sar_5bit = false;
279 dc->sar_m32_5bit = false;
280 dc->sar_m32_allocated = false;
281}
282
283static void reset_sar_tracker(DisasContext *dc)
284{
285 if (dc->sar_m32_allocated) {
286 tcg_temp_free(dc->sar_m32);
287 }
288}
289
290static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
291{
292 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
293 if (dc->sar_m32_5bit) {
294 tcg_gen_discard_i32(dc->sar_m32);
295 }
296 dc->sar_5bit = true;
297 dc->sar_m32_5bit = false;
298}
299
300static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
301{
302 TCGv_i32 tmp = tcg_const_i32(32);
303 if (!dc->sar_m32_allocated) {
304 dc->sar_m32 = tcg_temp_local_new_i32();
305 dc->sar_m32_allocated = true;
306 }
307 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
308 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
309 dc->sar_5bit = false;
310 dc->sar_m32_5bit = true;
311 tcg_temp_free(tmp);
312}
313
314static void gen_advance_ccount_cond(DisasContext *dc)
315{
316 if (dc->ccount_delta > 0) {
317 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
318 gen_helper_advance_ccount(cpu_env, tmp);
319 tcg_temp_free(tmp);
320 }
321}
322
323static void gen_advance_ccount(DisasContext *dc)
324{
325 gen_advance_ccount_cond(dc);
326 dc->ccount_delta = 0;
327}
328
329static void reset_used_window(DisasContext *dc)
330{
331 dc->used_window = 0;
332}
333
334static void gen_exception(DisasContext *dc, int excp)
335{
336 TCGv_i32 tmp = tcg_const_i32(excp);
337 gen_advance_ccount(dc);
338 gen_helper_exception(cpu_env, tmp);
339 tcg_temp_free(tmp);
340}
341
342static void gen_exception_cause(DisasContext *dc, uint32_t cause)
343{
344 TCGv_i32 tpc = tcg_const_i32(dc->pc);
345 TCGv_i32 tcause = tcg_const_i32(cause);
346 gen_advance_ccount(dc);
347 gen_helper_exception_cause(cpu_env, tpc, tcause);
348 tcg_temp_free(tpc);
349 tcg_temp_free(tcause);
350 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
351 cause == SYSCALL_CAUSE) {
352 dc->is_jmp = DISAS_UPDATE;
353 }
354}
355
356static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
357 TCGv_i32 vaddr)
358{
359 TCGv_i32 tpc = tcg_const_i32(dc->pc);
360 TCGv_i32 tcause = tcg_const_i32(cause);
361 gen_advance_ccount(dc);
362 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
363 tcg_temp_free(tpc);
364 tcg_temp_free(tcause);
365}
366
367static void gen_debug_exception(DisasContext *dc, uint32_t cause)
368{
369 TCGv_i32 tpc = tcg_const_i32(dc->pc);
370 TCGv_i32 tcause = tcg_const_i32(cause);
371 gen_advance_ccount(dc);
372 gen_helper_debug_exception(cpu_env, tpc, tcause);
373 tcg_temp_free(tpc);
374 tcg_temp_free(tcause);
375 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
376 dc->is_jmp = DISAS_UPDATE;
377 }
378}
379
380static void gen_check_privilege(DisasContext *dc)
381{
382 if (dc->cring) {
383 gen_exception_cause(dc, PRIVILEGED_CAUSE);
384 dc->is_jmp = DISAS_UPDATE;
385 }
386}
387
388static void gen_check_cpenable(DisasContext *dc, unsigned cp)
389{
390 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
391 !(dc->cpenable & (1 << cp))) {
392 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
393 dc->is_jmp = DISAS_UPDATE;
394 }
395}
396
397static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
398{
399 tcg_gen_mov_i32(cpu_pc, dest);
400 gen_advance_ccount(dc);
401 if (dc->icount) {
402 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
403 }
404 if (dc->singlestep_enabled) {
405 gen_exception(dc, EXCP_DEBUG);
406 } else {
407 if (slot >= 0) {
408 tcg_gen_goto_tb(slot);
409 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
410 } else {
411 tcg_gen_exit_tb(0);
412 }
413 }
414 dc->is_jmp = DISAS_UPDATE;
415}
416
417static void gen_jump(DisasContext *dc, TCGv dest)
418{
419 gen_jump_slot(dc, dest, -1);
420}
421
422static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
423{
424 TCGv_i32 tmp = tcg_const_i32(dest);
425 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
426 slot = -1;
427 }
428 gen_jump_slot(dc, tmp, slot);
429 tcg_temp_free(tmp);
430}
431
432static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
433 int slot)
434{
435 TCGv_i32 tcallinc = tcg_const_i32(callinc);
436
437 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
438 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
439 tcg_temp_free(tcallinc);
440 tcg_gen_movi_i32(cpu_R[callinc << 2],
441 (callinc << 30) | (dc->next_pc & 0x3fffffff));
442 gen_jump_slot(dc, dest, slot);
443}
444
445static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
446{
447 gen_callw_slot(dc, callinc, dest, -1);
448}
449
450static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
451{
452 TCGv_i32 tmp = tcg_const_i32(dest);
453 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
454 slot = -1;
455 }
456 gen_callw_slot(dc, callinc, tmp, slot);
457 tcg_temp_free(tmp);
458}
459
460static bool gen_check_loop_end(DisasContext *dc, int slot)
461{
462 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
463 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
464 dc->next_pc == dc->lend) {
465 int label = gen_new_label();
466
467 gen_advance_ccount(dc);
468 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
469 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
470 gen_jumpi(dc, dc->lbeg, slot);
471 gen_set_label(label);
472 gen_jumpi(dc, dc->next_pc, -1);
473 return true;
474 }
475 return false;
476}
477
478static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
479{
480 if (!gen_check_loop_end(dc, slot)) {
481 gen_jumpi(dc, dc->next_pc, slot);
482 }
483}
484
485static void gen_brcond(DisasContext *dc, TCGCond cond,
486 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
487{
488 int label = gen_new_label();
489
490 gen_advance_ccount(dc);
491 tcg_gen_brcond_i32(cond, t0, t1, label);
492 gen_jumpi_check_loop_end(dc, 0);
493 gen_set_label(label);
494 gen_jumpi(dc, dc->pc + offset, 1);
495}
496
497static void gen_brcondi(DisasContext *dc, TCGCond cond,
498 TCGv_i32 t0, uint32_t t1, uint32_t offset)
499{
500 TCGv_i32 tmp = tcg_const_i32(t1);
501 gen_brcond(dc, cond, t0, tmp, offset);
502 tcg_temp_free(tmp);
503}
504
505static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
506{
507 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
508 if (sregnames[sr].name) {
509 qemu_log("SR %s is not configured\n", sregnames[sr].name);
510 } else {
511 qemu_log("SR %d is not implemented\n", sr);
512 }
513 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
514 return false;
515 } else if (!(sregnames[sr].access & access)) {
516 static const char * const access_text[] = {
517 [SR_R] = "rsr",
518 [SR_W] = "wsr",
519 [SR_X] = "xsr",
520 };
521 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
522 qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
523 access_text[access]);
524 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
525 return false;
526 }
527 return true;
528}
529
530static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
531{
532 gen_advance_ccount(dc);
533 tcg_gen_mov_i32(d, cpu_SR[sr]);
534}
535
536static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
537{
538 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
539 tcg_gen_or_i32(d, d, cpu_SR[sr]);
540 tcg_gen_andi_i32(d, d, 0xfffffffc);
541}
542
543static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
544{
545 static void (* const rsr_handler[256])(DisasContext *dc,
546 TCGv_i32 d, uint32_t sr) = {
547 [CCOUNT] = gen_rsr_ccount,
548 [PTEVADDR] = gen_rsr_ptevaddr,
549 };
550
551 if (rsr_handler[sr]) {
552 rsr_handler[sr](dc, d, sr);
553 } else {
554 tcg_gen_mov_i32(d, cpu_SR[sr]);
555 }
556}
557
558static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
559{
560 gen_helper_wsr_lbeg(cpu_env, s);
561 gen_jumpi_check_loop_end(dc, 0);
562}
563
564static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
565{
566 gen_helper_wsr_lend(cpu_env, s);
567 gen_jumpi_check_loop_end(dc, 0);
568}
569
570static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
571{
572 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
573 if (dc->sar_m32_5bit) {
574 tcg_gen_discard_i32(dc->sar_m32);
575 }
576 dc->sar_5bit = false;
577 dc->sar_m32_5bit = false;
578}
579
580static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
581{
582 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
583}
584
585static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
586{
587 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
588
589 gen_jumpi_check_loop_end(dc, -1);
590}
591
592static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
593{
594 tcg_gen_ext8s_i32(cpu_SR[sr], s);
595}
596
597static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
598{
599 gen_helper_wsr_windowbase(cpu_env, v);
600 reset_used_window(dc);
601}
602
603static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
604{
605 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
606 reset_used_window(dc);
607}
608
609static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
610{
611 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
612}
613
614static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
615{
616 gen_helper_wsr_rasid(cpu_env, v);
617
618 gen_jumpi_check_loop_end(dc, -1);
619}
620
621static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
622{
623 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
624}
625
626static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
627{
628 gen_helper_wsr_ibreakenable(cpu_env, v);
629 gen_jumpi_check_loop_end(dc, 0);
630}
631
632static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
633{
634 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
635}
636
637static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
638{
639 unsigned id = sr - IBREAKA;
640
641 if (id < dc->config->nibreak) {
642 TCGv_i32 tmp = tcg_const_i32(id);
643 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
644 tcg_temp_free(tmp);
645 gen_jumpi_check_loop_end(dc, 0);
646 }
647}
648
649static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
650{
651 unsigned id = sr - DBREAKA;
652
653 if (id < dc->config->ndbreak) {
654 TCGv_i32 tmp = tcg_const_i32(id);
655 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
656 tcg_temp_free(tmp);
657 }
658}
659
660static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
661{
662 unsigned id = sr - DBREAKC;
663
664 if (id < dc->config->ndbreak) {
665 TCGv_i32 tmp = tcg_const_i32(id);
666 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
667 tcg_temp_free(tmp);
668 }
669}
670
671static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
672{
673 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
674
675 gen_jumpi_check_loop_end(dc, -1);
676}
677
678static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
679{
680 tcg_gen_andi_i32(cpu_SR[sr], v,
681 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
682 gen_helper_check_interrupts(cpu_env);
683 gen_jumpi_check_loop_end(dc, 0);
684}
685
686static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
687{
688 TCGv_i32 tmp = tcg_temp_new_i32();
689
690 tcg_gen_andi_i32(tmp, v,
691 dc->config->inttype_mask[INTTYPE_EDGE] |
692 dc->config->inttype_mask[INTTYPE_NMI] |
693 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
694 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
695 tcg_temp_free(tmp);
696 gen_helper_check_interrupts(cpu_env);
697}
698
699static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
700{
701 tcg_gen_mov_i32(cpu_SR[sr], v);
702 gen_helper_check_interrupts(cpu_env);
703 gen_jumpi_check_loop_end(dc, 0);
704}
705
706static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
707{
708 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
709 PS_UM | PS_EXCM | PS_INTLEVEL;
710
711 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
712 mask |= PS_RING;
713 }
714 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
715 reset_used_window(dc);
716 gen_helper_check_interrupts(cpu_env);
717
718 gen_jumpi_check_loop_end(dc, -1);
719}
720
721static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
722{
723 if (dc->icount) {
724 tcg_gen_mov_i32(dc->next_icount, v);
725 } else {
726 tcg_gen_mov_i32(cpu_SR[sr], v);
727 }
728}
729
730static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
731{
732 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
733
734 gen_jumpi_check_loop_end(dc, -1);
735}
736
737static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
738{
739 uint32_t id = sr - CCOMPARE;
740 if (id < dc->config->nccompare) {
741 uint32_t int_bit = 1 << dc->config->timerint[id];
742 gen_advance_ccount(dc);
743 tcg_gen_mov_i32(cpu_SR[sr], v);
744 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
745 gen_helper_check_interrupts(cpu_env);
746 }
747}
748
749static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
750{
751 static void (* const wsr_handler[256])(DisasContext *dc,
752 uint32_t sr, TCGv_i32 v) = {
753 [LBEG] = gen_wsr_lbeg,
754 [LEND] = gen_wsr_lend,
755 [SAR] = gen_wsr_sar,
756 [BR] = gen_wsr_br,
757 [LITBASE] = gen_wsr_litbase,
758 [ACCHI] = gen_wsr_acchi,
759 [WINDOW_BASE] = gen_wsr_windowbase,
760 [WINDOW_START] = gen_wsr_windowstart,
761 [PTEVADDR] = gen_wsr_ptevaddr,
762 [RASID] = gen_wsr_rasid,
763 [ITLBCFG] = gen_wsr_tlbcfg,
764 [DTLBCFG] = gen_wsr_tlbcfg,
765 [IBREAKENABLE] = gen_wsr_ibreakenable,
766 [ATOMCTL] = gen_wsr_atomctl,
767 [IBREAKA] = gen_wsr_ibreaka,
768 [IBREAKA + 1] = gen_wsr_ibreaka,
769 [DBREAKA] = gen_wsr_dbreaka,
770 [DBREAKA + 1] = gen_wsr_dbreaka,
771 [DBREAKC] = gen_wsr_dbreakc,
772 [DBREAKC + 1] = gen_wsr_dbreakc,
773 [CPENABLE] = gen_wsr_cpenable,
774 [INTSET] = gen_wsr_intset,
775 [INTCLEAR] = gen_wsr_intclear,
776 [INTENABLE] = gen_wsr_intenable,
777 [PS] = gen_wsr_ps,
778 [ICOUNT] = gen_wsr_icount,
779 [ICOUNTLEVEL] = gen_wsr_icountlevel,
780 [CCOMPARE] = gen_wsr_ccompare,
781 [CCOMPARE + 1] = gen_wsr_ccompare,
782 [CCOMPARE + 2] = gen_wsr_ccompare,
783 };
784
785 if (wsr_handler[sr]) {
786 wsr_handler[sr](dc, sr, s);
787 } else {
788 tcg_gen_mov_i32(cpu_SR[sr], s);
789 }
790}
791
792static void gen_wur(uint32_t ur, TCGv_i32 s)
793{
794 switch (ur) {
795 case FCR:
796 gen_helper_wur_fcr(cpu_env, s);
797 break;
798
799 case FSR:
800 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
801 break;
802
803 default:
804 tcg_gen_mov_i32(cpu_UR[ur], s);
805 break;
806 }
807}
808
809static void gen_load_store_alignment(DisasContext *dc, int shift,
810 TCGv_i32 addr, bool no_hw_alignment)
811{
812 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
813 tcg_gen_andi_i32(addr, addr, ~0 << shift);
814 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
815 no_hw_alignment) {
816 int label = gen_new_label();
817 TCGv_i32 tmp = tcg_temp_new_i32();
818 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
819 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
820 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
821 gen_set_label(label);
822 tcg_temp_free(tmp);
823 }
824}
825
826static void gen_waiti(DisasContext *dc, uint32_t imm4)
827{
828 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
829 TCGv_i32 intlevel = tcg_const_i32(imm4);
830 gen_advance_ccount(dc);
831 gen_helper_waiti(cpu_env, pc, intlevel);
832 tcg_temp_free(pc);
833 tcg_temp_free(intlevel);
834}
835
836static void gen_window_check1(DisasContext *dc, unsigned r1)
837{
838 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
839 return;
840 }
841 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
842 r1 / 4 > dc->used_window) {
843 int label = gen_new_label();
844 TCGv_i32 ws = tcg_temp_new_i32();
845
846 dc->used_window = r1 / 4;
847 tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START],
848 dc->config->nareg / 4, dc->config->nareg / 4);
849 tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]);
850 tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2);
851 tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label);
852 {
853 TCGv_i32 pc = tcg_const_i32(dc->pc);
854 TCGv_i32 w = tcg_const_i32(r1 / 4);
855
856 gen_advance_ccount_cond(dc);
857 gen_helper_window_check(cpu_env, pc, w);
858
859 tcg_temp_free(w);
860 tcg_temp_free(pc);
861 }
862 gen_set_label(label);
863 tcg_temp_free(ws);
864 }
865}
866
867static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
868{
869 gen_window_check1(dc, r1 > r2 ? r1 : r2);
870}
871
872static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
873 unsigned r3)
874{
875 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
876}
877
878static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
879{
880 TCGv_i32 m = tcg_temp_new_i32();
881
882 if (hi) {
883 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
884 } else {
885 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
886 }
887 return m;
888}
889
890static inline unsigned xtensa_op0_insn_len(unsigned op0)
891{
892 return op0 >= 8 ? 2 : 3;
893}
894
895static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
896{
897#define HAS_OPTION_BITS(opt) do { \
898 if (!option_bits_enabled(dc, opt)) { \
899 qemu_log("Option is not enabled %s:%d\n", \
900 __FILE__, __LINE__); \
901 goto invalid_opcode; \
902 } \
903 } while (0)
904
905#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
906
907#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
908#define RESERVED() do { \
909 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
910 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
911 goto invalid_opcode; \
912 } while (0)
913
914
915#ifdef TARGET_WORDS_BIGENDIAN
916#define OP0 (((b0) & 0xf0) >> 4)
917#define OP1 (((b2) & 0xf0) >> 4)
918#define OP2 ((b2) & 0xf)
919#define RRR_R ((b1) & 0xf)
920#define RRR_S (((b1) & 0xf0) >> 4)
921#define RRR_T ((b0) & 0xf)
922#else
923#define OP0 (((b0) & 0xf))
924#define OP1 (((b2) & 0xf))
925#define OP2 (((b2) & 0xf0) >> 4)
926#define RRR_R (((b1) & 0xf0) >> 4)
927#define RRR_S (((b1) & 0xf))
928#define RRR_T (((b0) & 0xf0) >> 4)
929#endif
930#define RRR_X ((RRR_R & 0x4) >> 2)
931#define RRR_Y ((RRR_T & 0x4) >> 2)
932#define RRR_W (RRR_R & 0x3)
933
934#define RRRN_R RRR_R
935#define RRRN_S RRR_S
936#define RRRN_T RRR_T
937
938#define RRI4_R RRR_R
939#define RRI4_S RRR_S
940#define RRI4_T RRR_T
941#ifdef TARGET_WORDS_BIGENDIAN
942#define RRI4_IMM4 ((b2) & 0xf)
943#else
944#define RRI4_IMM4 (((b2) & 0xf0) >> 4)
945#endif
946
947#define RRI8_R RRR_R
948#define RRI8_S RRR_S
949#define RRI8_T RRR_T
950#define RRI8_IMM8 (b2)
951#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
952
953#ifdef TARGET_WORDS_BIGENDIAN
954#define RI16_IMM16 (((b1) << 8) | (b2))
955#else
956#define RI16_IMM16 (((b2) << 8) | (b1))
957#endif
958
959#ifdef TARGET_WORDS_BIGENDIAN
960#define CALL_N (((b0) & 0xc) >> 2)
961#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
962#else
963#define CALL_N (((b0) & 0x30) >> 4)
964#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
965#endif
966#define CALL_OFFSET_SE \
967 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
968
969#define CALLX_N CALL_N
970#ifdef TARGET_WORDS_BIGENDIAN
971#define CALLX_M ((b0) & 0x3)
972#else
973#define CALLX_M (((b0) & 0xc0) >> 6)
974#endif
975#define CALLX_S RRR_S
976
977#define BRI12_M CALLX_M
978#define BRI12_S RRR_S
979#ifdef TARGET_WORDS_BIGENDIAN
980#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
981#else
982#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
983#endif
984#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
985
986#define BRI8_M BRI12_M
987#define BRI8_R RRI8_R
988#define BRI8_S RRI8_S
989#define BRI8_IMM8 RRI8_IMM8
990#define BRI8_IMM8_SE RRI8_IMM8_SE
991
992#define RSR_SR (b1)
993
994 uint8_t b0 = cpu_ldub_code(env, dc->pc);
995 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
996 uint8_t b2 = 0;
997 unsigned len = xtensa_op0_insn_len(OP0);
998
999 static const uint32_t B4CONST[] = {
1000 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1001 };
1002
1003 static const uint32_t B4CONSTU[] = {
1004 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1005 };
1006
1007 switch (len) {
1008 case 2:
1009 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
1010 break;
1011
1012 case 3:
1013 b2 = cpu_ldub_code(env, dc->pc + 2);
1014 break;
1015
1016 default:
1017 RESERVED();
1018 }
1019 dc->next_pc = dc->pc + len;
1020
1021 switch (OP0) {
1022 case 0:
1023 switch (OP1) {
1024 case 0:
1025 switch (OP2) {
1026 case 0:
1027 if ((RRR_R & 0xc) == 0x8) {
1028 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1029 }
1030
1031 switch (RRR_R) {
1032 case 0:
1033 switch (CALLX_M) {
1034 case 0:
1035 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1036 break;
1037
1038 case 1:
1039 RESERVED();
1040 break;
1041
1042 case 2:
1043 switch (CALLX_N) {
1044 case 0:
1045 case 2:
1046 gen_window_check1(dc, CALLX_S);
1047 gen_jump(dc, cpu_R[CALLX_S]);
1048 break;
1049
1050 case 1:
1051 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1052 {
1053 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1054 gen_advance_ccount(dc);
1055 gen_helper_retw(tmp, cpu_env, tmp);
1056 gen_jump(dc, tmp);
1057 tcg_temp_free(tmp);
1058 }
1059 break;
1060
1061 case 3:
1062 RESERVED();
1063 break;
1064 }
1065 break;
1066
1067 case 3:
1068 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
1069 switch (CALLX_N) {
1070 case 0:
1071 {
1072 TCGv_i32 tmp = tcg_temp_new_i32();
1073 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1074 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1075 gen_jump(dc, tmp);
1076 tcg_temp_free(tmp);
1077 }
1078 break;
1079
1080 case 1:
1081 case 2:
1082 case 3:
1083 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1084 {
1085 TCGv_i32 tmp = tcg_temp_new_i32();
1086
1087 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1088 gen_callw(dc, CALLX_N, tmp);
1089 tcg_temp_free(tmp);
1090 }
1091 break;
1092 }
1093 break;
1094 }
1095 break;
1096
1097 case 1:
1098 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1099 gen_window_check2(dc, RRR_T, RRR_S);
1100 {
1101 TCGv_i32 pc = tcg_const_i32(dc->pc);
1102 gen_advance_ccount(dc);
1103 gen_helper_movsp(cpu_env, pc);
1104 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1105 tcg_temp_free(pc);
1106 }
1107 break;
1108
1109 case 2:
1110 switch (RRR_T) {
1111 case 0:
1112 break;
1113
1114 case 1:
1115 break;
1116
1117 case 2:
1118 break;
1119
1120 case 3:
1121 break;
1122
1123 case 8:
1124 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1125 break;
1126
1127 case 12:
1128 break;
1129
1130 case 13:
1131 break;
1132
1133 case 15:
1134 break;
1135
1136 default:
1137 RESERVED();
1138 break;
1139 }
1140 break;
1141
1142 case 3:
1143 switch (RRR_T) {
1144 case 0:
1145 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1146 switch (RRR_S) {
1147 case 0:
1148 gen_check_privilege(dc);
1149 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1150 gen_helper_check_interrupts(cpu_env);
1151 gen_jump(dc, cpu_SR[EPC1]);
1152 break;
1153
1154 case 1:
1155 RESERVED();
1156 break;
1157
1158 case 2:
1159 gen_check_privilege(dc);
1160 gen_jump(dc, cpu_SR[
1161 dc->config->ndepc ? DEPC : EPC1]);
1162 break;
1163
1164 case 4:
1165 case 5:
1166 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1167 gen_check_privilege(dc);
1168 {
1169 TCGv_i32 tmp = tcg_const_i32(1);
1170
1171 tcg_gen_andi_i32(
1172 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1173 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1174
1175 if (RRR_S == 4) {
1176 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1177 cpu_SR[WINDOW_START], tmp);
1178 } else {
1179 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1180 cpu_SR[WINDOW_START], tmp);
1181 }
1182
1183 gen_helper_restore_owb(cpu_env);
1184 gen_helper_check_interrupts(cpu_env);
1185 gen_jump(dc, cpu_SR[EPC1]);
1186
1187 tcg_temp_free(tmp);
1188 }
1189 break;
1190
1191 default:
1192 RESERVED();
1193 break;
1194 }
1195 break;
1196
1197 case 1:
1198 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1199 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1200 gen_check_privilege(dc);
1201 tcg_gen_mov_i32(cpu_SR[PS],
1202 cpu_SR[EPS2 + RRR_S - 2]);
1203 gen_helper_check_interrupts(cpu_env);
1204 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1205 } else {
1206 qemu_log("RFI %d is illegal\n", RRR_S);
1207 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1208 }
1209 break;
1210
1211 case 2:
1212 TBD();
1213 break;
1214
1215 default:
1216 RESERVED();
1217 break;
1218
1219 }
1220 break;
1221
1222 case 4:
1223 HAS_OPTION(XTENSA_OPTION_DEBUG);
1224 if (dc->debug) {
1225 gen_debug_exception(dc, DEBUGCAUSE_BI);
1226 }
1227 break;
1228
1229 case 5:
1230 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1231 switch (RRR_S) {
1232 case 0:
1233 gen_exception_cause(dc, SYSCALL_CAUSE);
1234 break;
1235
1236 case 1:
1237 if (semihosting_enabled) {
1238 gen_check_privilege(dc);
1239 gen_helper_simcall(cpu_env);
1240 } else {
1241 qemu_log("SIMCALL but semihosting is disabled\n");
1242 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1243 }
1244 break;
1245
1246 default:
1247 RESERVED();
1248 break;
1249 }
1250 break;
1251
1252 case 6:
1253 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1254 gen_check_privilege(dc);
1255 gen_window_check1(dc, RRR_T);
1256 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1257 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1258 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1259 gen_helper_check_interrupts(cpu_env);
1260 gen_jumpi_check_loop_end(dc, 0);
1261 break;
1262
1263 case 7:
1264 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1265 gen_check_privilege(dc);
1266 gen_waiti(dc, RRR_S);
1267 break;
1268
1269 case 8:
1270 case 9:
1271 case 10:
1272 case 11:
1273 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1274 {
1275 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1276 TCGv_i32 mask = tcg_const_i32(
1277 ((1 << shift) - 1) << RRR_S);
1278 TCGv_i32 tmp = tcg_temp_new_i32();
1279
1280 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1281 if (RRR_R & 1) {
1282 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1283 } else {
1284 tcg_gen_add_i32(tmp, tmp, mask);
1285 }
1286 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1287 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1288 tmp, RRR_T, 1);
1289 tcg_temp_free(mask);
1290 tcg_temp_free(tmp);
1291 }
1292 break;
1293
1294 default:
1295 RESERVED();
1296 break;
1297
1298 }
1299 break;
1300
1301 case 1:
1302 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1303 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1304 break;
1305
1306 case 2:
1307 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1308 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1309 break;
1310
1311 case 3:
1312 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1313 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1314 break;
1315
1316 case 4:
1317 switch (RRR_R) {
1318 case 0:
1319 gen_window_check1(dc, RRR_S);
1320 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1321 break;
1322
1323 case 1:
1324 gen_window_check1(dc, RRR_S);
1325 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1326 break;
1327
1328 case 2:
1329 gen_window_check1(dc, RRR_S);
1330 {
1331 TCGv_i32 tmp = tcg_temp_new_i32();
1332 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1333 gen_right_shift_sar(dc, tmp);
1334 tcg_temp_free(tmp);
1335 }
1336 break;
1337
1338 case 3:
1339 gen_window_check1(dc, RRR_S);
1340 {
1341 TCGv_i32 tmp = tcg_temp_new_i32();
1342 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1343 gen_left_shift_sar(dc, tmp);
1344 tcg_temp_free(tmp);
1345 }
1346 break;
1347
1348 case 4:
1349 {
1350 TCGv_i32 tmp = tcg_const_i32(
1351 RRR_S | ((RRR_T & 1) << 4));
1352 gen_right_shift_sar(dc, tmp);
1353 tcg_temp_free(tmp);
1354 }
1355 break;
1356
1357 case 6:
1358 TBD();
1359 break;
1360
1361 case 7:
1362 TBD();
1363 break;
1364
1365 case 8:
1366 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1367 gen_check_privilege(dc);
1368 {
1369 TCGv_i32 tmp = tcg_const_i32(
1370 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1371 gen_helper_rotw(cpu_env, tmp);
1372 tcg_temp_free(tmp);
1373 reset_used_window(dc);
1374 }
1375 break;
1376
1377 case 14:
1378 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1379 gen_window_check2(dc, RRR_S, RRR_T);
1380 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1381 break;
1382
1383 case 15:
1384 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1385 gen_window_check2(dc, RRR_S, RRR_T);
1386 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1387 break;
1388
1389 default:
1390 RESERVED();
1391 break;
1392 }
1393 break;
1394
1395 case 5:
1396 HAS_OPTION_BITS(
1397 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1398 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1399 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1400 gen_check_privilege(dc);
1401 gen_window_check2(dc, RRR_S, RRR_T);
1402 {
1403 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1404
1405 switch (RRR_R & 7) {
1406 case 3:
1407 gen_helper_rtlb0(cpu_R[RRR_T],
1408 cpu_env, cpu_R[RRR_S], dtlb);
1409 break;
1410
1411 case 4:
1412 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1413
1414 gen_jumpi_check_loop_end(dc, -1);
1415 break;
1416
1417 case 5:
1418 tcg_gen_movi_i32(cpu_pc, dc->pc);
1419 gen_helper_ptlb(cpu_R[RRR_T],
1420 cpu_env, cpu_R[RRR_S], dtlb);
1421 break;
1422
1423 case 6:
1424 gen_helper_wtlb(
1425 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1426
1427 gen_jumpi_check_loop_end(dc, -1);
1428 break;
1429
1430 case 7:
1431 gen_helper_rtlb1(cpu_R[RRR_T],
1432 cpu_env, cpu_R[RRR_S], dtlb);
1433 break;
1434
1435 default:
1436 tcg_temp_free(dtlb);
1437 RESERVED();
1438 break;
1439 }
1440 tcg_temp_free(dtlb);
1441 }
1442 break;
1443
1444 case 6:
1445 gen_window_check2(dc, RRR_R, RRR_T);
1446 switch (RRR_S) {
1447 case 0:
1448 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1449 break;
1450
1451 case 1:
1452 {
1453 TCGv_i32 zero = tcg_const_i32(0);
1454 TCGv_i32 neg = tcg_temp_new_i32();
1455
1456 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1457 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1458 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1459 tcg_temp_free(neg);
1460 tcg_temp_free(zero);
1461 }
1462 break;
1463
1464 default:
1465 RESERVED();
1466 break;
1467 }
1468 break;
1469
1470 case 7:
1471 RESERVED();
1472 break;
1473
1474 case 8:
1475 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1476 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1477 break;
1478
1479 case 9:
1480 case 10:
1481 case 11:
1482 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1483 {
1484 TCGv_i32 tmp = tcg_temp_new_i32();
1485 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1486 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1487 tcg_temp_free(tmp);
1488 }
1489 break;
1490
1491 case 12:
1492 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1493 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1494 break;
1495
1496 case 13:
1497 case 14:
1498 case 15:
1499 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1500 {
1501 TCGv_i32 tmp = tcg_temp_new_i32();
1502 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1503 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1504 tcg_temp_free(tmp);
1505 }
1506 break;
1507 }
1508 break;
1509
1510 case 1:
1511 switch (OP2) {
1512 case 0:
1513 case 1:
1514 gen_window_check2(dc, RRR_R, RRR_S);
1515 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1516 32 - (RRR_T | ((OP2 & 1) << 4)));
1517 break;
1518
1519 case 2:
1520 case 3:
1521 gen_window_check2(dc, RRR_R, RRR_T);
1522 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1523 RRR_S | ((OP2 & 1) << 4));
1524 break;
1525
1526 case 4:
1527 gen_window_check2(dc, RRR_R, RRR_T);
1528 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1529 break;
1530
1531 case 6:
1532 if (gen_check_sr(dc, RSR_SR, SR_X)) {
1533 TCGv_i32 tmp = tcg_temp_new_i32();
1534
1535 if (RSR_SR >= 64) {
1536 gen_check_privilege(dc);
1537 }
1538 gen_window_check1(dc, RRR_T);
1539 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1540 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1541 gen_wsr(dc, RSR_SR, tmp);
1542 tcg_temp_free(tmp);
1543 }
1544 break;
1545
1546
1547
1548
1549
1550#define gen_shift_reg(cmd, reg) do { \
1551 TCGv_i64 tmp = tcg_temp_new_i64(); \
1552 tcg_gen_extu_i32_i64(tmp, reg); \
1553 tcg_gen_##cmd##_i64(v, v, tmp); \
1554 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1555 tcg_temp_free_i64(v); \
1556 tcg_temp_free_i64(tmp); \
1557 } while (0)
1558
1559#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1560
1561 case 8:
1562 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1563 {
1564 TCGv_i64 v = tcg_temp_new_i64();
1565 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1566 gen_shift(shr);
1567 }
1568 break;
1569
1570 case 9:
1571 gen_window_check2(dc, RRR_R, RRR_T);
1572 if (dc->sar_5bit) {
1573 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1574 } else {
1575 TCGv_i64 v = tcg_temp_new_i64();
1576 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1577 gen_shift(shr);
1578 }
1579 break;
1580
1581 case 10:
1582 gen_window_check2(dc, RRR_R, RRR_S);
1583 if (dc->sar_m32_5bit) {
1584 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1585 } else {
1586 TCGv_i64 v = tcg_temp_new_i64();
1587 TCGv_i32 s = tcg_const_i32(32);
1588 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1589 tcg_gen_andi_i32(s, s, 0x3f);
1590 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1591 gen_shift_reg(shl, s);
1592 tcg_temp_free(s);
1593 }
1594 break;
1595
1596 case 11:
1597 gen_window_check2(dc, RRR_R, RRR_T);
1598 if (dc->sar_5bit) {
1599 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1600 } else {
1601 TCGv_i64 v = tcg_temp_new_i64();
1602 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1603 gen_shift(sar);
1604 }
1605 break;
1606#undef gen_shift
1607#undef gen_shift_reg
1608
1609 case 12:
1610 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1611 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1612 {
1613 TCGv_i32 v1 = tcg_temp_new_i32();
1614 TCGv_i32 v2 = tcg_temp_new_i32();
1615 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1616 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1617 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1618 tcg_temp_free(v2);
1619 tcg_temp_free(v1);
1620 }
1621 break;
1622
1623 case 13:
1624 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1625 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1626 {
1627 TCGv_i32 v1 = tcg_temp_new_i32();
1628 TCGv_i32 v2 = tcg_temp_new_i32();
1629 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1630 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1631 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1632 tcg_temp_free(v2);
1633 tcg_temp_free(v1);
1634 }
1635 break;
1636
1637 default:
1638 RESERVED();
1639 break;
1640 }
1641 break;
1642
1643 case 2:
1644 if (OP2 >= 8) {
1645 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1646 }
1647
1648 if (OP2 >= 12) {
1649 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1650 int label = gen_new_label();
1651 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1652 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1653 gen_set_label(label);
1654 }
1655
1656 switch (OP2) {
1657#define BOOLEAN_LOGIC(fn, r, s, t) \
1658 do { \
1659 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1660 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1661 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1662 \
1663 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1664 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1665 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1666 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1667 tcg_temp_free(tmp1); \
1668 tcg_temp_free(tmp2); \
1669 } while (0)
1670
1671 case 0:
1672 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1673 break;
1674
1675 case 1:
1676 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1677 break;
1678
1679 case 2:
1680 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1681 break;
1682
1683 case 3:
1684 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1685 break;
1686
1687 case 4:
1688 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1689 break;
1690
1691#undef BOOLEAN_LOGIC
1692
1693 case 8:
1694 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1695 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1696 break;
1697
1698 case 10:
1699 case 11:
1700 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1701 {
1702 TCGv lo = tcg_temp_new();
1703
1704 if (OP2 == 10) {
1705 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1706 cpu_R[RRR_S], cpu_R[RRR_T]);
1707 } else {
1708 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1709 cpu_R[RRR_S], cpu_R[RRR_T]);
1710 }
1711 tcg_temp_free(lo);
1712 }
1713 break;
1714
1715 case 12:
1716 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1717 break;
1718
1719 case 13:
1720 case 15:
1721 {
1722 int label1 = gen_new_label();
1723 int label2 = gen_new_label();
1724
1725 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1726 label1);
1727 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1728 label1);
1729 tcg_gen_movi_i32(cpu_R[RRR_R],
1730 OP2 == 13 ? 0x80000000 : 0);
1731 tcg_gen_br(label2);
1732 gen_set_label(label1);
1733 if (OP2 == 13) {
1734 tcg_gen_div_i32(cpu_R[RRR_R],
1735 cpu_R[RRR_S], cpu_R[RRR_T]);
1736 } else {
1737 tcg_gen_rem_i32(cpu_R[RRR_R],
1738 cpu_R[RRR_S], cpu_R[RRR_T]);
1739 }
1740 gen_set_label(label2);
1741 }
1742 break;
1743
1744 case 14:
1745 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1746 break;
1747
1748 default:
1749 RESERVED();
1750 break;
1751 }
1752 break;
1753
1754 case 3:
1755 switch (OP2) {
1756 case 0:
1757 if (gen_check_sr(dc, RSR_SR, SR_R)) {
1758 if (RSR_SR >= 64) {
1759 gen_check_privilege(dc);
1760 }
1761 gen_window_check1(dc, RRR_T);
1762 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1763 }
1764 break;
1765
1766 case 1:
1767 if (gen_check_sr(dc, RSR_SR, SR_W)) {
1768 if (RSR_SR >= 64) {
1769 gen_check_privilege(dc);
1770 }
1771 gen_window_check1(dc, RRR_T);
1772 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1773 }
1774 break;
1775
1776 case 2:
1777 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1778 gen_window_check2(dc, RRR_R, RRR_S);
1779 {
1780 int shift = 24 - RRR_T;
1781
1782 if (shift == 24) {
1783 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1784 } else if (shift == 16) {
1785 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1786 } else {
1787 TCGv_i32 tmp = tcg_temp_new_i32();
1788 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1789 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1790 tcg_temp_free(tmp);
1791 }
1792 }
1793 break;
1794
1795 case 3:
1796 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1797 gen_window_check2(dc, RRR_R, RRR_S);
1798 {
1799 TCGv_i32 tmp1 = tcg_temp_new_i32();
1800 TCGv_i32 tmp2 = tcg_temp_new_i32();
1801 TCGv_i32 zero = tcg_const_i32(0);
1802
1803 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1804 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1805 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1806
1807 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1808 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1809
1810 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1811 cpu_R[RRR_S], tmp1);
1812 tcg_temp_free(tmp1);
1813 tcg_temp_free(tmp2);
1814 tcg_temp_free(zero);
1815 }
1816 break;
1817
1818 case 4:
1819 case 5:
1820 case 6:
1821 case 7:
1822 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1823 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1824 {
1825 static const TCGCond cond[] = {
1826 TCG_COND_LE,
1827 TCG_COND_GE,
1828 TCG_COND_LEU,
1829 TCG_COND_GEU
1830 };
1831 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1832 cpu_R[RRR_S], cpu_R[RRR_T],
1833 cpu_R[RRR_S], cpu_R[RRR_T]);
1834 }
1835 break;
1836
1837 case 8:
1838 case 9:
1839 case 10:
1840 case 11:
1841 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1842 {
1843 static const TCGCond cond[] = {
1844 TCG_COND_EQ,
1845 TCG_COND_NE,
1846 TCG_COND_LT,
1847 TCG_COND_GE,
1848 };
1849 TCGv_i32 zero = tcg_const_i32(0);
1850
1851 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1852 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1853 tcg_temp_free(zero);
1854 }
1855 break;
1856
1857 case 12:
1858 case 13:
1859 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1860 gen_window_check2(dc, RRR_R, RRR_S);
1861 {
1862 TCGv_i32 zero = tcg_const_i32(0);
1863 TCGv_i32 tmp = tcg_temp_new_i32();
1864
1865 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1866 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1867 cpu_R[RRR_R], tmp, zero,
1868 cpu_R[RRR_S], cpu_R[RRR_R]);
1869
1870 tcg_temp_free(tmp);
1871 tcg_temp_free(zero);
1872 }
1873 break;
1874
1875 case 14:
1876 gen_window_check1(dc, RRR_R);
1877 {
1878 int st = (RRR_S << 4) + RRR_T;
1879 if (uregnames[st].name) {
1880 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1881 } else {
1882 qemu_log("RUR %d not implemented, ", st);
1883 TBD();
1884 }
1885 }
1886 break;
1887
1888 case 15:
1889 gen_window_check1(dc, RRR_T);
1890 if (uregnames[RSR_SR].name) {
1891 gen_wur(RSR_SR, cpu_R[RRR_T]);
1892 } else {
1893 qemu_log("WUR %d not implemented, ", RSR_SR);
1894 TBD();
1895 }
1896 break;
1897
1898 }
1899 break;
1900
1901 case 4:
1902 case 5:
1903 gen_window_check2(dc, RRR_R, RRR_T);
1904 {
1905 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1906 int maskimm = (1 << (OP2 + 1)) - 1;
1907
1908 TCGv_i32 tmp = tcg_temp_new_i32();
1909 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1910 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1911 tcg_temp_free(tmp);
1912 }
1913 break;
1914
1915 case 6:
1916 RESERVED();
1917 break;
1918
1919 case 7:
1920 RESERVED();
1921 break;
1922
1923 case 8:
1924 switch (OP2) {
1925 case 0:
1926 case 1:
1927 case 4:
1928 case 5:
1929 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1930 gen_window_check2(dc, RRR_S, RRR_T);
1931 gen_check_cpenable(dc, 0);
1932 {
1933 TCGv_i32 addr = tcg_temp_new_i32();
1934 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1935 gen_load_store_alignment(dc, 2, addr, false);
1936 if (OP2 & 0x4) {
1937 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1938 } else {
1939 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1940 }
1941 if (OP2 & 0x1) {
1942 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1943 }
1944 tcg_temp_free(addr);
1945 }
1946 break;
1947
1948 default:
1949 RESERVED();
1950 break;
1951 }
1952 break;
1953
1954 case 9:
1955 gen_window_check2(dc, RRR_S, RRR_T);
1956 switch (OP2) {
1957 case 0:
1958 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1959 gen_check_privilege(dc);
1960 {
1961 TCGv_i32 addr = tcg_temp_new_i32();
1962 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1963 (0xffffffc0 | (RRR_R << 2)));
1964 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1965 tcg_temp_free(addr);
1966 }
1967 break;
1968
1969 case 4:
1970 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1971 gen_check_privilege(dc);
1972 {
1973 TCGv_i32 addr = tcg_temp_new_i32();
1974 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1975 (0xffffffc0 | (RRR_R << 2)));
1976 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1977 tcg_temp_free(addr);
1978 }
1979 break;
1980
1981 default:
1982 RESERVED();
1983 break;
1984 }
1985 break;
1986
1987 case 10:
1988 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1989 switch (OP2) {
1990 case 0:
1991 gen_check_cpenable(dc, 0);
1992 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1993 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1994 break;
1995
1996 case 1:
1997 gen_check_cpenable(dc, 0);
1998 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1999 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2000 break;
2001
2002 case 2:
2003 gen_check_cpenable(dc, 0);
2004 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2005 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2006 break;
2007
2008 case 4:
2009 gen_check_cpenable(dc, 0);
2010 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2011 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
2012 break;
2013
2014 case 5:
2015 gen_check_cpenable(dc, 0);
2016 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2017 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
2018 break;
2019
2020 case 8:
2021 case 9:
2022 case 10:
2023 case 11:
2024 case 14:
2025 gen_window_check1(dc, RRR_R);
2026 gen_check_cpenable(dc, 0);
2027 {
2028 static const unsigned rounding_mode_const[] = {
2029 float_round_nearest_even,
2030 float_round_to_zero,
2031 float_round_down,
2032 float_round_up,
2033 [6] = float_round_to_zero,
2034 };
2035 TCGv_i32 rounding_mode = tcg_const_i32(
2036 rounding_mode_const[OP2 & 7]);
2037 TCGv_i32 scale = tcg_const_i32(RRR_T);
2038
2039 if (OP2 == 14) {
2040 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2041 rounding_mode, scale);
2042 } else {
2043 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2044 rounding_mode, scale);
2045 }
2046
2047 tcg_temp_free(rounding_mode);
2048 tcg_temp_free(scale);
2049 }
2050 break;
2051
2052 case 12:
2053 case 13:
2054 gen_window_check1(dc, RRR_S);
2055 gen_check_cpenable(dc, 0);
2056 {
2057 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2058
2059 if (OP2 == 13) {
2060 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2061 cpu_R[RRR_S], scale);
2062 } else {
2063 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2064 cpu_R[RRR_S], scale);
2065 }
2066 tcg_temp_free(scale);
2067 }
2068 break;
2069
2070 case 15:
2071 switch (RRR_T) {
2072 case 0:
2073 gen_check_cpenable(dc, 0);
2074 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2075 break;
2076
2077 case 1:
2078 gen_check_cpenable(dc, 0);
2079 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2080 break;
2081
2082 case 4:
2083 gen_window_check1(dc, RRR_R);
2084 gen_check_cpenable(dc, 0);
2085 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2086 break;
2087
2088 case 5:
2089 gen_window_check1(dc, RRR_S);
2090 gen_check_cpenable(dc, 0);
2091 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2092 break;
2093
2094 case 6:
2095 gen_check_cpenable(dc, 0);
2096 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2097 break;
2098
2099 default:
2100 RESERVED();
2101 break;
2102 }
2103 break;
2104
2105 default:
2106 RESERVED();
2107 break;
2108 }
2109 break;
2110
2111 case 11:
2112 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2113
2114#define gen_compare(rel, br, a, b) \
2115 do { \
2116 TCGv_i32 bit = tcg_const_i32(1 << br); \
2117 \
2118 gen_check_cpenable(dc, 0); \
2119 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2120 tcg_temp_free(bit); \
2121 } while (0)
2122
2123 switch (OP2) {
2124 case 1:
2125 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2126 break;
2127
2128 case 2:
2129 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2130 break;
2131
2132 case 3:
2133 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2134 break;
2135
2136 case 4:
2137 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2138 break;
2139
2140 case 5:
2141 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2142 break;
2143
2144 case 6:
2145 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2146 break;
2147
2148 case 7:
2149 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2150 break;
2151
2152#undef gen_compare
2153
2154 case 8:
2155 case 9:
2156 case 10:
2157 case 11:
2158 gen_window_check1(dc, RRR_T);
2159 gen_check_cpenable(dc, 0);
2160 {
2161 static const TCGCond cond[] = {
2162 TCG_COND_EQ,
2163 TCG_COND_NE,
2164 TCG_COND_LT,
2165 TCG_COND_GE,
2166 };
2167 TCGv_i32 zero = tcg_const_i32(0);
2168
2169 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2170 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2171 tcg_temp_free(zero);
2172 }
2173 break;
2174
2175 case 12:
2176 case 13:
2177 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2178 gen_check_cpenable(dc, 0);
2179 {
2180 TCGv_i32 zero = tcg_const_i32(0);
2181 TCGv_i32 tmp = tcg_temp_new_i32();
2182
2183 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2184 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2185 cpu_FR[RRR_R], tmp, zero,
2186 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2187
2188 tcg_temp_free(tmp);
2189 tcg_temp_free(zero);
2190 }
2191 break;
2192
2193 default:
2194 RESERVED();
2195 break;
2196 }
2197 break;
2198
2199 default:
2200 RESERVED();
2201 break;
2202 }
2203 break;
2204
2205 case 1:
2206 gen_window_check1(dc, RRR_T);
2207 {
2208 TCGv_i32 tmp = tcg_const_i32(
2209 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2210 0 : ((dc->pc + 3) & ~3)) +
2211 (0xfffc0000 | (RI16_IMM16 << 2)));
2212
2213 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2214 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2215 }
2216 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2217 tcg_temp_free(tmp);
2218 }
2219 break;
2220
2221 case 2:
2222#define gen_load_store(type, shift) do { \
2223 TCGv_i32 addr = tcg_temp_new_i32(); \
2224 gen_window_check2(dc, RRI8_S, RRI8_T); \
2225 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2226 if (shift) { \
2227 gen_load_store_alignment(dc, shift, addr, false); \
2228 } \
2229 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2230 tcg_temp_free(addr); \
2231 } while (0)
2232
2233 switch (RRI8_R) {
2234 case 0:
2235 gen_load_store(ld8u, 0);
2236 break;
2237
2238 case 1:
2239 gen_load_store(ld16u, 1);
2240 break;
2241
2242 case 2:
2243 gen_load_store(ld32u, 2);
2244 break;
2245
2246 case 4:
2247 gen_load_store(st8, 0);
2248 break;
2249
2250 case 5:
2251 gen_load_store(st16, 1);
2252 break;
2253
2254 case 6:
2255 gen_load_store(st32, 2);
2256 break;
2257
2258#define gen_dcache_hit_test(w, shift) do { \
2259 TCGv_i32 addr = tcg_temp_new_i32(); \
2260 TCGv_i32 res = tcg_temp_new_i32(); \
2261 gen_window_check1(dc, RRI##w##_S); \
2262 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2263 RRI##w##_IMM##w << shift); \
2264 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2265 tcg_temp_free(addr); \
2266 tcg_temp_free(res); \
2267 } while (0)
2268
2269#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2270#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2271
2272 case 7:
2273 if (RRI8_T < 8) {
2274 HAS_OPTION(XTENSA_OPTION_DCACHE);
2275 }
2276
2277 switch (RRI8_T) {
2278 case 0:
2279 gen_window_check1(dc, RRI8_S);
2280 break;
2281
2282 case 1:
2283 gen_window_check1(dc, RRI8_S);
2284 break;
2285
2286 case 2:
2287 gen_window_check1(dc, RRI8_S);
2288 break;
2289
2290 case 3:
2291 gen_window_check1(dc, RRI8_S);
2292 break;
2293
2294 case 4:
2295 gen_dcache_hit_test8();
2296 break;
2297
2298 case 5:
2299 gen_dcache_hit_test8();
2300 break;
2301
2302 case 6:
2303 gen_check_privilege(dc);
2304 gen_dcache_hit_test8();
2305 break;
2306
2307 case 7:
2308 gen_check_privilege(dc);
2309 gen_window_check1(dc, RRI8_S);
2310 break;
2311
2312 case 8:
2313 switch (OP1) {
2314 case 0:
2315 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2316 gen_check_privilege(dc);
2317 gen_dcache_hit_test4();
2318 break;
2319
2320 case 2:
2321 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2322 gen_check_privilege(dc);
2323 gen_dcache_hit_test4();
2324 break;
2325
2326 case 3:
2327 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2328 gen_check_privilege(dc);
2329 gen_window_check1(dc, RRI4_S);
2330 break;
2331
2332 case 4:
2333 HAS_OPTION(XTENSA_OPTION_DCACHE);
2334 gen_check_privilege(dc);
2335 gen_window_check1(dc, RRI4_S);
2336 break;
2337
2338 case 5:
2339 HAS_OPTION(XTENSA_OPTION_DCACHE);
2340 gen_check_privilege(dc);
2341 gen_window_check1(dc, RRI4_S);
2342 break;
2343
2344 default:
2345 RESERVED();
2346 break;
2347
2348 }
2349 break;
2350
2351#undef gen_dcache_hit_test
2352#undef gen_dcache_hit_test4
2353#undef gen_dcache_hit_test8
2354
2355#define gen_icache_hit_test(w, shift) do { \
2356 TCGv_i32 addr = tcg_temp_new_i32(); \
2357 gen_window_check1(dc, RRI##w##_S); \
2358 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2359 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2360 RRI##w##_IMM##w << shift); \
2361 gen_helper_itlb_hit_test(cpu_env, addr); \
2362 tcg_temp_free(addr); \
2363 } while (0)
2364
2365#define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2366#define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2367
2368 case 12:
2369 HAS_OPTION(XTENSA_OPTION_ICACHE);
2370 gen_window_check1(dc, RRI8_S);
2371 break;
2372
2373 case 13:
2374 switch (OP1) {
2375 case 0:
2376 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2377 gen_check_privilege(dc);
2378 gen_icache_hit_test4();
2379 break;
2380
2381 case 2:
2382 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2383 gen_check_privilege(dc);
2384 gen_icache_hit_test4();
2385 break;
2386
2387 case 3:
2388 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2389 gen_check_privilege(dc);
2390 gen_window_check1(dc, RRI4_S);
2391 break;
2392
2393 default:
2394 RESERVED();
2395 break;
2396 }
2397 break;
2398
2399 case 14:
2400 HAS_OPTION(XTENSA_OPTION_ICACHE);
2401 gen_icache_hit_test8();
2402 break;
2403
2404 case 15:
2405 HAS_OPTION(XTENSA_OPTION_ICACHE);
2406 gen_check_privilege(dc);
2407 gen_window_check1(dc, RRI8_S);
2408 break;
2409
2410 default:
2411 RESERVED();
2412 break;
2413 }
2414 break;
2415
2416#undef gen_icache_hit_test
2417#undef gen_icache_hit_test4
2418#undef gen_icache_hit_test8
2419
2420 case 9:
2421 gen_load_store(ld16s, 1);
2422 break;
2423#undef gen_load_store
2424
2425 case 10:
2426 gen_window_check1(dc, RRI8_T);
2427 tcg_gen_movi_i32(cpu_R[RRI8_T],
2428 RRI8_IMM8 | (RRI8_S << 8) |
2429 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2430 break;
2431
2432#define gen_load_store_no_hw_align(type) do { \
2433 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2434 gen_window_check2(dc, RRI8_S, RRI8_T); \
2435 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2436 gen_load_store_alignment(dc, 2, addr, true); \
2437 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2438 tcg_temp_free(addr); \
2439 } while (0)
2440
2441 case 11:
2442 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2443 gen_load_store_no_hw_align(ld32u);
2444 break;
2445
2446 case 12:
2447 gen_window_check2(dc, RRI8_S, RRI8_T);
2448 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2449 break;
2450
2451 case 13:
2452 gen_window_check2(dc, RRI8_S, RRI8_T);
2453 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2454 break;
2455
2456 case 14:
2457 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2458 gen_window_check2(dc, RRI8_S, RRI8_T);
2459 {
2460 int label = gen_new_label();
2461 TCGv_i32 tmp = tcg_temp_local_new_i32();
2462 TCGv_i32 addr = tcg_temp_local_new_i32();
2463 TCGv_i32 tpc;
2464
2465 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2466 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2467 gen_load_store_alignment(dc, 2, addr, true);
2468
2469 gen_advance_ccount(dc);
2470 tpc = tcg_const_i32(dc->pc);
2471 gen_helper_check_atomctl(cpu_env, tpc, addr);
2472 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2473 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2474 cpu_SR[SCOMPARE1], label);
2475
2476 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2477
2478 gen_set_label(label);
2479 tcg_temp_free(tpc);
2480 tcg_temp_free(addr);
2481 tcg_temp_free(tmp);
2482 }
2483 break;
2484
2485 case 15:
2486 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2487 gen_load_store_no_hw_align(st32);
2488 break;
2489#undef gen_load_store_no_hw_align
2490
2491 default:
2492 RESERVED();
2493 break;
2494 }
2495 break;
2496
2497 case 3:
2498 switch (RRI8_R) {
2499 case 0:
2500 case 4:
2501 case 8:
2502 case 12:
2503 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2504 gen_window_check1(dc, RRI8_S);
2505 gen_check_cpenable(dc, 0);
2506 {
2507 TCGv_i32 addr = tcg_temp_new_i32();
2508 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2509 gen_load_store_alignment(dc, 2, addr, false);
2510 if (RRI8_R & 0x4) {
2511 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2512 } else {
2513 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2514 }
2515 if (RRI8_R & 0x8) {
2516 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2517 }
2518 tcg_temp_free(addr);
2519 }
2520 break;
2521
2522 default:
2523 RESERVED();
2524 break;
2525 }
2526 break;
2527
2528 case 4:
2529 HAS_OPTION(XTENSA_OPTION_MAC16);
2530 {
2531 enum {
2532 MAC16_UMUL = 0x0,
2533 MAC16_MUL = 0x4,
2534 MAC16_MULA = 0x8,
2535 MAC16_MULS = 0xc,
2536 MAC16_NONE = 0xf,
2537 } op = OP1 & 0xc;
2538 bool is_m1_sr = (OP2 & 0x3) == 2;
2539 bool is_m2_sr = (OP2 & 0xc) == 0;
2540 uint32_t ld_offset = 0;
2541
2542 if (OP2 > 9) {
2543 RESERVED();
2544 }
2545
2546 switch (OP2 & 2) {
2547 case 0:
2548 is_m1_sr = true;
2549 ld_offset = (OP2 & 1) ? -4 : 4;
2550
2551 if (OP2 >= 8) {
2552 if (OP1 == 0) {
2553 op = MAC16_NONE;
2554 } else {
2555 RESERVED();
2556 }
2557 } else if (op != MAC16_MULA) {
2558 RESERVED();
2559 }
2560 break;
2561
2562 case 2:
2563 if (op == MAC16_UMUL && OP2 != 7) {
2564 RESERVED();
2565 }
2566 break;
2567 }
2568
2569 if (op != MAC16_NONE) {
2570 if (!is_m1_sr) {
2571 gen_window_check1(dc, RRR_S);
2572 }
2573 if (!is_m2_sr) {
2574 gen_window_check1(dc, RRR_T);
2575 }
2576 }
2577
2578 {
2579 TCGv_i32 vaddr = tcg_temp_new_i32();
2580 TCGv_i32 mem32 = tcg_temp_new_i32();
2581
2582 if (ld_offset) {
2583 gen_window_check1(dc, RRR_S);
2584 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2585 gen_load_store_alignment(dc, 2, vaddr, false);
2586 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2587 }
2588 if (op != MAC16_NONE) {
2589 TCGv_i32 m1 = gen_mac16_m(
2590 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2591 OP1 & 1, op == MAC16_UMUL);
2592 TCGv_i32 m2 = gen_mac16_m(
2593 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2594 OP1 & 2, op == MAC16_UMUL);
2595
2596 if (op == MAC16_MUL || op == MAC16_UMUL) {
2597 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2598 if (op == MAC16_UMUL) {
2599 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2600 } else {
2601 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2602 }
2603 } else {
2604 TCGv_i32 lo = tcg_temp_new_i32();
2605 TCGv_i32 hi = tcg_temp_new_i32();
2606
2607 tcg_gen_mul_i32(lo, m1, m2);
2608 tcg_gen_sari_i32(hi, lo, 31);
2609 if (op == MAC16_MULA) {
2610 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2611 cpu_SR[ACCLO], cpu_SR[ACCHI],
2612 lo, hi);
2613 } else {
2614 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2615 cpu_SR[ACCLO], cpu_SR[ACCHI],
2616 lo, hi);
2617 }
2618 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2619
2620 tcg_temp_free_i32(lo);
2621 tcg_temp_free_i32(hi);
2622 }
2623 tcg_temp_free(m1);
2624 tcg_temp_free(m2);
2625 }
2626 if (ld_offset) {
2627 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2628 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2629 }
2630 tcg_temp_free(vaddr);
2631 tcg_temp_free(mem32);
2632 }
2633 }
2634 break;
2635
2636 case 5:
2637 switch (CALL_N) {
2638 case 0:
2639 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2640 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2641 break;
2642
2643 case 1:
2644 case 2:
2645 case 3:
2646 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2647 gen_window_check1(dc, CALL_N << 2);
2648 gen_callwi(dc, CALL_N,
2649 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2650 break;
2651 }
2652 break;
2653
2654 case 6:
2655 switch (CALL_N) {
2656 case 0:
2657 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2658 break;
2659
2660 case 1:
2661 gen_window_check1(dc, BRI12_S);
2662 {
2663 static const TCGCond cond[] = {
2664 TCG_COND_EQ,
2665 TCG_COND_NE,
2666 TCG_COND_LT,
2667 TCG_COND_GE,
2668 };
2669
2670 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2671 4 + BRI12_IMM12_SE);
2672 }
2673 break;
2674
2675 case 2:
2676 gen_window_check1(dc, BRI8_S);
2677 {
2678 static const TCGCond cond[] = {
2679 TCG_COND_EQ,
2680 TCG_COND_NE,
2681 TCG_COND_LT,
2682 TCG_COND_GE,
2683 };
2684
2685 gen_brcondi(dc, cond[BRI8_M & 3],
2686 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2687 }
2688 break;
2689
2690 case 3:
2691 switch (BRI8_M) {
2692 case 0:
2693 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2694 {
2695 TCGv_i32 pc = tcg_const_i32(dc->pc);
2696 TCGv_i32 s = tcg_const_i32(BRI12_S);
2697 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2698 gen_advance_ccount(dc);
2699 gen_helper_entry(cpu_env, pc, s, imm);
2700 tcg_temp_free(imm);
2701 tcg_temp_free(s);
2702 tcg_temp_free(pc);
2703 reset_used_window(dc);
2704 }
2705 break;
2706
2707 case 1:
2708 switch (BRI8_R) {
2709 case 0:
2710 case 1:
2711 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2712 {
2713 TCGv_i32 tmp = tcg_temp_new_i32();
2714 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2715 gen_brcondi(dc,
2716 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2717 tmp, 0, 4 + RRI8_IMM8_SE);
2718 tcg_temp_free(tmp);
2719 }
2720 break;
2721
2722 case 8:
2723 case 9:
2724 case 10:
2725 HAS_OPTION(XTENSA_OPTION_LOOP);
2726 gen_window_check1(dc, RRI8_S);
2727 {
2728 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2729 TCGv_i32 tmp = tcg_const_i32(lend);
2730
2731 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2732 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2733 gen_helper_wsr_lend(cpu_env, tmp);
2734 tcg_temp_free(tmp);
2735
2736 if (BRI8_R > 8) {
2737 int label = gen_new_label();
2738 tcg_gen_brcondi_i32(
2739 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2740 cpu_R[RRI8_S], 0, label);
2741 gen_jumpi(dc, lend, 1);
2742 gen_set_label(label);
2743 }
2744
2745 gen_jumpi(dc, dc->next_pc, 0);
2746 }
2747 break;
2748
2749 default:
2750 RESERVED();
2751 break;
2752
2753 }
2754 break;
2755
2756 case 2:
2757 case 3:
2758 gen_window_check1(dc, BRI8_S);
2759 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2760 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2761 break;
2762 }
2763 break;
2764
2765 }
2766 break;
2767
2768 case 7:
2769 {
2770 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2771
2772 switch (RRI8_R & 7) {
2773 case 0:
2774 gen_window_check2(dc, RRI8_S, RRI8_T);
2775 {
2776 TCGv_i32 tmp = tcg_temp_new_i32();
2777 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2778 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2779 tcg_temp_free(tmp);
2780 }
2781 break;
2782
2783 case 1:
2784 case 2:
2785 case 3:
2786 gen_window_check2(dc, RRI8_S, RRI8_T);
2787 {
2788 static const TCGCond cond[] = {
2789 [1] = TCG_COND_EQ,
2790 [2] = TCG_COND_LT,
2791 [3] = TCG_COND_LTU,
2792 [9] = TCG_COND_NE,
2793 [10] = TCG_COND_GE,
2794 [11] = TCG_COND_GEU,
2795 };
2796 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2797 4 + RRI8_IMM8_SE);
2798 }
2799 break;
2800
2801 case 4:
2802 gen_window_check2(dc, RRI8_S, RRI8_T);
2803 {
2804 TCGv_i32 tmp = tcg_temp_new_i32();
2805 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2806 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2807 4 + RRI8_IMM8_SE);
2808 tcg_temp_free(tmp);
2809 }
2810 break;
2811
2812 case 5:
2813 gen_window_check2(dc, RRI8_S, RRI8_T);
2814 {
2815#ifdef TARGET_WORDS_BIGENDIAN
2816 TCGv_i32 bit = tcg_const_i32(0x80000000);
2817#else
2818 TCGv_i32 bit = tcg_const_i32(0x00000001);
2819#endif
2820 TCGv_i32 tmp = tcg_temp_new_i32();
2821 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2822#ifdef TARGET_WORDS_BIGENDIAN
2823 tcg_gen_shr_i32(bit, bit, tmp);
2824#else
2825 tcg_gen_shl_i32(bit, bit, tmp);
2826#endif
2827 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2828 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2829 tcg_temp_free(tmp);
2830 tcg_temp_free(bit);
2831 }
2832 break;
2833
2834 case 6:
2835 case 7:
2836 gen_window_check1(dc, RRI8_S);
2837 {
2838 TCGv_i32 tmp = tcg_temp_new_i32();
2839 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2840#ifdef TARGET_WORDS_BIGENDIAN
2841 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2842#else
2843 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2844#endif
2845 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2846 tcg_temp_free(tmp);
2847 }
2848 break;
2849
2850 }
2851 }
2852 break;
2853
2854#define gen_narrow_load_store(type) do { \
2855 TCGv_i32 addr = tcg_temp_new_i32(); \
2856 gen_window_check2(dc, RRRN_S, RRRN_T); \
2857 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2858 gen_load_store_alignment(dc, 2, addr, false); \
2859 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2860 tcg_temp_free(addr); \
2861 } while (0)
2862
2863 case 8:
2864 gen_narrow_load_store(ld32u);
2865 break;
2866
2867 case 9:
2868 gen_narrow_load_store(st32);
2869 break;
2870#undef gen_narrow_load_store
2871
2872 case 10:
2873 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
2874 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2875 break;
2876
2877 case 11:
2878 gen_window_check2(dc, RRRN_R, RRRN_S);
2879 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
2880 break;
2881
2882 case 12:
2883 gen_window_check1(dc, RRRN_S);
2884 if (RRRN_T < 8) {
2885 tcg_gen_movi_i32(cpu_R[RRRN_S],
2886 RRRN_R | (RRRN_T << 4) |
2887 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2888 } else {
2889 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2890
2891 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2892 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2893 }
2894 break;
2895
2896 case 13:
2897 switch (RRRN_R) {
2898 case 0:
2899 gen_window_check2(dc, RRRN_S, RRRN_T);
2900 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2901 break;
2902
2903 case 15:
2904 switch (RRRN_T) {
2905 case 0:
2906 gen_jump(dc, cpu_R[0]);
2907 break;
2908
2909 case 1:
2910 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2911 {
2912 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2913 gen_advance_ccount(dc);
2914 gen_helper_retw(tmp, cpu_env, tmp);
2915 gen_jump(dc, tmp);
2916 tcg_temp_free(tmp);
2917 }
2918 break;
2919
2920 case 2:
2921 HAS_OPTION(XTENSA_OPTION_DEBUG);
2922 if (dc->debug) {
2923 gen_debug_exception(dc, DEBUGCAUSE_BN);
2924 }
2925 break;
2926
2927 case 3:
2928 break;
2929
2930 case 6:
2931 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2932 break;
2933
2934 default:
2935 RESERVED();
2936 break;
2937 }
2938 break;
2939
2940 default:
2941 RESERVED();
2942 break;
2943 }
2944 break;
2945
2946 default:
2947 RESERVED();
2948 break;
2949 }
2950
2951 if (dc->is_jmp == DISAS_NEXT) {
2952 gen_check_loop_end(dc, 0);
2953 }
2954 dc->pc = dc->next_pc;
2955
2956 return;
2957
2958invalid_opcode:
2959 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2960 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2961#undef HAS_OPTION
2962}
2963
2964static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
2965{
2966 uint8_t b0 = cpu_ldub_code(env, dc->pc);
2967 return xtensa_op0_insn_len(OP0);
2968}
2969
2970static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
2971{
2972 CPUState *cs = CPU(xtensa_env_get_cpu(env));
2973 CPUBreakpoint *bp;
2974
2975 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
2976 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
2977 if (bp->pc == dc->pc) {
2978 tcg_gen_movi_i32(cpu_pc, dc->pc);
2979 gen_exception(dc, EXCP_DEBUG);
2980 dc->is_jmp = DISAS_UPDATE;
2981 }
2982 }
2983 }
2984}
2985
2986static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
2987{
2988 unsigned i;
2989
2990 for (i = 0; i < dc->config->nibreak; ++i) {
2991 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2992 env->sregs[IBREAKA + i] == dc->pc) {
2993 gen_debug_exception(dc, DEBUGCAUSE_IB);
2994 break;
2995 }
2996 }
2997}
2998
2999static inline
3000void gen_intermediate_code_internal(XtensaCPU *cpu,
3001 TranslationBlock *tb, bool search_pc)
3002{
3003 CPUState *cs = CPU(cpu);
3004 CPUXtensaState *env = &cpu->env;
3005 DisasContext dc;
3006 int insn_count = 0;
3007 int j, lj = -1;
3008 uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
3009 int max_insns = tb->cflags & CF_COUNT_MASK;
3010 uint32_t pc_start = tb->pc;
3011 uint32_t next_page_start =
3012 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3013
3014 if (max_insns == 0) {
3015 max_insns = CF_COUNT_MASK;
3016 }
3017
3018 dc.config = env->config;
3019 dc.singlestep_enabled = cs->singlestep_enabled;
3020 dc.tb = tb;
3021 dc.pc = pc_start;
3022 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3023 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
3024 dc.lbeg = env->sregs[LBEG];
3025 dc.lend = env->sregs[LEND];
3026 dc.is_jmp = DISAS_NEXT;
3027 dc.ccount_delta = 0;
3028 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
3029 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
3030 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3031 XTENSA_TBFLAG_CPENABLE_SHIFT;
3032
3033 init_litbase(&dc);
3034 init_sar_tracker(&dc);
3035 reset_used_window(&dc);
3036 if (dc.icount) {
3037 dc.next_icount = tcg_temp_local_new_i32();
3038 }
3039
3040 gen_tb_start();
3041
3042 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
3043 tcg_gen_movi_i32(cpu_pc, dc.pc);
3044 gen_exception(&dc, EXCP_DEBUG);
3045 }
3046
3047 do {
3048 check_breakpoint(env, &dc);
3049
3050 if (search_pc) {
3051 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3052 if (lj < j) {
3053 lj++;
3054 while (lj < j) {
3055 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3056 }
3057 }
3058 tcg_ctx.gen_opc_pc[lj] = dc.pc;
3059 tcg_ctx.gen_opc_instr_start[lj] = 1;
3060 tcg_ctx.gen_opc_icount[lj] = insn_count;
3061 }
3062
3063 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3064 tcg_gen_debug_insn_start(dc.pc);
3065 }
3066
3067 ++dc.ccount_delta;
3068
3069 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3070 gen_io_start();
3071 }
3072
3073 if (dc.icount) {
3074 int label = gen_new_label();
3075
3076 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3077 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3078 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3079 if (dc.debug) {
3080 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3081 }
3082 gen_set_label(label);
3083 }
3084
3085 if (dc.debug) {
3086 gen_ibreak_check(env, &dc);
3087 }
3088
3089 disas_xtensa_insn(env, &dc);
3090 ++insn_count;
3091 if (dc.icount) {
3092 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3093 }
3094 if (cs->singlestep_enabled) {
3095 tcg_gen_movi_i32(cpu_pc, dc.pc);
3096 gen_exception(&dc, EXCP_DEBUG);
3097 break;
3098 }
3099 } while (dc.is_jmp == DISAS_NEXT &&
3100 insn_count < max_insns &&
3101 dc.pc < next_page_start &&
3102 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
3103 tcg_ctx.gen_opc_ptr < gen_opc_end);
3104
3105 reset_litbase(&dc);
3106 reset_sar_tracker(&dc);
3107 if (dc.icount) {
3108 tcg_temp_free(dc.next_icount);
3109 }
3110
3111 if (tb->cflags & CF_LAST_IO) {
3112 gen_io_end();
3113 }
3114
3115 if (dc.is_jmp == DISAS_NEXT) {
3116 gen_jumpi(&dc, dc.pc, 0);
3117 }
3118 gen_tb_end(tb, insn_count);
3119 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3120
3121#ifdef DEBUG_DISAS
3122 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3123 qemu_log("----------------\n");
3124 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3125 log_target_disas(env, pc_start, dc.pc - pc_start, 0);
3126 qemu_log("\n");
3127 }
3128#endif
3129 if (search_pc) {
3130 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3131 memset(tcg_ctx.gen_opc_instr_start + lj + 1, 0,
3132 (j - lj) * sizeof(tcg_ctx.gen_opc_instr_start[0]));
3133 } else {
3134 tb->size = dc.pc - pc_start;
3135 tb->icount = insn_count;
3136 }
3137}
3138
3139void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3140{
3141 gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, false);
3142}
3143
3144void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
3145{
3146 gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, true);
3147}
3148
3149void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3150 fprintf_function cpu_fprintf, int flags)
3151{
3152 XtensaCPU *cpu = XTENSA_CPU(cs);
3153 CPUXtensaState *env = &cpu->env;
3154 int i, j;
3155
3156 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3157
3158 for (i = j = 0; i < 256; ++i) {
3159 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3160 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3161 (j++ % 4) == 3 ? '\n' : ' ');
3162 }
3163 }
3164
3165 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3166
3167 for (i = j = 0; i < 256; ++i) {
3168 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3169 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
3170 (j++ % 4) == 3 ? '\n' : ' ');
3171 }
3172 }
3173
3174 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3175
3176 for (i = 0; i < 16; ++i) {
3177 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
3178 (i % 4) == 3 ? '\n' : ' ');
3179 }
3180
3181 cpu_fprintf(f, "\n");
3182
3183 for (i = 0; i < env->config->nareg; ++i) {
3184 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3185 (i % 4) == 3 ? '\n' : ' ');
3186 }
3187
3188 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3189 cpu_fprintf(f, "\n");
3190
3191 for (i = 0; i < 16; ++i) {
3192 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3193 float32_val(env->fregs[i]),
3194 *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
3195 }
3196 }
3197}
3198
3199void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
3200{
3201 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3202}
3203
