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26#include "qemu-common.h"
27#include "qemu/error-report.h"
28#include "ui/console.h"
29#include "hw/sysbus.h"
30#include "hw/loader.h"
31
32
33#define DEBUG_CG3 0
34
35#define CG3_ROM_FILE "QEMU,cgthree.bin"
36#define FCODE_MAX_ROM_SIZE 0x10000
37
38#define CG3_REG_SIZE 0x20
39
40#define CG3_REG_BT458_ADDR 0x0
41#define CG3_REG_BT458_COLMAP 0x4
42#define CG3_REG_FBC_CTRL 0x10
43#define CG3_REG_FBC_STATUS 0x11
44#define CG3_REG_FBC_CURSTART 0x12
45#define CG3_REG_FBC_CUREND 0x13
46#define CG3_REG_FBC_VCTRL 0x14
47
48
49#define CG3_CR_ENABLE_INTS 0x80
50
51
52#define CG3_SR_PENDING_INT 0x80
53#define CG3_SR_1152_900_76_B 0x60
54#define CG3_SR_ID_COLOR 0x01
55
56#define CG3_VRAM_SIZE 0x100000
57#define CG3_VRAM_OFFSET 0x800000
58
59#define DPRINTF(fmt, ...) do { \
60 if (DEBUG_CG3) { \
61 printf("CG3: " fmt , ## __VA_ARGS__); \
62 } \
63} while (0);
64
65#define TYPE_CG3 "cgthree"
66#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
67
68typedef struct CG3State {
69 SysBusDevice parent_obj;
70
71 QemuConsole *con;
72 qemu_irq irq;
73 hwaddr prom_addr;
74 MemoryRegion vram_mem;
75 MemoryRegion rom;
76 MemoryRegion reg;
77 uint32_t vram_size;
78 int full_update;
79 uint8_t regs[16];
80 uint8_t r[256], g[256], b[256];
81 uint16_t width, height, depth;
82 uint8_t dac_index, dac_state;
83} CG3State;
84
85static void cg3_update_display(void *opaque)
86{
87 CG3State *s = opaque;
88 DisplaySurface *surface = qemu_console_surface(s->con);
89 const uint8_t *pix;
90 uint32_t *data;
91 uint32_t dval;
92 int x, y, y_start;
93 unsigned int width, height;
94 ram_addr_t page, page_min, page_max;
95
96 if (surface_bits_per_pixel(surface) != 32) {
97 return;
98 }
99 width = s->width;
100 height = s->height;
101
102 y_start = -1;
103 page_min = -1;
104 page_max = 0;
105 page = 0;
106 pix = memory_region_get_ram_ptr(&s->vram_mem);
107 data = (uint32_t *)surface_data(surface);
108
109 for (y = 0; y < height; y++) {
110 int update = s->full_update;
111
112 page = (y * width) & TARGET_PAGE_MASK;
113 update |= memory_region_get_dirty(&s->vram_mem, page, page + width,
114 DIRTY_MEMORY_VGA);
115 if (update) {
116 if (y_start < 0) {
117 y_start = y;
118 }
119 if (page < page_min) {
120 page_min = page;
121 }
122 if (page > page_max) {
123 page_max = page;
124 }
125
126 for (x = 0; x < width; x++) {
127 dval = *pix++;
128 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
129 *data++ = dval;
130 }
131 } else {
132 if (y_start >= 0) {
133 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
134 y_start = -1;
135 }
136 pix += width;
137 data += width;
138 }
139 }
140 s->full_update = 0;
141 if (y_start >= 0) {
142 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
143 }
144 if (page_max >= page_min) {
145 memory_region_reset_dirty(&s->vram_mem,
146 page_min, page_max - page_min + TARGET_PAGE_SIZE,
147 DIRTY_MEMORY_VGA);
148 }
149
150 if (s->regs[0] & CG3_CR_ENABLE_INTS) {
151 s->regs[1] |= CG3_SR_PENDING_INT;
152 qemu_irq_raise(s->irq);
153 }
154}
155
156static void cg3_invalidate_display(void *opaque)
157{
158 CG3State *s = opaque;
159
160 memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
161}
162
163static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
164{
165 CG3State *s = opaque;
166 int val;
167
168 switch (addr) {
169 case CG3_REG_BT458_ADDR:
170 case CG3_REG_BT458_COLMAP:
171 val = 0;
172 break;
173 case CG3_REG_FBC_CTRL:
174 val = s->regs[0];
175 break;
176 case CG3_REG_FBC_STATUS:
177
178 val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
179 break;
180 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
181 val = s->regs[addr - 0x10];
182 break;
183 default:
184 qemu_log_mask(LOG_UNIMP,
185 "cg3: Unimplemented register read "
186 "reg 0x%" HWADDR_PRIx " size 0x%x\n",
187 addr, size);
188 val = 0;
189 break;
190 }
191 DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
192 return val;
193}
194
195static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
196 unsigned size)
197{
198 CG3State *s = opaque;
199 uint8_t regval;
200 int i;
201
202 DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
203 val, addr, size);
204
205 switch (addr) {
206 case CG3_REG_BT458_ADDR:
207 s->dac_index = val;
208 s->dac_state = 0;
209 break;
210 case CG3_REG_BT458_COLMAP:
211
212 if (size == 1) {
213 val <<= 24;
214 }
215
216 for (i = 0; i < size; i++) {
217 regval = val >> 24;
218
219 switch (s->dac_state) {
220 case 0:
221 s->r[s->dac_index] = regval;
222 s->dac_state++;
223 break;
224 case 1:
225 s->g[s->dac_index] = regval;
226 s->dac_state++;
227 break;
228 case 2:
229 s->b[s->dac_index] = regval;
230
231 s->dac_index = (s->dac_index + 1) & 0xff;
232 default:
233 s->dac_state = 0;
234 break;
235 }
236 val <<= 8;
237 }
238 s->full_update = 1;
239 break;
240 case CG3_REG_FBC_CTRL:
241 s->regs[0] = val;
242 break;
243 case CG3_REG_FBC_STATUS:
244 if (s->regs[1] & CG3_SR_PENDING_INT) {
245
246 s->regs[1] &= ~CG3_SR_PENDING_INT;
247 qemu_irq_lower(s->irq);
248 }
249 break;
250 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
251 s->regs[addr - 0x10] = val;
252 break;
253 default:
254 qemu_log_mask(LOG_UNIMP,
255 "cg3: Unimplemented register write "
256 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
257 addr, size, val);
258 break;
259 }
260}
261
262static const MemoryRegionOps cg3_reg_ops = {
263 .read = cg3_reg_read,
264 .write = cg3_reg_write,
265 .endianness = DEVICE_NATIVE_ENDIAN,
266 .valid = {
267 .min_access_size = 1,
268 .max_access_size = 4,
269 },
270};
271
272static const GraphicHwOps cg3_ops = {
273 .invalidate = cg3_invalidate_display,
274 .gfx_update = cg3_update_display,
275};
276
277static void cg3_initfn(Object *obj)
278{
279 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
280 CG3State *s = CG3(obj);
281
282 memory_region_init_ram(&s->rom, NULL, "cg3.prom", FCODE_MAX_ROM_SIZE,
283 &error_abort);
284 memory_region_set_readonly(&s->rom, true);
285 sysbus_init_mmio(sbd, &s->rom);
286
287 memory_region_init_io(&s->reg, NULL, &cg3_reg_ops, s, "cg3.reg",
288 CG3_REG_SIZE);
289 sysbus_init_mmio(sbd, &s->reg);
290}
291
292static void cg3_realizefn(DeviceState *dev, Error **errp)
293{
294 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
295 CG3State *s = CG3(dev);
296 int ret;
297 char *fcode_filename;
298
299
300 vmstate_register_ram_global(&s->rom);
301 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
302 if (fcode_filename) {
303 ret = load_image_targphys(fcode_filename, s->prom_addr,
304 FCODE_MAX_ROM_SIZE);
305 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
306 error_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
307 }
308 }
309
310 memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size,
311 &error_abort);
312 vmstate_register_ram_global(&s->vram_mem);
313 sysbus_init_mmio(sbd, &s->vram_mem);
314
315 sysbus_init_irq(sbd, &s->irq);
316
317 s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s);
318 qemu_console_resize(s->con, s->width, s->height);
319}
320
321static int vmstate_cg3_post_load(void *opaque, int version_id)
322{
323 CG3State *s = opaque;
324
325 cg3_invalidate_display(s);
326
327 return 0;
328}
329
330static const VMStateDescription vmstate_cg3 = {
331 .name = "cg3",
332 .version_id = 1,
333 .minimum_version_id = 1,
334 .post_load = vmstate_cg3_post_load,
335 .fields = (VMStateField[]) {
336 VMSTATE_UINT16(height, CG3State),
337 VMSTATE_UINT16(width, CG3State),
338 VMSTATE_UINT16(depth, CG3State),
339 VMSTATE_BUFFER(r, CG3State),
340 VMSTATE_BUFFER(g, CG3State),
341 VMSTATE_BUFFER(b, CG3State),
342 VMSTATE_UINT8(dac_index, CG3State),
343 VMSTATE_UINT8(dac_state, CG3State),
344 VMSTATE_END_OF_LIST()
345 }
346};
347
348static void cg3_reset(DeviceState *d)
349{
350 CG3State *s = CG3(d);
351
352
353 memset(s->r, 0, 256);
354 memset(s->g, 0, 256);
355 memset(s->b, 0, 256);
356
357 s->dac_state = 0;
358 s->full_update = 1;
359 qemu_irq_lower(s->irq);
360}
361
362static Property cg3_properties[] = {
363 DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1),
364 DEFINE_PROP_UINT16("width", CG3State, width, -1),
365 DEFINE_PROP_UINT16("height", CG3State, height, -1),
366 DEFINE_PROP_UINT16("depth", CG3State, depth, -1),
367 DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1),
368 DEFINE_PROP_END_OF_LIST(),
369};
370
371static void cg3_class_init(ObjectClass *klass, void *data)
372{
373 DeviceClass *dc = DEVICE_CLASS(klass);
374
375 dc->realize = cg3_realizefn;
376 dc->reset = cg3_reset;
377 dc->vmsd = &vmstate_cg3;
378 dc->props = cg3_properties;
379}
380
381static const TypeInfo cg3_info = {
382 .name = TYPE_CG3,
383 .parent = TYPE_SYS_BUS_DEVICE,
384 .instance_size = sizeof(CG3State),
385 .instance_init = cg3_initfn,
386 .class_init = cg3_class_init,
387};
388
389static void cg3_register_types(void)
390{
391 type_register_static(&cg3_info);
392}
393
394type_init(cg3_register_types)
395
