LXR qemu/hw/misc/puv3

   1/*
   2 * Power Management device simulation in PKUnity SoC
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#include "hw/hw.h"
  12#include "hw/sysbus.h"
  13
  14#undef DEBUG_PUV3
  15#include "hw/unicore32/puv3.h"
  16
  17#define TYPE_PUV3_PM "puv3_pm"
  18#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
  19
  20typedef struct PUV3PMState {
  21    SysBusDevice parent_obj;
  22
  23    MemoryRegion iomem;
  24
  25    uint32_t reg_PMCR;
  26    uint32_t reg_PCGR;
  27    uint32_t reg_PLL_SYS_CFG;
  28    uint32_t reg_PLL_DDR_CFG;
  29    uint32_t reg_PLL_VGA_CFG;
  30    uint32_t reg_DIVCFG;
  31} PUV3PMState;
  32
  33static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
  34        unsigned size)
  35{
  36    PUV3PMState *s = opaque;
  37    uint32_t ret = 0;
  38
  39    switch (offset) {
  40    case 0x14:
  41        ret = s->reg_PCGR;
  42        break;
  43    case 0x18:
  44        ret = s->reg_PLL_SYS_CFG;
  45        break;
  46    case 0x1c:
  47        ret = s->reg_PLL_DDR_CFG;
  48        break;
  49    case 0x20:
  50        ret = s->reg_PLL_VGA_CFG;
  51        break;
  52    case 0x24:
  53        ret = s->reg_DIVCFG;
  54        break;
  55    case 0x28: /* PLL SYS STATUS */
  56        ret = 0x00002401;
  57        break;
  58    case 0x2c: /* PLL DDR STATUS */
  59        ret = 0x00100c00;
  60        break;
  61    case 0x30: /* PLL VGA STATUS */
  62        ret = 0x00003801;
  63        break;
  64    case 0x34: /* DIV STATUS */
  65        ret = 0x22f52015;
  66        break;
  67    case 0x38: /* SW RESET */
  68        ret = 0x0;
  69        break;
  70    case 0x44: /* PLL DFC DONE */
  71        ret = 0x7;
  72        break;
  73    default:
  74        DPRINTF("Bad offset 0x%x\n", offset);
  75    }
  76    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  77
  78    return ret;
  79}
  80
  81static void puv3_pm_write(void *opaque, hwaddr offset,
  82        uint64_t value, unsigned size)
  83{
  84    PUV3PMState *s = opaque;
  85
  86    switch (offset) {
  87    case 0x0:
  88        s->reg_PMCR = value;
  89        break;
  90    case 0x14:
  91        s->reg_PCGR = value;
  92        break;
  93    case 0x18:
  94        s->reg_PLL_SYS_CFG = value;
  95        break;
  96    case 0x1c:
  97        s->reg_PLL_DDR_CFG = value;
  98        break;
  99    case 0x20:
 100        s->reg_PLL_VGA_CFG = value;
 101        break;
 102    case 0x24:
 103    case 0x38:
 104        break;
 105    default:
 106        DPRINTF("Bad offset 0x%x\n", offset);
 107    }
 108    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
 109}
 110
 111static const MemoryRegionOps puv3_pm_ops = {
 112    .read = puv3_pm_read,
 113    .write = puv3_pm_write,
 114    .impl = {
 115        .min_access_size = 4,
 116        .max_access_size = 4,
 117    },
 118    .endianness = DEVICE_NATIVE_ENDIAN,
 119};
 120
 121static int puv3_pm_init(SysBusDevice *dev)
 122{
 123    PUV3PMState *s = PUV3_PM(dev);
 124
 125    s->reg_PCGR = 0x0;
 126
 127    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
 128            PUV3_REGS_OFFSET);
 129    sysbus_init_mmio(dev, &s->iomem);
 130
 131    return 0;
 132}
 133
 134static void puv3_pm_class_init(ObjectClass *klass, void *data)
 135{
 136    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 137
 138    sdc->init = puv3_pm_init;
 139}
 140
 141static const TypeInfo puv3_pm_info = {
 142    .name = TYPE_PUV3_PM,
 143    .parent = TYPE_SYS_BUS_DEVICE,
 144    .instance_size = sizeof(PUV3PMState),
 145    .class_init = puv3_pm_class_init,
 146};
 147
 148static void puv3_pm_register_type(void)
 149{
 150    type_register_static(&puv3_pm_info);
 151}
 152
 153type_init(puv3_pm_register_type)
 154