LXR qemu/hw/timer/puv3

   1/*
   2 * OSTimer device simulation in PKUnity SoC
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#include "hw/sysbus.h"
  12#include "hw/ptimer.h"
  13#include "qemu/main-loop.h"
  14
  15#undef DEBUG_PUV3
  16#include "hw/unicore32/puv3.h"
  17
  18#define TYPE_PUV3_OST "puv3_ost"
  19#define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
  20
  21/* puv3 ostimer implementation. */
  22typedef struct PUV3OSTState {
  23    SysBusDevice parent_obj;
  24
  25    MemoryRegion iomem;
  26    QEMUBH *bh;
  27    qemu_irq irq;
  28    ptimer_state *ptimer;
  29
  30    uint32_t reg_OSMR0;
  31    uint32_t reg_OSCR;
  32    uint32_t reg_OSSR;
  33    uint32_t reg_OIER;
  34} PUV3OSTState;
  35
  36static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  37        unsigned size)
  38{
  39    PUV3OSTState *s = opaque;
  40    uint32_t ret = 0;
  41
  42    switch (offset) {
  43    case 0x10: /* Counter Register */
  44        ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  45        break;
  46    case 0x14: /* Status Register */
  47        ret = s->reg_OSSR;
  48        break;
  49    case 0x1c: /* Interrupt Enable Register */
  50        ret = s->reg_OIER;
  51        break;
  52    default:
  53        DPRINTF("Bad offset %x\n", (int)offset);
  54    }
  55    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  56    return ret;
  57}
  58
  59static void puv3_ost_write(void *opaque, hwaddr offset,
  60        uint64_t value, unsigned size)
  61{
  62    PUV3OSTState *s = opaque;
  63
  64    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  65    switch (offset) {
  66    case 0x00: /* Match Register 0 */
  67        s->reg_OSMR0 = value;
  68        if (s->reg_OSMR0 > s->reg_OSCR) {
  69            ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  70        } else {
  71            ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  72                    (0xffffffff - s->reg_OSCR));
  73        }
  74        ptimer_run(s->ptimer, 2);
  75        break;
  76    case 0x14: /* Status Register */
  77        assert(value == 0);
  78        if (s->reg_OSSR) {
  79            s->reg_OSSR = value;
  80            qemu_irq_lower(s->irq);
  81        }
  82        break;
  83    case 0x1c: /* Interrupt Enable Register */
  84        s->reg_OIER = value;
  85        break;
  86    default:
  87        DPRINTF("Bad offset %x\n", (int)offset);
  88    }
  89}
  90
  91static const MemoryRegionOps puv3_ost_ops = {
  92    .read = puv3_ost_read,
  93    .write = puv3_ost_write,
  94    .impl = {
  95        .min_access_size = 4,
  96        .max_access_size = 4,
  97    },
  98    .endianness = DEVICE_NATIVE_ENDIAN,
  99};
 100
 101static void puv3_ost_tick(void *opaque)
 102{
 103    PUV3OSTState *s = opaque;
 104
 105    DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 106            s->reg_OSCR, s->reg_OSMR0);
 107
 108    s->reg_OSCR = s->reg_OSMR0;
 109    if (s->reg_OIER) {
 110        s->reg_OSSR = 1;
 111        qemu_irq_raise(s->irq);
 112    }
 113}
 114
 115static int puv3_ost_init(SysBusDevice *dev)
 116{
 117    PUV3OSTState *s = PUV3_OST(dev);
 118
 119    s->reg_OIER = 0;
 120    s->reg_OSSR = 0;
 121    s->reg_OSMR0 = 0;
 122    s->reg_OSCR = 0;
 123
 124    sysbus_init_irq(dev, &s->irq);
 125
 126    s->bh = qemu_bh_new(puv3_ost_tick, s);
 127    s->ptimer = ptimer_init(s->bh);
 128    ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 129
 130    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
 131            PUV3_REGS_OFFSET);
 132    sysbus_init_mmio(dev, &s->iomem);
 133
 134    return 0;
 135}
 136
 137static void puv3_ost_class_init(ObjectClass *klass, void *data)
 138{
 139    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 140
 141    sdc->init = puv3_ost_init;
 142}
 143
 144static const TypeInfo puv3_ost_info = {
 145    .name = TYPE_PUV3_OST,
 146    .parent = TYPE_SYS_BUS_DEVICE,
 147    .instance_size = sizeof(PUV3OSTState),
 148    .class_init = puv3_ost_class_init,
 149};
 150
 151static void puv3_ost_register_type(void)
 152{
 153    type_register_static(&puv3_ost_info);
 154}
 155
 156type_init(puv3_ost_register_type)
 157