1/* 2 * q35.h 3 * 4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/> 20 */ 21 22#ifndef HW_Q35_H 23#define HW_Q35_H 24 25#include "hw/hw.h" 26#include "qemu/range.h" 27#include "hw/isa/isa.h" 28#include "hw/sysbus.h" 29#include "hw/i386/pc.h" 30#include "hw/isa/apm.h" 31#include "hw/pci/pci.h" 32#include "hw/pci/pcie_host.h" 33#include "hw/acpi/acpi.h" 34#include "hw/acpi/ich9.h" 35#include "hw/pci-host/pam.h" 36#include "hw/i386/intel_iommu.h" 37 38#define TYPE_Q35_HOST_DEVICE "q35-pcihost" 39#define Q35_HOST_DEVICE(obj) \ 40 OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE) 41 42#define TYPE_MCH_PCI_DEVICE "mch" 43#define MCH_PCI_DEVICE(obj) \ 44 OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE) 45 46typedef struct MCHPCIState { 47 /*< private >*/ 48 PCIDevice parent_obj; 49 /*< public >*/ 50 51 MemoryRegion *ram_memory; 52 MemoryRegion *pci_address_space; 53 MemoryRegion *system_memory; 54 MemoryRegion *address_space_io; 55 PAMMemoryRegion pam_regions[13]; 56 MemoryRegion smram_region; 57 PcPciInfo pci_info; 58 uint8_t smm_enabled; 59 ram_addr_t below_4g_mem_size; 60 ram_addr_t above_4g_mem_size; 61 uint64_t pci_hole64_size; 62 PcGuestInfo *guest_info; 63 uint32_t short_root_bus; 64 IntelIOMMUState *iommu; 65} MCHPCIState; 66 67typedef struct Q35PCIHost { 68 /*< private >*/ 69 PCIExpressHost parent_obj; 70 /*< public >*/ 71 72 MCHPCIState mch; 73} Q35PCIHost; 74 75#define Q35_MASK(bit, ms_bit, ls_bit) \ 76((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 77 78/* 79 * gmch part 80 */ 81 82/* PCI configuration */ 83#define MCH_HOST_BRIDGE "MCH" 84 85#define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8 86#define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc 87 88/* D0:F0 configuration space */ 89#define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0 90 91#define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */ 92#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ 93#define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 94#define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ 95#define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) 96#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) 97#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) 98#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) 99#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) 100#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1)) 101#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1)) 102#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1)) 103#define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1) 104 105#define MCH_HOST_BRIDGE_PAM_NB 7 106#define MCH_HOST_BRIDGE_PAM_SIZE 7 107#define MCH_HOST_BRIDGE_PAM0 0x90 108#define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000 109#define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */ 110#define MCH_HOST_BRIDGE_PAM1 0x91 111#define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000 112#define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000 113#define MCH_HOST_BRIDGE_PAM2 0x92 114#define MCH_HOST_BRIDGE_PAM3 0x93 115#define MCH_HOST_BRIDGE_PAM4 0x94 116#define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000 117#define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000 118#define MCH_HOST_BRIDGE_PAM5 0x95 119#define MCH_HOST_BRIDGE_PAM6 0x96 120#define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4)) 121#define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4)) 122#define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4)) 123#define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2) 124#define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1) 125#define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3) 126#define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2) 127#define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1) 128#define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3) 129 130#define MCH_HOST_BRIDGE_SMRAM 0x9d 131#define MCH_HOST_BRIDGE_SMRAM_SIZE 1 132#define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2) 133#define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) 134#define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) 135#define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) 136#define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3)) 137#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) 138#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */ 139#define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000 140#define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 141#define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 142#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 143 144#define MCH_HOST_BRIDGE_ESMRAMC 0x9e 145#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6)) 146#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5)) 147#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4)) 148#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3)) 149#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2)) 150#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1)) 151#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1)) 152#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) 153#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) 154#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1) 155 156/* D1:F0 PCIE* port*/ 157#define MCH_PCIE_DEV 1 158#define MCH_PCIE_FUNC 0 159 160uint64_t mch_mcfg_base(void); 161 162#endif /* HW_Q35_H */ 163