LXR qemu/target-cris/cpu.h

   1/*
   2 *  CRIS virtual CPU header
   3 *
   4 *  Copyright (c) 2007 AXIS Communications AB
   5 *  Written by Edgar E. Iglesias
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20#ifndef CPU_CRIS_H
  21#define CPU_CRIS_H
  22
  23#include "config.h"
  24#include "qemu-common.h"
  25
  26#define TARGET_LONG_BITS 32
  27
  28#define CPUArchState struct CPUCRISState
  29
  30#include "exec/cpu-defs.h"
  31
  32#define ELF_MACHINE     EM_CRIS
  33
  34#define EXCP_NMI        1
  35#define EXCP_GURU       2
  36#define EXCP_BUSFAULT   3
  37#define EXCP_IRQ        4
  38#define EXCP_BREAK      5
  39
  40/* CRIS-specific interrupt pending bits.  */
  41#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  42
  43/* CRUS CPU device objects interrupt lines.  */
  44#define CRIS_CPU_IRQ 0
  45#define CRIS_CPU_NMI 1
  46
  47/* Register aliases. R0 - R15 */
  48#define R_FP  8
  49#define R_SP  14
  50#define R_ACR 15
  51
  52/* Support regs, P0 - P15  */
  53#define PR_BZ  0
  54#define PR_VR  1
  55#define PR_PID 2
  56#define PR_SRS 3
  57#define PR_WZ  4
  58#define PR_EXS 5
  59#define PR_EDA 6
  60#define PR_PREFIX 6    /* On CRISv10 P6 is reserved, we use it as prefix.  */
  61#define PR_MOF 7
  62#define PR_DZ  8
  63#define PR_EBP 9
  64#define PR_ERP 10
  65#define PR_SRP 11
  66#define PR_NRP 12
  67#define PR_CCS 13
  68#define PR_USP 14
  69#define PRV10_BRP 14
  70#define PR_SPC 15
  71
  72/* CPU flags.  */
  73#define Q_FLAG 0x80000000
  74#define M_FLAG_V32 0x40000000
  75#define PFIX_FLAG 0x800      /* CRISv10 Only.  */
  76#define F_FLAG_V10 0x400
  77#define P_FLAG_V10 0x200
  78#define S_FLAG 0x200
  79#define R_FLAG 0x100
  80#define P_FLAG 0x80
  81#define M_FLAG_V10 0x80
  82#define U_FLAG 0x40
  83#define I_FLAG 0x20
  84#define X_FLAG 0x10
  85#define N_FLAG 0x08
  86#define Z_FLAG 0x04
  87#define V_FLAG 0x02
  88#define C_FLAG 0x01
  89#define ALU_FLAGS 0x1F
  90
  91/* Condition codes.  */
  92#define CC_CC   0
  93#define CC_CS   1
  94#define CC_NE   2
  95#define CC_EQ   3
  96#define CC_VC   4
  97#define CC_VS   5
  98#define CC_PL   6
  99#define CC_MI   7
 100#define CC_LS   8
 101#define CC_HI   9
 102#define CC_GE  10
 103#define CC_LT  11
 104#define CC_GT  12
 105#define CC_LE  13
 106#define CC_A   14
 107#define CC_P   15
 108
 109#define NB_MMU_MODES 2
 110
 111typedef struct CPUCRISState {
 112        uint32_t regs[16];
 113        /* P0 - P15 are referred to as special registers in the docs.  */
 114        uint32_t pregs[16];
 115
 116        /* Pseudo register for the PC. Not directly accessible on CRIS.  */
 117        uint32_t pc;
 118
 119        /* Pseudo register for the kernel stack.  */
 120        uint32_t ksp;
 121
 122        /* Branch.  */
 123        int dslot;
 124        int btaken;
 125        uint32_t btarget;
 126
 127        /* Condition flag tracking.  */
 128        uint32_t cc_op;
 129        uint32_t cc_mask;
 130        uint32_t cc_dest;
 131        uint32_t cc_src;
 132        uint32_t cc_result;
 133        /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 134        int cc_size;
 135        /* X flag at the time of cc snapshot.  */
 136        int cc_x;
 137
 138        /* CRIS has certain insns that lockout interrupts.  */
 139        int locked_irq;
 140        int interrupt_vector;
 141        int fault_vector;
 142        int trap_vector;
 143
 144        /* FIXME: add a check in the translator to avoid writing to support
 145           register sets beyond the 4th. The ISA allows up to 256! but in
 146           practice there is no core that implements more than 4.
 147
 148           Support function registers are used to control units close to the
 149           core. Accesses do not pass down the normal hierarchy.
 150        */
 151        uint32_t sregs[4][16];
 152
 153        /* Linear feedback shift reg in the mmu. Used to provide pseudo
 154           randomness for the 'hint' the mmu gives to sw for chosing valid
 155           sets on TLB refills.  */
 156        uint32_t mmu_rand_lfsr;
 157
 158        /*
 159         * We just store the stores to the tlbset here for later evaluation
 160         * when the hw needs access to them.
 161         *
 162         * One for I and another for D.
 163         */
 164        struct
 165        {
 166                uint32_t hi;
 167                uint32_t lo;
 168        } tlbsets[2][4][16];
 169
 170        CPU_COMMON
 171
 172    /* Members from load_info on are preserved across resets.  */
 173    void *load_info;
 174} CPUCRISState;
 175
 176#include "cpu-qom.h"
 177
 178CRISCPU *cpu_cris_init(const char *cpu_model);
 179int cpu_cris_exec(CPUCRISState *s);
 180/* you can call this signal handler from your SIGBUS and SIGSEGV
 181   signal handlers to inform the virtual CPU of exceptions. non zero
 182   is returned if the signal was handled by the virtual CPU.  */
 183int cpu_cris_signal_handler(int host_signum, void *pinfo,
 184                           void *puc);
 185
 186void cris_initialize_tcg(void);
 187void cris_initialize_crisv10_tcg(void);
 188
 189enum {
 190    CC_OP_DYNAMIC, /* Use env->cc_op  */
 191    CC_OP_FLAGS,
 192    CC_OP_CMP,
 193    CC_OP_MOVE,
 194    CC_OP_ADD,
 195    CC_OP_ADDC,
 196    CC_OP_MCP,
 197    CC_OP_ADDU,
 198    CC_OP_SUB,
 199    CC_OP_SUBU,
 200    CC_OP_NEG,
 201    CC_OP_BTST,
 202    CC_OP_MULS,
 203    CC_OP_MULU,
 204    CC_OP_DSTEP,
 205    CC_OP_MSTEP,
 206    CC_OP_BOUND,
 207
 208    CC_OP_OR,
 209    CC_OP_AND,
 210    CC_OP_XOR,
 211    CC_OP_LSL,
 212    CC_OP_LSR,
 213    CC_OP_ASR,
 214    CC_OP_LZ
 215};
 216
 217/* CRIS uses 8k pages.  */
 218#define TARGET_PAGE_BITS 13
 219#define MMAP_SHIFT TARGET_PAGE_BITS
 220
 221#define TARGET_PHYS_ADDR_SPACE_BITS 32
 222#define TARGET_VIRT_ADDR_SPACE_BITS 32
 223
 224#define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model))
 225
 226#define cpu_exec cpu_cris_exec
 227#define cpu_gen_code cpu_cris_gen_code
 228#define cpu_signal_handler cpu_cris_signal_handler
 229
 230#define CPU_SAVE_VERSION 1
 231
 232/* MMU modes definitions */
 233#define MMU_MODE0_SUFFIX _kernel
 234#define MMU_MODE1_SUFFIX _user
 235#define MMU_USER_IDX 1
 236static inline int cpu_mmu_index (CPUCRISState *env)
 237{
 238        return !!(env->pregs[PR_CCS] & U_FLAG);
 239}
 240
 241int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 242                              int mmu_idx);
 243
 244/* Support function regs.  */
 245#define SFR_RW_GC_CFG      0][0
 246#define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 247#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 248#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 249#define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 250#define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 251#define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 252#define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 253
 254#include "exec/cpu-all.h"
 255
 256static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
 257                                        target_ulong *cs_base, int *flags)
 258{
 259    *pc = env->pc;
 260    *cs_base = 0;
 261    *flags = env->dslot |
 262            (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
 263                                     | X_FLAG | PFIX_FLAG));
 264}
 265
 266#define cpu_list cris_cpu_list
 267void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 268
 269#include "exec/exec-all.h"
 270
 271#endif
 272