LXR qemu/target-unicore32/softmmu.c

   1/*
   2 * Softmmu related functions
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#ifdef CONFIG_USER_ONLY
  12#error This file only exist under softmmu circumstance
  13#endif
  14
  15#include <cpu.h>
  16
  17#undef DEBUG_UC32
  18
  19#ifdef DEBUG_UC32
  20#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
  21#else
  22#define DPRINTF(fmt, ...) do {} while (0)
  23#endif
  24
  25#define SUPERPAGE_SIZE             (1 << 22)
  26#define UC32_PAGETABLE_READ        (1 << 8)
  27#define UC32_PAGETABLE_WRITE       (1 << 7)
  28#define UC32_PAGETABLE_EXEC        (1 << 6)
  29#define UC32_PAGETABLE_EXIST       (1 << 2)
  30#define PAGETABLE_TYPE(x)          ((x) & 3)
  31
  32
  33/* Map CPU modes onto saved register banks.  */
  34static inline int bank_number(CPUUniCore32State *env, int mode)
  35{
  36    UniCore32CPU *cpu = uc32_env_get_cpu(env);
  37
  38    switch (mode) {
  39    case ASR_MODE_USER:
  40    case ASR_MODE_SUSR:
  41        return 0;
  42    case ASR_MODE_PRIV:
  43        return 1;
  44    case ASR_MODE_TRAP:
  45        return 2;
  46    case ASR_MODE_EXTN:
  47        return 3;
  48    case ASR_MODE_INTR:
  49        return 4;
  50    }
  51    cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
  52    return -1;
  53}
  54
  55void switch_mode(CPUUniCore32State *env, int mode)
  56{
  57    int old_mode;
  58    int i;
  59
  60    old_mode = env->uncached_asr & ASR_M;
  61    if (mode == old_mode) {
  62        return;
  63    }
  64
  65    i = bank_number(env, old_mode);
  66    env->banked_r29[i] = env->regs[29];
  67    env->banked_r30[i] = env->regs[30];
  68    env->banked_bsr[i] = env->bsr;
  69
  70    i = bank_number(env, mode);
  71    env->regs[29] = env->banked_r29[i];
  72    env->regs[30] = env->banked_r30[i];
  73    env->bsr = env->banked_bsr[i];
  74}
  75
  76/* Handle a CPU exception.  */
  77void uc32_cpu_do_interrupt(CPUState *cs)
  78{
  79    UniCore32CPU *cpu = UNICORE32_CPU(cs);
  80    CPUUniCore32State *env = &cpu->env;
  81    uint32_t addr;
  82    int new_mode;
  83
  84    switch (cs->exception_index) {
  85    case UC32_EXCP_PRIV:
  86        new_mode = ASR_MODE_PRIV;
  87        addr = 0x08;
  88        break;
  89    case UC32_EXCP_ITRAP:
  90        DPRINTF("itrap happened at %x\n", env->regs[31]);
  91        new_mode = ASR_MODE_TRAP;
  92        addr = 0x0c;
  93        break;
  94    case UC32_EXCP_DTRAP:
  95        DPRINTF("dtrap happened at %x\n", env->regs[31]);
  96        new_mode = ASR_MODE_TRAP;
  97        addr = 0x10;
  98        break;
  99    case UC32_EXCP_INTR:
 100        new_mode = ASR_MODE_INTR;
 101        addr = 0x18;
 102        break;
 103    default:
 104        cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
 105        return;
 106    }
 107    /* High vectors.  */
 108    if (env->cp0.c1_sys & (1 << 13)) {
 109        addr += 0xffff0000;
 110    }
 111
 112    switch_mode(env, new_mode);
 113    env->bsr = cpu_asr_read(env);
 114    env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
 115    env->uncached_asr |= ASR_I;
 116    /* The PC already points to the proper instruction.  */
 117    env->regs[30] = env->regs[31];
 118    env->regs[31] = addr;
 119    cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 120}
 121
 122static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
 123        int access_type, int is_user, uint32_t *phys_ptr, int *prot,
 124        target_ulong *page_size)
 125{
 126    UniCore32CPU *cpu = uc32_env_get_cpu(env);
 127    CPUState *cs = CPU(cpu);
 128    int code;
 129    uint32_t table;
 130    uint32_t desc;
 131    uint32_t phys_addr;
 132
 133    /* Pagetable walk.  */
 134    /* Lookup l1 descriptor.  */
 135    table = env->cp0.c2_base & 0xfffff000;
 136    table |= (address >> 20) & 0xffc;
 137    desc = ldl_phys(cs->as, table);
 138    code = 0;
 139    switch (PAGETABLE_TYPE(desc)) {
 140    case 3:
 141        /* Superpage  */
 142        if (!(desc & UC32_PAGETABLE_EXIST)) {
 143            code = 0x0b; /* superpage miss */
 144            goto do_fault;
 145        }
 146        phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
 147        *page_size = SUPERPAGE_SIZE;
 148        break;
 149    case 0:
 150        /* Lookup l2 entry.  */
 151        if (is_user) {
 152            DPRINTF("PGD address %x, desc %x\n", table, desc);
 153        }
 154        if (!(desc & UC32_PAGETABLE_EXIST)) {
 155            code = 0x05; /* second pagetable miss */
 156            goto do_fault;
 157        }
 158        table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
 159        desc = ldl_phys(cs->as, table);
 160        /* 4k page.  */
 161        if (is_user) {
 162            DPRINTF("PTE address %x, desc %x\n", table, desc);
 163        }
 164        if (!(desc & UC32_PAGETABLE_EXIST)) {
 165            code = 0x08; /* page miss */
 166            goto do_fault;
 167        }
 168        switch (PAGETABLE_TYPE(desc)) {
 169        case 0:
 170            phys_addr = (desc & 0xfffff000) | (address & 0xfff);
 171            *page_size = TARGET_PAGE_SIZE;
 172            break;
 173        default:
 174            cpu_abort(CPU(cpu), "wrong page type!");
 175        }
 176        break;
 177    default:
 178        cpu_abort(CPU(cpu), "wrong page type!");
 179    }
 180
 181    *phys_ptr = phys_addr;
 182    *prot = 0;
 183    /* Check access permissions.  */
 184    if (desc & UC32_PAGETABLE_READ) {
 185        *prot |= PAGE_READ;
 186    } else {
 187        if (is_user && (access_type == 0)) {
 188            code = 0x11; /* access unreadable area */
 189            goto do_fault;
 190        }
 191    }
 192
 193    if (desc & UC32_PAGETABLE_WRITE) {
 194        *prot |= PAGE_WRITE;
 195    } else {
 196        if (is_user && (access_type == 1)) {
 197            code = 0x12; /* access unwritable area */
 198            goto do_fault;
 199        }
 200    }
 201
 202    if (desc & UC32_PAGETABLE_EXEC) {
 203        *prot |= PAGE_EXEC;
 204    } else {
 205        if (is_user && (access_type == 2)) {
 206            code = 0x13; /* access unexecutable area */
 207            goto do_fault;
 208        }
 209    }
 210
 211do_fault:
 212    return code;
 213}
 214
 215int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
 216                              int access_type, int mmu_idx)
 217{
 218    UniCore32CPU *cpu = UNICORE32_CPU(cs);
 219    CPUUniCore32State *env = &cpu->env;
 220    uint32_t phys_addr;
 221    target_ulong page_size;
 222    int prot;
 223    int ret, is_user;
 224
 225    ret = 1;
 226    is_user = mmu_idx == MMU_USER_IDX;
 227
 228    if ((env->cp0.c1_sys & 1) == 0) {
 229        /* MMU disabled.  */
 230        phys_addr = address;
 231        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 232        page_size = TARGET_PAGE_SIZE;
 233        ret = 0;
 234    } else {
 235        if ((address & (1 << 31)) || (is_user)) {
 236            ret = get_phys_addr_ucv2(env, address, access_type, is_user,
 237                                    &phys_addr, &prot, &page_size);
 238            if (is_user) {
 239                DPRINTF("user space access: ret %x, address %" VADDR_PRIx ", "
 240                        "access_type %x, phys_addr %x, prot %x\n",
 241                        ret, address, access_type, phys_addr, prot);
 242            }
 243        } else {
 244            /*IO memory */
 245            phys_addr = address | (1 << 31);
 246            prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 247            page_size = TARGET_PAGE_SIZE;
 248            ret = 0;
 249        }
 250    }
 251
 252    if (ret == 0) {
 253        /* Map a single page.  */
 254        phys_addr &= TARGET_PAGE_MASK;
 255        address &= TARGET_PAGE_MASK;
 256        tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
 257        return 0;
 258    }
 259
 260    env->cp0.c3_faultstatus = ret;
 261    env->cp0.c4_faultaddr = address;
 262    if (access_type == 2) {
 263        cs->exception_index = UC32_EXCP_ITRAP;
 264    } else {
 265        cs->exception_index = UC32_EXCP_DTRAP;
 266    }
 267    return ret;
 268}
 269
 270hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 271{
 272    UniCore32CPU *cpu = UNICORE32_CPU(cs);
 273
 274    cpu_abort(CPU(cpu), "%s not supported yet\n", __func__);
 275    return addr;
 276}
 277