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22#include <inttypes.h>
23
24#include "qemu-common.h"
25#include "qemu/timer.h"
26#include "sysemu/watchdog.h"
27#include "hw/hw.h"
28#include "hw/pci/pci.h"
29
30
31
32#ifdef I6300ESB_DEBUG
33#define i6300esb_debug(fs,...) \
34 fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
35#else
36#define i6300esb_debug(fs,...)
37#endif
38
39
40#define ESB_CONFIG_REG 0x60
41#define ESB_LOCK_REG 0x68
42
43
44#define ESB_TIMER1_REG 0x00
45#define ESB_TIMER2_REG 0x04
46#define ESB_GINTSR_REG 0x08
47#define ESB_RELOAD_REG 0x0c
48
49
50#define ESB_WDT_FUNC (0x01 << 2)
51#define ESB_WDT_ENABLE (0x01 << 1)
52#define ESB_WDT_LOCK (0x01 << 0)
53
54
55#define ESB_WDT_REBOOT (0x01 << 5)
56#define ESB_WDT_FREQ (0x01 << 2)
57#define ESB_WDT_INTTYPE (0x11 << 0)
58
59
60#define ESB_WDT_RELOAD (0x01 << 8)
61
62
63#define ESB_UNLOCK1 0x80
64#define ESB_UNLOCK2 0x86
65
66
67struct I6300State {
68 PCIDevice dev;
69 MemoryRegion io_mem;
70
71 int reboot_enabled;
72
73
74
75 int clock_scale;
76#define CLOCK_SCALE_1KHZ 0
77#define CLOCK_SCALE_1MHZ 1
78
79 int int_type;
80#define INT_TYPE_IRQ 0
81#define INT_TYPE_SMI 2
82#define INT_TYPE_DISABLED 3
83
84 int free_run;
85 int locked;
86 int enabled;
87
88 QEMUTimer *timer;
89
90 uint32_t timer1_preload;
91 uint32_t timer2_preload;
92 int stage;
93
94 int unlock_state;
95
96
97
98
99 int previous_reboot_flag;
100
101
102};
103
104typedef struct I6300State I6300State;
105
106
107
108
109static void i6300esb_restart_timer(I6300State *d, int stage)
110{
111 int64_t timeout;
112
113 if (!d->enabled)
114 return;
115
116 d->stage = stage;
117
118 if (d->stage <= 1)
119 timeout = d->timer1_preload;
120 else
121 timeout = d->timer2_preload;
122
123 if (d->clock_scale == CLOCK_SCALE_1KHZ)
124 timeout <<= 15;
125 else
126 timeout <<= 5;
127
128
129
130
131
132
133
134
135 timeout = muldiv64(get_ticks_per_sec(), timeout, 33000000);
136
137 i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
138
139 timer_mod(d->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
140}
141
142
143static void i6300esb_disable_timer(I6300State *d)
144{
145 i6300esb_debug("timer disabled\n");
146
147 timer_del(d->timer);
148}
149
150static void i6300esb_reset(DeviceState *dev)
151{
152 PCIDevice *pdev = PCI_DEVICE(dev);
153 I6300State *d = DO_UPCAST(I6300State, dev, pdev);
154
155 i6300esb_debug("I6300State = %p\n", d);
156
157 i6300esb_disable_timer(d);
158
159
160
161 d->reboot_enabled = 1;
162 d->clock_scale = CLOCK_SCALE_1KHZ;
163 d->int_type = INT_TYPE_IRQ;
164 d->free_run = 0;
165 d->locked = 0;
166 d->enabled = 0;
167 d->timer1_preload = 0xfffff;
168 d->timer2_preload = 0xfffff;
169 d->stage = 1;
170 d->unlock_state = 0;
171}
172
173
174
175
176
177
178
179
180static void i6300esb_timer_expired(void *vp)
181{
182 I6300State *d = vp;
183
184 i6300esb_debug("stage %d\n", d->stage);
185
186 if (d->stage == 1) {
187
188 switch (d->int_type) {
189 case INT_TYPE_IRQ:
190 fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
191 break;
192 case INT_TYPE_SMI:
193 fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
194 break;
195 }
196
197
198 i6300esb_restart_timer(d, 2);
199 } else {
200
201 if (d->reboot_enabled) {
202 d->previous_reboot_flag = 1;
203 watchdog_perform_action();
204 i6300esb_reset(&d->dev.qdev);
205 }
206
207
208 if (d->free_run)
209 i6300esb_restart_timer(d, 1);
210 }
211}
212
213static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
214 uint32_t data, int len)
215{
216 I6300State *d = DO_UPCAST(I6300State, dev, dev);
217 int old;
218
219 i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
220
221 if (addr == ESB_CONFIG_REG && len == 2) {
222 d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
223 d->clock_scale =
224 (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
225 d->int_type = (data & ESB_WDT_INTTYPE);
226 } else if (addr == ESB_LOCK_REG && len == 1) {
227 if (!d->locked) {
228 d->locked = (data & ESB_WDT_LOCK) != 0;
229 d->free_run = (data & ESB_WDT_FUNC) != 0;
230 old = d->enabled;
231 d->enabled = (data & ESB_WDT_ENABLE) != 0;
232 if (!old && d->enabled)
233 i6300esb_restart_timer(d, 1);
234 else if (!d->enabled)
235 i6300esb_disable_timer(d);
236 }
237 } else {
238 pci_default_write_config(dev, addr, data, len);
239 }
240}
241
242static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
243{
244 I6300State *d = DO_UPCAST(I6300State, dev, dev);
245 uint32_t data;
246
247 i6300esb_debug ("addr = %x, len = %d\n", addr, len);
248
249 if (addr == ESB_CONFIG_REG && len == 2) {
250 data =
251 (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
252 (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
253 d->int_type;
254 return data;
255 } else if (addr == ESB_LOCK_REG && len == 1) {
256 data =
257 (d->free_run ? ESB_WDT_FUNC : 0) |
258 (d->locked ? ESB_WDT_LOCK : 0) |
259 (d->enabled ? ESB_WDT_ENABLE : 0);
260 return data;
261 } else {
262 return pci_default_read_config(dev, addr, len);
263 }
264}
265
266static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
267{
268 i6300esb_debug ("addr = %x\n", (int) addr);
269
270 return 0;
271}
272
273static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
274{
275 uint32_t data = 0;
276 I6300State *d = vp;
277
278 i6300esb_debug("addr = %x\n", (int) addr);
279
280 if (addr == 0xc) {
281
282
283
284
285 data = d->previous_reboot_flag ? 0x1200 : 0;
286 }
287
288 return data;
289}
290
291static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
292{
293 i6300esb_debug("addr = %x\n", (int) addr);
294
295 return 0;
296}
297
298static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
299{
300 I6300State *d = vp;
301
302 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
303
304 if (addr == 0xc && val == 0x80)
305 d->unlock_state = 1;
306 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
307 d->unlock_state = 2;
308}
309
310static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
311{
312 I6300State *d = vp;
313
314 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
315
316 if (addr == 0xc && val == 0x80)
317 d->unlock_state = 1;
318 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
319 d->unlock_state = 2;
320 else {
321 if (d->unlock_state == 2) {
322 if (addr == 0xc) {
323 if ((val & 0x100) != 0)
324
325
326
327 i6300esb_restart_timer(d, 1);
328
329
330
331
332
333 if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
334 d->previous_reboot_flag = 0;
335 }
336 }
337
338 d->unlock_state = 0;
339 }
340 }
341}
342
343static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
344{
345 I6300State *d = vp;
346
347 i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
348
349 if (addr == 0xc && val == 0x80)
350 d->unlock_state = 1;
351 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
352 d->unlock_state = 2;
353 else {
354 if (d->unlock_state == 2) {
355 if (addr == 0)
356 d->timer1_preload = val & 0xfffff;
357 else if (addr == 4)
358 d->timer2_preload = val & 0xfffff;
359
360 d->unlock_state = 0;
361 }
362 }
363}
364
365static const MemoryRegionOps i6300esb_ops = {
366 .old_mmio = {
367 .read = {
368 i6300esb_mem_readb,
369 i6300esb_mem_readw,
370 i6300esb_mem_readl,
371 },
372 .write = {
373 i6300esb_mem_writeb,
374 i6300esb_mem_writew,
375 i6300esb_mem_writel,
376 },
377 },
378 .endianness = DEVICE_LITTLE_ENDIAN,
379};
380
381static const VMStateDescription vmstate_i6300esb = {
382 .name = "i6300esb_wdt",
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397 .version_id = 10000,
398 .minimum_version_id = 1,
399 .fields = (VMStateField[]) {
400 VMSTATE_PCI_DEVICE(dev, I6300State),
401 VMSTATE_INT32(reboot_enabled, I6300State),
402 VMSTATE_INT32(clock_scale, I6300State),
403 VMSTATE_INT32(int_type, I6300State),
404 VMSTATE_INT32(free_run, I6300State),
405 VMSTATE_INT32(locked, I6300State),
406 VMSTATE_INT32(enabled, I6300State),
407 VMSTATE_TIMER_PTR(timer, I6300State),
408 VMSTATE_UINT32(timer1_preload, I6300State),
409 VMSTATE_UINT32(timer2_preload, I6300State),
410 VMSTATE_INT32(stage, I6300State),
411 VMSTATE_INT32(unlock_state, I6300State),
412 VMSTATE_INT32(previous_reboot_flag, I6300State),
413 VMSTATE_END_OF_LIST()
414 }
415};
416
417static void i6300esb_realize(PCIDevice *dev, Error **errp)
418{
419 I6300State *d = DO_UPCAST(I6300State, dev, dev);
420
421 i6300esb_debug("I6300State = %p\n", d);
422
423 d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d);
424 d->previous_reboot_flag = 0;
425
426 memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
427 "i6300esb", 0x10);
428 pci_register_bar(&d->dev, 0, 0, &d->io_mem);
429
430}
431
432static WatchdogTimerModel model = {
433 .wdt_name = "i6300esb",
434 .wdt_description = "Intel 6300ESB",
435};
436
437static void i6300esb_class_init(ObjectClass *klass, void *data)
438{
439 DeviceClass *dc = DEVICE_CLASS(klass);
440 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
441
442 k->config_read = i6300esb_config_read;
443 k->config_write = i6300esb_config_write;
444 k->realize = i6300esb_realize;
445 k->vendor_id = PCI_VENDOR_ID_INTEL;
446 k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
447 k->class_id = PCI_CLASS_SYSTEM_OTHER;
448 dc->reset = i6300esb_reset;
449 dc->vmsd = &vmstate_i6300esb;
450 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
451}
452
453static const TypeInfo i6300esb_info = {
454 .name = "i6300esb",
455 .parent = TYPE_PCI_DEVICE,
456 .instance_size = sizeof(I6300State),
457 .class_init = i6300esb_class_init,
458};
459
460static void i6300esb_register_types(void)
461{
462 watchdog_add_model(&model);
463 type_register_static(&i6300esb_info);
464}
465
466type_init(i6300esb_register_types)
467