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28#include "cpu.h"
29#include "exec/exec-all.h"
30#include "exec/gdbstub.h"
31#include "qemu/host-utils.h"
32#if !defined(CONFIG_USER_ONLY)
33#include "hw/loader.h"
34#endif
35
36static struct XtensaConfigList *xtensa_cores;
37
38static void xtensa_core_class_init(ObjectClass *oc, void *data)
39{
40 CPUClass *cc = CPU_CLASS(oc);
41 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
42 const XtensaConfig *config = data;
43
44 xcc->config = config;
45
46
47
48
49
50
51 cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
52}
53
54void xtensa_register_core(XtensaConfigList *node)
55{
56 TypeInfo type = {
57 .parent = TYPE_XTENSA_CPU,
58 .class_init = xtensa_core_class_init,
59 .class_data = (void *)node->config,
60 };
61
62 node->next = xtensa_cores;
63 xtensa_cores = node;
64 type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name);
65 type_register(&type);
66 g_free((gpointer)type.name);
67}
68
69static uint32_t check_hw_breakpoints(CPUXtensaState *env)
70{
71 unsigned i;
72
73 for (i = 0; i < env->config->ndbreak; ++i) {
74 if (env->cpu_watchpoint[i] &&
75 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
76 return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
77 }
78 }
79 return 0;
80}
81
82void xtensa_breakpoint_handler(CPUState *cs)
83{
84 XtensaCPU *cpu = XTENSA_CPU(cs);
85 CPUXtensaState *env = &cpu->env;
86
87 if (cs->watchpoint_hit) {
88 if (cs->watchpoint_hit->flags & BP_CPU) {
89 uint32_t cause;
90
91 cs->watchpoint_hit = NULL;
92 cause = check_hw_breakpoints(env);
93 if (cause) {
94 debug_exception_env(env, cause);
95 }
96 cpu_resume_from_signal(cs, NULL);
97 }
98 }
99}
100
101XtensaCPU *cpu_xtensa_init(const char *cpu_model)
102{
103 ObjectClass *oc;
104 XtensaCPU *cpu;
105 CPUXtensaState *env;
106
107 oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
108 if (oc == NULL) {
109 return NULL;
110 }
111
112 cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
113 env = &cpu->env;
114
115 xtensa_irq_init(env);
116
117 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
118
119 return cpu;
120}
121
122
123void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
124{
125 XtensaConfigList *core = xtensa_cores;
126 cpu_fprintf(f, "Available CPUs:\n");
127 for (; core; core = core->next) {
128 cpu_fprintf(f, " %s\n", core->config->name);
129 }
130}
131
132hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
133{
134 XtensaCPU *cpu = XTENSA_CPU(cs);
135 uint32_t paddr;
136 uint32_t page_size;
137 unsigned access;
138
139 if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
140 &paddr, &page_size, &access) == 0) {
141 return paddr;
142 }
143 if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
144 &paddr, &page_size, &access) == 0) {
145 return paddr;
146 }
147 return ~0;
148}
149
150static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
151{
152 if (xtensa_option_enabled(env->config,
153 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
154 return vector - env->config->vecbase + env->sregs[VECBASE];
155 } else {
156 return vector;
157 }
158}
159
160
161
162
163
164
165
166static void handle_interrupt(CPUXtensaState *env)
167{
168 int level = env->pending_irq_level;
169
170 if (level > xtensa_get_cintlevel(env) &&
171 level <= env->config->nlevel &&
172 (env->config->level_mask[level] &
173 env->sregs[INTSET] &
174 env->sregs[INTENABLE])) {
175 CPUState *cs = CPU(xtensa_env_get_cpu(env));
176
177 if (level > 1) {
178 env->sregs[EPC1 + level - 1] = env->pc;
179 env->sregs[EPS2 + level - 2] = env->sregs[PS];
180 env->sregs[PS] =
181 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
182 env->pc = relocated_vector(env,
183 env->config->interrupt_vector[level]);
184 } else {
185 env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
186
187 if (env->sregs[PS] & PS_EXCM) {
188 if (env->config->ndepc) {
189 env->sregs[DEPC] = env->pc;
190 } else {
191 env->sregs[EPC1] = env->pc;
192 }
193 cs->exception_index = EXC_DOUBLE;
194 } else {
195 env->sregs[EPC1] = env->pc;
196 cs->exception_index =
197 (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
198 }
199 env->sregs[PS] |= PS_EXCM;
200 }
201 env->exception_taken = 1;
202 }
203}
204
205void xtensa_cpu_do_interrupt(CPUState *cs)
206{
207 XtensaCPU *cpu = XTENSA_CPU(cs);
208 CPUXtensaState *env = &cpu->env;
209
210 if (cs->exception_index == EXC_IRQ) {
211 qemu_log_mask(CPU_LOG_INT,
212 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
213 "pc = %08x, a0 = %08x, ps = %08x, "
214 "intset = %08x, intenable = %08x, "
215 "ccount = %08x\n",
216 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
217 env->pc, env->regs[0], env->sregs[PS],
218 env->sregs[INTSET], env->sregs[INTENABLE],
219 env->sregs[CCOUNT]);
220 handle_interrupt(env);
221 }
222
223 switch (cs->exception_index) {
224 case EXC_WINDOW_OVERFLOW4:
225 case EXC_WINDOW_UNDERFLOW4:
226 case EXC_WINDOW_OVERFLOW8:
227 case EXC_WINDOW_UNDERFLOW8:
228 case EXC_WINDOW_OVERFLOW12:
229 case EXC_WINDOW_UNDERFLOW12:
230 case EXC_KERNEL:
231 case EXC_USER:
232 case EXC_DOUBLE:
233 case EXC_DEBUG:
234 qemu_log_mask(CPU_LOG_INT, "%s(%d) "
235 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
236 __func__, cs->exception_index,
237 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
238 if (env->config->exception_vector[cs->exception_index]) {
239 env->pc = relocated_vector(env,
240 env->config->exception_vector[cs->exception_index]);
241 env->exception_taken = 1;
242 } else {
243 qemu_log("%s(pc = %08x) bad exception_index: %d\n",
244 __func__, env->pc, cs->exception_index);
245 }
246 break;
247
248 case EXC_IRQ:
249 break;
250
251 default:
252 qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
253 __func__, env->pc, cs->exception_index);
254 break;
255 }
256 check_interrupts(env);
257}
258
259bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
260{
261 if (interrupt_request & CPU_INTERRUPT_HARD) {
262 cs->exception_index = EXC_IRQ;
263 xtensa_cpu_do_interrupt(cs);
264 return true;
265 }
266 return false;
267}
268
269static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
270 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
271{
272 unsigned wi, ei;
273
274 for (wi = 0; wi < tlb->nways; ++wi) {
275 for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
276 entry[wi][ei].asid = 0;
277 entry[wi][ei].variable = true;
278 }
279 }
280}
281
282static void reset_tlb_mmu_ways56(CPUXtensaState *env,
283 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
284{
285 if (!tlb->varway56) {
286 static const xtensa_tlb_entry way5[] = {
287 {
288 .vaddr = 0xd0000000,
289 .paddr = 0,
290 .asid = 1,
291 .attr = 7,
292 .variable = false,
293 }, {
294 .vaddr = 0xd8000000,
295 .paddr = 0,
296 .asid = 1,
297 .attr = 3,
298 .variable = false,
299 }
300 };
301 static const xtensa_tlb_entry way6[] = {
302 {
303 .vaddr = 0xe0000000,
304 .paddr = 0xf0000000,
305 .asid = 1,
306 .attr = 7,
307 .variable = false,
308 }, {
309 .vaddr = 0xf0000000,
310 .paddr = 0xf0000000,
311 .asid = 1,
312 .attr = 3,
313 .variable = false,
314 }
315 };
316 memcpy(entry[5], way5, sizeof(way5));
317 memcpy(entry[6], way6, sizeof(way6));
318 } else {
319 uint32_t ei;
320 for (ei = 0; ei < 8; ++ei) {
321 entry[6][ei].vaddr = ei << 29;
322 entry[6][ei].paddr = ei << 29;
323 entry[6][ei].asid = 1;
324 entry[6][ei].attr = 3;
325 }
326 }
327}
328
329static void reset_tlb_region_way0(CPUXtensaState *env,
330 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
331{
332 unsigned ei;
333
334 for (ei = 0; ei < 8; ++ei) {
335 entry[0][ei].vaddr = ei << 29;
336 entry[0][ei].paddr = ei << 29;
337 entry[0][ei].asid = 1;
338 entry[0][ei].attr = 2;
339 entry[0][ei].variable = true;
340 }
341}
342
343void reset_mmu(CPUXtensaState *env)
344{
345 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
346 env->sregs[RASID] = 0x04030201;
347 env->sregs[ITLBCFG] = 0;
348 env->sregs[DTLBCFG] = 0;
349 env->autorefill_idx = 0;
350 reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
351 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
352 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
353 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
354 } else {
355 reset_tlb_region_way0(env, env->itlb);
356 reset_tlb_region_way0(env, env->dtlb);
357 }
358}
359
360static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
361{
362 unsigned i;
363 for (i = 0; i < 4; ++i) {
364 if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
365 return i;
366 }
367 }
368 return 0xff;
369}
370
371
372
373
374
375
376
377
378
379
380int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
381 uint32_t *pwi, uint32_t *pei, uint8_t *pring)
382{
383 const xtensa_tlb *tlb = dtlb ?
384 &env->config->dtlb : &env->config->itlb;
385 const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
386 env->dtlb : env->itlb;
387
388 int nhits = 0;
389 unsigned wi;
390
391 for (wi = 0; wi < tlb->nways; ++wi) {
392 uint32_t vpn;
393 uint32_t ei;
394 split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
395 if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
396 unsigned ring = get_ring(env, entry[wi][ei].asid);
397 if (ring < 4) {
398 if (++nhits > 1) {
399 return dtlb ?
400 LOAD_STORE_TLB_MULTI_HIT_CAUSE :
401 INST_TLB_MULTI_HIT_CAUSE;
402 }
403 *pwi = wi;
404 *pei = ei;
405 *pring = ring;
406 }
407 }
408 }
409 return nhits ? 0 :
410 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
411}
412
413
414
415
416
417static unsigned mmu_attr_to_access(uint32_t attr)
418{
419 unsigned access = 0;
420
421 if (attr < 12) {
422 access |= PAGE_READ;
423 if (attr & 0x1) {
424 access |= PAGE_EXEC;
425 }
426 if (attr & 0x2) {
427 access |= PAGE_WRITE;
428 }
429
430 switch (attr & 0xc) {
431 case 0:
432 access |= PAGE_CACHE_BYPASS;
433 break;
434
435 case 4:
436 access |= PAGE_CACHE_WB;
437 break;
438
439 case 8:
440 access |= PAGE_CACHE_WT;
441 break;
442 }
443 } else if (attr == 13) {
444 access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
445 }
446 return access;
447}
448
449
450
451
452
453static unsigned region_attr_to_access(uint32_t attr)
454{
455 static const unsigned access[16] = {
456 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
457 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
458 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
459 [3] = PAGE_EXEC | PAGE_CACHE_WB,
460 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
461 [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
462 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
463 };
464
465 return access[attr & 0xf];
466}
467
468
469
470
471
472static unsigned cacheattr_attr_to_access(uint32_t attr)
473{
474 static const unsigned access[16] = {
475 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
476 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
477 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
478 [3] = PAGE_EXEC | PAGE_CACHE_WB,
479 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
480 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
481 };
482
483 return access[attr & 0xf];
484}
485
486static bool is_access_granted(unsigned access, int is_write)
487{
488 switch (is_write) {
489 case 0:
490 return access & PAGE_READ;
491
492 case 1:
493 return access & PAGE_WRITE;
494
495 case 2:
496 return access & PAGE_EXEC;
497
498 default:
499 return 0;
500 }
501}
502
503static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
504
505static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
506 uint32_t vaddr, int is_write, int mmu_idx,
507 uint32_t *paddr, uint32_t *page_size, unsigned *access,
508 bool may_lookup_pt)
509{
510 bool dtlb = is_write != 2;
511 uint32_t wi;
512 uint32_t ei;
513 uint8_t ring;
514 uint32_t vpn;
515 uint32_t pte;
516 const xtensa_tlb_entry *entry = NULL;
517 xtensa_tlb_entry tmp_entry;
518 int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
519
520 if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
521 may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
522 ring = (pte >> 4) & 0x3;
523 wi = 0;
524 split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
525
526 if (update_tlb) {
527 wi = ++env->autorefill_idx & 0x3;
528 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
529 env->sregs[EXCVADDR] = vaddr;
530 qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
531 __func__, vaddr, vpn, pte);
532 } else {
533 xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
534 entry = &tmp_entry;
535 }
536 ret = 0;
537 }
538 if (ret != 0) {
539 return ret;
540 }
541
542 if (entry == NULL) {
543 entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
544 }
545
546 if (ring < mmu_idx) {
547 return dtlb ?
548 LOAD_STORE_PRIVILEGE_CAUSE :
549 INST_FETCH_PRIVILEGE_CAUSE;
550 }
551
552 *access = mmu_attr_to_access(entry->attr) &
553 ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
554 if (!is_access_granted(*access, is_write)) {
555 return dtlb ?
556 (is_write ?
557 STORE_PROHIBITED_CAUSE :
558 LOAD_PROHIBITED_CAUSE) :
559 INST_FETCH_PROHIBITED_CAUSE;
560 }
561
562 *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
563 *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
564
565 return 0;
566}
567
568static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
569{
570 CPUState *cs = CPU(xtensa_env_get_cpu(env));
571 uint32_t paddr;
572 uint32_t page_size;
573 unsigned access;
574 uint32_t pt_vaddr =
575 (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
576 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
577 &paddr, &page_size, &access, false);
578
579 qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
580 vaddr, ret ? ~0 : paddr);
581
582 if (ret == 0) {
583 *pte = ldl_phys(cs->as, paddr);
584 }
585 return ret;
586}
587
588static int get_physical_addr_region(CPUXtensaState *env,
589 uint32_t vaddr, int is_write, int mmu_idx,
590 uint32_t *paddr, uint32_t *page_size, unsigned *access)
591{
592 bool dtlb = is_write != 2;
593 uint32_t wi = 0;
594 uint32_t ei = (vaddr >> 29) & 0x7;
595 const xtensa_tlb_entry *entry =
596 xtensa_tlb_get_entry(env, dtlb, wi, ei);
597
598 *access = region_attr_to_access(entry->attr);
599 if (!is_access_granted(*access, is_write)) {
600 return dtlb ?
601 (is_write ?
602 STORE_PROHIBITED_CAUSE :
603 LOAD_PROHIBITED_CAUSE) :
604 INST_FETCH_PROHIBITED_CAUSE;
605 }
606
607 *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
608 *page_size = ~REGION_PAGE_MASK + 1;
609
610 return 0;
611}
612
613
614
615
616
617
618
619int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
620 uint32_t vaddr, int is_write, int mmu_idx,
621 uint32_t *paddr, uint32_t *page_size, unsigned *access)
622{
623 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
624 return get_physical_addr_mmu(env, update_tlb,
625 vaddr, is_write, mmu_idx, paddr, page_size, access, true);
626 } else if (xtensa_option_bits_enabled(env->config,
627 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
628 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
629 return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
630 paddr, page_size, access);
631 } else {
632 *paddr = vaddr;
633 *page_size = TARGET_PAGE_SIZE;
634 *access = cacheattr_attr_to_access(
635 env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
636 return 0;
637 }
638}
639
640static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
641 CPUXtensaState *env, bool dtlb)
642{
643 unsigned wi, ei;
644 const xtensa_tlb *conf =
645 dtlb ? &env->config->dtlb : &env->config->itlb;
646 unsigned (*attr_to_access)(uint32_t) =
647 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
648 mmu_attr_to_access : region_attr_to_access;
649
650 for (wi = 0; wi < conf->nways; ++wi) {
651 uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
652 const char *sz_text;
653 bool print_header = true;
654
655 if (sz >= 0x100000) {
656 sz >>= 20;
657 sz_text = "MB";
658 } else {
659 sz >>= 10;
660 sz_text = "KB";
661 }
662
663 for (ei = 0; ei < conf->way_size[wi]; ++ei) {
664 const xtensa_tlb_entry *entry =
665 xtensa_tlb_get_entry(env, dtlb, wi, ei);
666
667 if (entry->asid) {
668 static const char * const cache_text[8] = {
669 [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
670 [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
671 [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
672 [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
673 };
674 unsigned access = attr_to_access(entry->attr);
675 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
676 PAGE_CACHE_SHIFT;
677
678 if (print_header) {
679 print_header = false;
680 cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
681 cpu_fprintf(f,
682 "\tVaddr Paddr ASID Attr RWX Cache\n"
683 "\t---------- ---------- ---- ---- --- -------\n");
684 }
685 cpu_fprintf(f,
686 "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
687 entry->vaddr,
688 entry->paddr,
689 entry->asid,
690 entry->attr,
691 (access & PAGE_READ) ? 'R' : '-',
692 (access & PAGE_WRITE) ? 'W' : '-',
693 (access & PAGE_EXEC) ? 'X' : '-',
694 cache_text[cache_idx] ? cache_text[cache_idx] :
695 "Invalid");
696 }
697 }
698 }
699}
700
701void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
702{
703 if (xtensa_option_bits_enabled(env->config,
704 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
705 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
706 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
707
708 cpu_fprintf(f, "ITLB:\n");
709 dump_tlb(f, cpu_fprintf, env, false);
710 cpu_fprintf(f, "\nDTLB:\n");
711 dump_tlb(f, cpu_fprintf, env, true);
712 } else {
713 cpu_fprintf(f, "No TLB for this CPU core\n");
714 }
715}
716
