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10#include "hw/hw.h"
11#include "hw/sysbus.h"
12#include "hw/arm/pxa.h"
13
14#define PXA2XX_GPIO_BANKS 4
15
16#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
17#define PXA2XX_GPIO(obj) \
18 OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
19
20typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
21struct PXA2xxGPIOInfo {
22
23 SysBusDevice parent_obj;
24
25
26 MemoryRegion iomem;
27 qemu_irq irq0, irq1, irqX;
28 int lines;
29 int ncpu;
30 ARMCPU *cpu;
31
32
33 uint32_t ilevel[PXA2XX_GPIO_BANKS];
34 uint32_t olevel[PXA2XX_GPIO_BANKS];
35 uint32_t dir[PXA2XX_GPIO_BANKS];
36 uint32_t rising[PXA2XX_GPIO_BANKS];
37 uint32_t falling[PXA2XX_GPIO_BANKS];
38 uint32_t status[PXA2XX_GPIO_BANKS];
39 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
40
41 uint32_t prev_level[PXA2XX_GPIO_BANKS];
42 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
43 qemu_irq read_notify;
44};
45
46static struct {
47 enum {
48 GPIO_NONE,
49 GPLR,
50 GPSR,
51 GPCR,
52 GPDR,
53 GRER,
54 GFER,
55 GEDR,
56 GAFR_L,
57 GAFR_U,
58 } reg;
59 int bank;
60} pxa2xx_gpio_regs[0x200] = {
61 [0 ... 0x1ff] = { GPIO_NONE, 0 },
62#define PXA2XX_REG(reg, a0, a1, a2, a3) \
63 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
64
65 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
66 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
67 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
68 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
69 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
70 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
71 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
72 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
73 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
74};
75
76static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
77{
78 if (s->status[0] & (1 << 0))
79 qemu_irq_raise(s->irq0);
80 else
81 qemu_irq_lower(s->irq0);
82
83 if (s->status[0] & (1 << 1))
84 qemu_irq_raise(s->irq1);
85 else
86 qemu_irq_lower(s->irq1);
87
88 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
89 qemu_irq_raise(s->irqX);
90 else
91 qemu_irq_lower(s->irqX);
92}
93
94
95static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
96 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
97};
98
99static void pxa2xx_gpio_set(void *opaque, int line, int level)
100{
101 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
102 CPUState *cpu = CPU(s->cpu);
103 int bank;
104 uint32_t mask;
105
106 if (line >= s->lines) {
107 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
108 return;
109 }
110
111 bank = line >> 5;
112 mask = 1U << (line & 31);
113
114 if (level) {
115 s->status[bank] |= s->rising[bank] & mask &
116 ~s->ilevel[bank] & ~s->dir[bank];
117 s->ilevel[bank] |= mask;
118 } else {
119 s->status[bank] |= s->falling[bank] & mask &
120 s->ilevel[bank] & ~s->dir[bank];
121 s->ilevel[bank] &= ~mask;
122 }
123
124 if (s->status[bank] & mask)
125 pxa2xx_gpio_irq_update(s);
126
127
128 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
129 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
130 }
131}
132
133static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
134 uint32_t level, diff;
135 int i, bit, line;
136 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
137 level = s->olevel[i] & s->dir[i];
138
139 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
140 bit = ctz32(diff);
141 line = bit + 32 * i;
142 qemu_set_irq(s->handler[line], (level >> bit) & 1);
143 }
144
145 s->prev_level[i] = level;
146 }
147}
148
149static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
150 unsigned size)
151{
152 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
153 uint32_t ret;
154 int bank;
155 if (offset >= 0x200)
156 return 0;
157
158 bank = pxa2xx_gpio_regs[offset].bank;
159 switch (pxa2xx_gpio_regs[offset].reg) {
160 case GPDR:
161 return s->dir[bank];
162
163 case GPSR:
164 qemu_log_mask(LOG_GUEST_ERROR,
165 "pxa2xx GPIO: read from write only register GPSR\n");
166 return 0;
167
168 case GPCR:
169 qemu_log_mask(LOG_GUEST_ERROR,
170 "pxa2xx GPIO: read from write only register GPCR\n");
171 return 0;
172
173 case GRER:
174 return s->rising[bank];
175
176 case GFER:
177 return s->falling[bank];
178
179 case GAFR_L:
180 return s->gafr[bank * 2];
181
182 case GAFR_U:
183 return s->gafr[bank * 2 + 1];
184
185 case GPLR:
186 ret = (s->olevel[bank] & s->dir[bank]) |
187 (s->ilevel[bank] & ~s->dir[bank]);
188 qemu_irq_raise(s->read_notify);
189 return ret;
190
191 case GEDR:
192 return s->status[bank];
193
194 default:
195 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
196 }
197
198 return 0;
199}
200
201static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
202 uint64_t value, unsigned size)
203{
204 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
205 int bank;
206 if (offset >= 0x200)
207 return;
208
209 bank = pxa2xx_gpio_regs[offset].bank;
210 switch (pxa2xx_gpio_regs[offset].reg) {
211 case GPDR:
212 s->dir[bank] = value;
213 pxa2xx_gpio_handler_update(s);
214 break;
215
216 case GPSR:
217 s->olevel[bank] |= value;
218 pxa2xx_gpio_handler_update(s);
219 break;
220
221 case GPCR:
222 s->olevel[bank] &= ~value;
223 pxa2xx_gpio_handler_update(s);
224 break;
225
226 case GRER:
227 s->rising[bank] = value;
228 break;
229
230 case GFER:
231 s->falling[bank] = value;
232 break;
233
234 case GAFR_L:
235 s->gafr[bank * 2] = value;
236 break;
237
238 case GAFR_U:
239 s->gafr[bank * 2 + 1] = value;
240 break;
241
242 case GEDR:
243 s->status[bank] &= ~value;
244 pxa2xx_gpio_irq_update(s);
245 break;
246
247 default:
248 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
249 }
250}
251
252static const MemoryRegionOps pxa_gpio_ops = {
253 .read = pxa2xx_gpio_read,
254 .write = pxa2xx_gpio_write,
255 .endianness = DEVICE_NATIVE_ENDIAN,
256};
257
258DeviceState *pxa2xx_gpio_init(hwaddr base,
259 ARMCPU *cpu, DeviceState *pic, int lines)
260{
261 CPUState *cs = CPU(cpu);
262 DeviceState *dev;
263
264 dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
265 qdev_prop_set_int32(dev, "lines", lines);
266 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
267 qdev_init_nofail(dev);
268
269 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
270 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
271 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
272 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
273 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
274 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
275 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
276
277 return dev;
278}
279
280static int pxa2xx_gpio_initfn(SysBusDevice *sbd)
281{
282 DeviceState *dev = DEVICE(sbd);
283 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
284
285 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
286
287 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
288 qdev_init_gpio_out(dev, s->handler, s->lines);
289
290 memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
291 sysbus_init_mmio(sbd, &s->iomem);
292 sysbus_init_irq(sbd, &s->irq0);
293 sysbus_init_irq(sbd, &s->irq1);
294 sysbus_init_irq(sbd, &s->irqX);
295
296 return 0;
297}
298
299
300
301
302
303void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
304{
305 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
306
307 s->read_notify = handler;
308}
309
310static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
311 .name = "pxa2xx-gpio",
312 .version_id = 1,
313 .minimum_version_id = 1,
314 .fields = (VMStateField[]) {
315 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
316 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
317 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
318 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
319 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
320 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
321 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
322 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
323 VMSTATE_END_OF_LIST(),
324 },
325};
326
327static Property pxa2xx_gpio_properties[] = {
328 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
329 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
330 DEFINE_PROP_END_OF_LIST(),
331};
332
333static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
334{
335 DeviceClass *dc = DEVICE_CLASS(klass);
336 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
337
338 k->init = pxa2xx_gpio_initfn;
339 dc->desc = "PXA2xx GPIO controller";
340 dc->props = pxa2xx_gpio_properties;
341 dc->vmsd = &vmstate_pxa2xx_gpio_regs;
342}
343
344static const TypeInfo pxa2xx_gpio_info = {
345 .name = TYPE_PXA2XX_GPIO,
346 .parent = TYPE_SYS_BUS_DEVICE,
347 .instance_size = sizeof(PXA2xxGPIOInfo),
348 .class_init = pxa2xx_gpio_class_init,
349};
350
351static void pxa2xx_gpio_register_types(void)
352{
353 type_register_static(&pxa2xx_gpio_info);
354}
355
356type_init(pxa2xx_gpio_register_types)
357
