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22#ifndef CPU_S390X_H
23#define CPU_S390X_H
24
25#include "config.h"
26#include "qemu-common.h"
27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
31#define ELF_MACHINE_UNAME "S390X"
32
33#define CPUArchState struct CPUS390XState
34
35#include "exec/cpu-defs.h"
36#define TARGET_PAGE_BITS 12
37
38#define TARGET_PHYS_ADDR_SPACE_BITS 64
39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
41#include "exec/cpu-all.h"
42
43#include "fpu/softfloat.h"
44
45#define NB_MMU_MODES 3
46
47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 0
52
53#define MAX_EXT_QUEUE 16
54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
70
71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
82typedef struct CPUS390XState {
83 uint64_t regs[16];
84
85
86
87
88 CPU_DoubleU vregs[32][2];
89 uint32_t aregs[16];
90
91 uint32_t fpc;
92 uint32_t cc_op;
93
94 float_status fpu_status;
95
96
97 uint64_t retxl;
98
99 PSW psw;
100
101 uint64_t cc_src;
102 uint64_t cc_dst;
103 uint64_t cc_vr;
104
105 uint64_t __excp_addr;
106 uint64_t psa;
107
108 uint32_t int_pgm_code;
109 uint32_t int_pgm_ilen;
110
111 uint32_t int_svc_code;
112 uint32_t int_svc_ilen;
113
114 uint64_t per_address;
115 uint16_t per_perc_atmid;
116
117 uint64_t cregs[16];
118
119 ExtQueue ext_queue[MAX_EXT_QUEUE];
120 IOIntQueue io_queue[MAX_IO_QUEUE][8];
121 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
122
123 int pending_int;
124 int ext_index;
125 int io_index[8];
126 int mchk_index;
127
128 uint64_t ckc;
129 uint64_t cputm;
130 uint32_t todpr;
131
132 uint64_t pfault_token;
133 uint64_t pfault_compare;
134 uint64_t pfault_select;
135
136 uint64_t gbea;
137 uint64_t pp;
138
139 CPU_COMMON
140
141
142
143 uint32_t cpu_num;
144 uint32_t machine_type;
145
146 uint8_t *storage_keys;
147
148 uint64_t tod_offset;
149 uint64_t tod_basetime;
150 QEMUTimer *tod_timer;
151
152 QEMUTimer *cpu_timer;
153
154
155
156
157
158
159
160#define CPU_STATE_UNINITIALIZED 0x00
161#define CPU_STATE_STOPPED 0x01
162#define CPU_STATE_CHECK_STOP 0x02
163#define CPU_STATE_OPERATING 0x03
164#define CPU_STATE_LOAD 0x04
165 uint8_t cpu_state;
166
167
168 uint8_t sigp_order;
169
170} CPUS390XState;
171
172static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
173{
174 return &cs->vregs[nr][0];
175}
176
177#include "cpu-qom.h"
178#include <sysemu/kvm.h>
179
180
181#define HIGH_ORDER_BIT 0x80000000
182
183
184
185#define PGM_OPERATION 0x0001
186#define PGM_PRIVILEGED 0x0002
187#define PGM_EXECUTE 0x0003
188#define PGM_PROTECTION 0x0004
189#define PGM_ADDRESSING 0x0005
190#define PGM_SPECIFICATION 0x0006
191#define PGM_DATA 0x0007
192#define PGM_FIXPT_OVERFLOW 0x0008
193#define PGM_FIXPT_DIVIDE 0x0009
194#define PGM_DEC_OVERFLOW 0x000a
195#define PGM_DEC_DIVIDE 0x000b
196#define PGM_HFP_EXP_OVERFLOW 0x000c
197#define PGM_HFP_EXP_UNDERFLOW 0x000d
198#define PGM_HFP_SIGNIFICANCE 0x000e
199#define PGM_HFP_DIVIDE 0x000f
200#define PGM_SEGMENT_TRANS 0x0010
201#define PGM_PAGE_TRANS 0x0011
202#define PGM_TRANS_SPEC 0x0012
203#define PGM_SPECIAL_OP 0x0013
204#define PGM_OPERAND 0x0015
205#define PGM_TRACE_TABLE 0x0016
206#define PGM_SPACE_SWITCH 0x001c
207#define PGM_HFP_SQRT 0x001d
208#define PGM_PC_TRANS_SPEC 0x001f
209#define PGM_AFX_TRANS 0x0020
210#define PGM_ASX_TRANS 0x0021
211#define PGM_LX_TRANS 0x0022
212#define PGM_EX_TRANS 0x0023
213#define PGM_PRIM_AUTH 0x0024
214#define PGM_SEC_AUTH 0x0025
215#define PGM_ALET_SPEC 0x0028
216#define PGM_ALEN_SPEC 0x0029
217#define PGM_ALE_SEQ 0x002a
218#define PGM_ASTE_VALID 0x002b
219#define PGM_ASTE_SEQ 0x002c
220#define PGM_EXT_AUTH 0x002d
221#define PGM_STACK_FULL 0x0030
222#define PGM_STACK_EMPTY 0x0031
223#define PGM_STACK_SPEC 0x0032
224#define PGM_STACK_TYPE 0x0033
225#define PGM_STACK_OP 0x0034
226#define PGM_ASCE_TYPE 0x0038
227#define PGM_REG_FIRST_TRANS 0x0039
228#define PGM_REG_SEC_TRANS 0x003a
229#define PGM_REG_THIRD_TRANS 0x003b
230#define PGM_MONITOR 0x0040
231#define PGM_PER 0x0080
232#define PGM_CRYPTO 0x0119
233
234
235#define EXT_INTERRUPT_KEY 0x0040
236#define EXT_CLOCK_COMP 0x1004
237#define EXT_CPU_TIMER 0x1005
238#define EXT_MALFUNCTION 0x1200
239#define EXT_EMERGENCY 0x1201
240#define EXT_EXTERNAL_CALL 0x1202
241#define EXT_ETR 0x1406
242#define EXT_SERVICE 0x2401
243#define EXT_VIRTIO 0x2603
244
245
246#undef PSW_MASK_PER
247#undef PSW_MASK_DAT
248#undef PSW_MASK_IO
249#undef PSW_MASK_EXT
250#undef PSW_MASK_KEY
251#undef PSW_SHIFT_KEY
252#undef PSW_MASK_MCHECK
253#undef PSW_MASK_WAIT
254#undef PSW_MASK_PSTATE
255#undef PSW_MASK_ASC
256#undef PSW_MASK_CC
257#undef PSW_MASK_PM
258#undef PSW_MASK_64
259#undef PSW_MASK_32
260#undef PSW_MASK_ESA_ADDR
261
262#define PSW_MASK_PER 0x4000000000000000ULL
263#define PSW_MASK_DAT 0x0400000000000000ULL
264#define PSW_MASK_IO 0x0200000000000000ULL
265#define PSW_MASK_EXT 0x0100000000000000ULL
266#define PSW_MASK_KEY 0x00F0000000000000ULL
267#define PSW_SHIFT_KEY 56
268#define PSW_MASK_MCHECK 0x0004000000000000ULL
269#define PSW_MASK_WAIT 0x0002000000000000ULL
270#define PSW_MASK_PSTATE 0x0001000000000000ULL
271#define PSW_MASK_ASC 0x0000C00000000000ULL
272#define PSW_MASK_CC 0x0000300000000000ULL
273#define PSW_MASK_PM 0x00000F0000000000ULL
274#define PSW_MASK_64 0x0000000100000000ULL
275#define PSW_MASK_32 0x0000000080000000ULL
276#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
277
278#undef PSW_ASC_PRIMARY
279#undef PSW_ASC_ACCREG
280#undef PSW_ASC_SECONDARY
281#undef PSW_ASC_HOME
282
283#define PSW_ASC_PRIMARY 0x0000000000000000ULL
284#define PSW_ASC_ACCREG 0x0000400000000000ULL
285#define PSW_ASC_SECONDARY 0x0000800000000000ULL
286#define PSW_ASC_HOME 0x0000C00000000000ULL
287
288
289
290#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
291#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
292#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
293#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
294#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
295#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
296#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
297#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
298#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
299#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
300#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
301#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
302#define FLAG_MASK_32 0x00001000
303
304
305#define CR0_LOWPROT 0x0000000010000000ULL
306#define CR0_EDAT 0x0000000000800000ULL
307
308
309#define MMU_PRIMARY_IDX 0
310#define MMU_SECONDARY_IDX 1
311#define MMU_HOME_IDX 2
312
313static inline int cpu_mmu_index (CPUS390XState *env)
314{
315 switch (env->psw.mask & PSW_MASK_ASC) {
316 case PSW_ASC_PRIMARY:
317 return MMU_PRIMARY_IDX;
318 case PSW_ASC_SECONDARY:
319 return MMU_SECONDARY_IDX;
320 case PSW_ASC_HOME:
321 return MMU_HOME_IDX;
322 case PSW_ASC_ACCREG:
323
324 default:
325 abort();
326 }
327}
328
329static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
330{
331 switch (mmu_idx) {
332 case MMU_PRIMARY_IDX:
333 return PSW_ASC_PRIMARY;
334 case MMU_SECONDARY_IDX:
335 return PSW_ASC_SECONDARY;
336 case MMU_HOME_IDX:
337 return PSW_ASC_HOME;
338 default:
339 abort();
340 }
341}
342
343static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
344 target_ulong *cs_base, int *flags)
345{
346 *pc = env->psw.addr;
347 *cs_base = 0;
348 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
349 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
350}
351
352
353
354
355
356
357static inline int get_ilen(uint8_t opc)
358{
359 switch (opc >> 6) {
360 case 0:
361 return 2;
362 case 1:
363 case 2:
364 return 4;
365 default:
366 return 6;
367 }
368}
369
370
371#define PER_CR9_EVENT_BRANCH 0x80000000
372#define PER_CR9_EVENT_IFETCH 0x40000000
373#define PER_CR9_EVENT_STORE 0x20000000
374#define PER_CR9_EVENT_STORE_REAL 0x08000000
375#define PER_CR9_EVENT_NULLIFICATION 0x01000000
376#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
377#define PER_CR9_CONTROL_ALTERATION 0x00200000
378
379
380#define PER_CODE_EVENT_BRANCH 0x8000
381#define PER_CODE_EVENT_IFETCH 0x4000
382#define PER_CODE_EVENT_STORE 0x2000
383#define PER_CODE_EVENT_STORE_REAL 0x0800
384#define PER_CODE_EVENT_NULLIFICATION 0x0100
385
386
387
388static inline uint8_t get_per_atmid(CPUS390XState *env)
389{
390 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
391 ( (1 << 6) ) |
392 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
393 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
394 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
395 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
396}
397
398
399
400static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
401{
402 if (env->cregs[10] <= env->cregs[11]) {
403 return env->cregs[10] <= addr && addr <= env->cregs[11];
404 } else {
405 return env->cregs[10] <= addr || addr <= env->cregs[11];
406 }
407}
408
409#ifndef CONFIG_USER_ONLY
410
411
412
413#define ILEN_LATER 0x20
414#define ILEN_LATER_INC 0x21
415void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
416#endif
417
418S390CPU *cpu_s390x_init(const char *cpu_model);
419void s390x_translate_init(void);
420int cpu_s390x_exec(CPUState *cpu);
421
422
423
424
425int cpu_s390x_signal_handler(int host_signum, void *pinfo,
426 void *puc);
427int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
428 int mmu_idx);
429
430#include "ioinst.h"
431
432
433#ifndef CONFIG_USER_ONLY
434void do_restart_interrupt(CPUS390XState *env);
435
436static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
437 uint8_t *ar)
438{
439 hwaddr addr = 0;
440 uint8_t reg;
441
442 reg = ipb >> 28;
443 if (reg > 0) {
444 addr = env->regs[reg];
445 }
446 addr += (ipb >> 16) & 0xfff;
447 if (ar) {
448 *ar = reg;
449 }
450
451 return addr;
452}
453
454
455#define decode_basedisp_rs decode_basedisp_s
456
457
458static inline void s390_do_cpu_reset(void *arg)
459{
460 CPUState *cs = arg;
461 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
462
463 scc->cpu_reset(cs);
464}
465static inline void s390_do_cpu_full_reset(void *arg)
466{
467 CPUState *cs = arg;
468
469 cpu_reset(cs);
470}
471
472void s390x_tod_timer(void *opaque);
473void s390x_cpu_timer(void *opaque);
474
475int s390_virtio_hypercall(CPUS390XState *env);
476void s390_virtio_irq(int config_change, uint64_t token);
477
478#ifdef CONFIG_KVM
479void kvm_s390_virtio_irq(int config_change, uint64_t token);
480void kvm_s390_service_interrupt(uint32_t parm);
481void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
482void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
483int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
484void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
485int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
486 int len, bool is_write);
487int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
488int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
489#else
490static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
491{
492}
493static inline void kvm_s390_service_interrupt(uint32_t parm)
494{
495}
496static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
497{
498 return -ENOSYS;
499}
500static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
501{
502 return -ENOSYS;
503}
504static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
505 void *hostbuf, int len, bool is_write)
506{
507 return -ENOSYS;
508}
509static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
510 uint64_t te_code)
511{
512}
513#endif
514
515static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
516{
517 if (kvm_enabled()) {
518 return kvm_s390_get_clock(tod_high, tod_low);
519 }
520
521 *tod_high = 0;
522 *tod_low = 0;
523 return 0;
524}
525
526static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
527{
528 if (kvm_enabled()) {
529 return kvm_s390_set_clock(tod_high, tod_low);
530 }
531
532 return 0;
533}
534
535S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
536unsigned int s390_cpu_halt(S390CPU *cpu);
537void s390_cpu_unhalt(S390CPU *cpu);
538unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
539static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
540{
541 return cpu->env.cpu_state;
542}
543
544void gtod_save(QEMUFile *f, void *opaque);
545int gtod_load(QEMUFile *f, void *opaque, int version_id);
546
547
548void s390_sclp_extint(uint32_t parm);
549
550
551extern const hwaddr virtio_size;
552
553#else
554static inline unsigned int s390_cpu_halt(S390CPU *cpu)
555{
556 return 0;
557}
558
559static inline void s390_cpu_unhalt(S390CPU *cpu)
560{
561}
562
563static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
564{
565 return 0;
566}
567#endif
568void cpu_lock(void);
569void cpu_unlock(void);
570
571typedef struct SubchDev SubchDev;
572
573#ifndef CONFIG_USER_ONLY
574extern void io_subsystem_reset(void);
575SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
576 uint16_t schid);
577bool css_subch_visible(SubchDev *sch);
578void css_conditional_io_interrupt(SubchDev *sch);
579int css_do_stsch(SubchDev *sch, SCHIB *schib);
580bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
581int css_do_msch(SubchDev *sch, const SCHIB *schib);
582int css_do_xsch(SubchDev *sch);
583int css_do_csch(SubchDev *sch);
584int css_do_hsch(SubchDev *sch);
585int css_do_ssch(SubchDev *sch, ORB *orb);
586int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
587void css_do_tsch_update_subch(SubchDev *sch);
588int css_do_stcrw(CRW *crw);
589void css_undo_stcrw(CRW *crw);
590int css_do_tpi(IOIntCode *int_code, int lowcore);
591int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
592 int rfmt, void *buf);
593void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
594int css_enable_mcsse(void);
595int css_enable_mss(void);
596int css_do_rsch(SubchDev *sch);
597int css_do_rchp(uint8_t cssid, uint8_t chpid);
598bool css_present(uint8_t cssid);
599#endif
600
601#define cpu_init(model) CPU(cpu_s390x_init(model))
602#define cpu_exec cpu_s390x_exec
603#define cpu_gen_code cpu_s390x_gen_code
604#define cpu_signal_handler cpu_s390x_signal_handler
605
606void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
607#define cpu_list s390_cpu_list
608
609#include "exec/exec-all.h"
610
611#define EXCP_EXT 1
612#define EXCP_SVC 2
613#define EXCP_PGM 3
614#define EXCP_IO 7
615#define EXCP_MCHK 8
616
617#define INTERRUPT_EXT (1 << 0)
618#define INTERRUPT_TOD (1 << 1)
619#define INTERRUPT_CPUTIMER (1 << 2)
620#define INTERRUPT_IO (1 << 3)
621#define INTERRUPT_MCHK (1 << 4)
622
623
624#define S390_PSWM_REGNUM 0
625#define S390_PSWA_REGNUM 1
626
627#define S390_R0_REGNUM 2
628#define S390_R1_REGNUM 3
629#define S390_R2_REGNUM 4
630#define S390_R3_REGNUM 5
631#define S390_R4_REGNUM 6
632#define S390_R5_REGNUM 7
633#define S390_R6_REGNUM 8
634#define S390_R7_REGNUM 9
635#define S390_R8_REGNUM 10
636#define S390_R9_REGNUM 11
637#define S390_R10_REGNUM 12
638#define S390_R11_REGNUM 13
639#define S390_R12_REGNUM 14
640#define S390_R13_REGNUM 15
641#define S390_R14_REGNUM 16
642#define S390_R15_REGNUM 17
643
644#define S390_NUM_CORE_REGS 18
645
646
647
648enum cc_op {
649 CC_OP_CONST0 = 0,
650 CC_OP_CONST1,
651 CC_OP_CONST2,
652 CC_OP_CONST3,
653
654 CC_OP_DYNAMIC,
655 CC_OP_STATIC,
656
657 CC_OP_NZ,
658 CC_OP_LTGT_32,
659 CC_OP_LTGT_64,
660 CC_OP_LTUGTU_32,
661 CC_OP_LTUGTU_64,
662 CC_OP_LTGT0_32,
663 CC_OP_LTGT0_64,
664
665 CC_OP_ADD_64,
666 CC_OP_ADDU_64,
667 CC_OP_ADDC_64,
668 CC_OP_SUB_64,
669 CC_OP_SUBU_64,
670 CC_OP_SUBB_64,
671 CC_OP_ABS_64,
672 CC_OP_NABS_64,
673
674 CC_OP_ADD_32,
675 CC_OP_ADDU_32,
676 CC_OP_ADDC_32,
677 CC_OP_SUB_32,
678 CC_OP_SUBU_32,
679 CC_OP_SUBB_32,
680 CC_OP_ABS_32,
681 CC_OP_NABS_32,
682
683 CC_OP_COMP_32,
684 CC_OP_COMP_64,
685
686 CC_OP_TM_32,
687 CC_OP_TM_64,
688
689 CC_OP_NZ_F32,
690 CC_OP_NZ_F64,
691 CC_OP_NZ_F128,
692
693 CC_OP_ICM,
694 CC_OP_SLA_32,
695 CC_OP_SLA_64,
696 CC_OP_FLOGR,
697 CC_OP_MAX
698};
699
700static const char *cc_names[] = {
701 [CC_OP_CONST0] = "CC_OP_CONST0",
702 [CC_OP_CONST1] = "CC_OP_CONST1",
703 [CC_OP_CONST2] = "CC_OP_CONST2",
704 [CC_OP_CONST3] = "CC_OP_CONST3",
705 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
706 [CC_OP_STATIC] = "CC_OP_STATIC",
707 [CC_OP_NZ] = "CC_OP_NZ",
708 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
709 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
710 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
711 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
712 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
713 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
714 [CC_OP_ADD_64] = "CC_OP_ADD_64",
715 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
716 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
717 [CC_OP_SUB_64] = "CC_OP_SUB_64",
718 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
719 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
720 [CC_OP_ABS_64] = "CC_OP_ABS_64",
721 [CC_OP_NABS_64] = "CC_OP_NABS_64",
722 [CC_OP_ADD_32] = "CC_OP_ADD_32",
723 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
724 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
725 [CC_OP_SUB_32] = "CC_OP_SUB_32",
726 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
727 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
728 [CC_OP_ABS_32] = "CC_OP_ABS_32",
729 [CC_OP_NABS_32] = "CC_OP_NABS_32",
730 [CC_OP_COMP_32] = "CC_OP_COMP_32",
731 [CC_OP_COMP_64] = "CC_OP_COMP_64",
732 [CC_OP_TM_32] = "CC_OP_TM_32",
733 [CC_OP_TM_64] = "CC_OP_TM_64",
734 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
735 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
736 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
737 [CC_OP_ICM] = "CC_OP_ICM",
738 [CC_OP_SLA_32] = "CC_OP_SLA_32",
739 [CC_OP_SLA_64] = "CC_OP_SLA_64",
740 [CC_OP_FLOGR] = "CC_OP_FLOGR",
741};
742
743static inline const char *cc_name(int cc_op)
744{
745 return cc_names[cc_op];
746}
747
748static inline void setcc(S390CPU *cpu, uint64_t cc)
749{
750 CPUS390XState *env = &cpu->env;
751
752 env->psw.mask &= ~(3ull << 44);
753 env->psw.mask |= (cc & 3) << 44;
754 env->cc_op = cc;
755}
756
757typedef struct LowCore
758{
759
760 uint32_t ccw1[2];
761 uint32_t ccw2[4];
762 uint8_t pad1[0x80-0x18];
763 uint32_t ext_params;
764 uint16_t cpu_addr;
765 uint16_t ext_int_code;
766 uint16_t svc_ilen;
767 uint16_t svc_code;
768 uint16_t pgm_ilen;
769 uint16_t pgm_code;
770 uint32_t data_exc_code;
771 uint16_t mon_class_num;
772 uint16_t per_perc_atmid;
773 uint64_t per_address;
774 uint8_t exc_access_id;
775 uint8_t per_access_id;
776 uint8_t op_access_id;
777 uint8_t ar_access_id;
778 uint8_t pad2[0xA8-0xA4];
779 uint64_t trans_exc_code;
780 uint64_t monitor_code;
781 uint16_t subchannel_id;
782 uint16_t subchannel_nr;
783 uint32_t io_int_parm;
784 uint32_t io_int_word;
785 uint8_t pad3[0xc8-0xc4];
786 uint32_t stfl_fac_list;
787 uint8_t pad4[0xe8-0xcc];
788 uint32_t mcck_interruption_code[2];
789 uint8_t pad5[0xf4-0xf0];
790 uint32_t external_damage_code;
791 uint64_t failing_storage_address;
792 uint8_t pad6[0x110-0x100];
793 uint64_t per_breaking_event_addr;
794 uint8_t pad7[0x120-0x118];
795 PSW restart_old_psw;
796 PSW external_old_psw;
797 PSW svc_old_psw;
798 PSW program_old_psw;
799 PSW mcck_old_psw;
800 PSW io_old_psw;
801 uint8_t pad8[0x1a0-0x180];
802 PSW restart_new_psw;
803 PSW external_new_psw;
804 PSW svc_new_psw;
805 PSW program_new_psw;
806 PSW mcck_new_psw;
807 PSW io_new_psw;
808 PSW return_psw;
809 uint8_t irb[64];
810 uint64_t sync_enter_timer;
811 uint64_t async_enter_timer;
812 uint64_t exit_timer;
813 uint64_t last_update_timer;
814 uint64_t user_timer;
815 uint64_t system_timer;
816 uint64_t last_update_clock;
817 uint64_t steal_clock;
818 PSW return_mcck_psw;
819 uint8_t pad9[0xc00-0x2a0];
820
821 uint64_t save_area[16];
822 uint8_t pad10[0xd40-0xc80];
823 uint64_t kernel_stack;
824 uint64_t thread_info;
825 uint64_t async_stack;
826 uint64_t kernel_asce;
827 uint64_t user_asce;
828 uint64_t panic_stack;
829 uint64_t user_exec_asce;
830 uint8_t pad11[0xdc0-0xd78];
831
832
833 uint64_t clock_comparator;
834 uint64_t ext_call_fast;
835 uint64_t percpu_offset;
836 uint64_t current_task;
837 uint32_t softirq_pending;
838 uint32_t pad_0x0de4;
839 uint64_t int_clock;
840 uint8_t pad12[0xe00-0xdf0];
841
842
843
844 uint32_t panic_magic;
845
846 uint8_t pad13[0x11b8-0xe04];
847
848
849 uint64_t ext_params2;
850
851 uint8_t pad14[0x1200-0x11C0];
852
853
854
855 uint64_t floating_pt_save_area[16];
856 uint64_t gpregs_save_area[16];
857 uint32_t st_status_fixed_logout[4];
858 uint8_t pad15[0x1318-0x1310];
859 uint32_t prefixreg_save_area;
860 uint32_t fpt_creg_save_area;
861 uint8_t pad16[0x1324-0x1320];
862 uint32_t tod_progreg_save_area;
863 uint32_t cpu_timer_save_area[2];
864 uint32_t clock_comp_save_area[2];
865 uint8_t pad17[0x1340-0x1338];
866 uint32_t access_regs_save_area[16];
867 uint64_t cregs_save_area[16];
868
869
870
871 uint8_t pad18[0x2000-0x1400];
872} QEMU_PACKED LowCore;
873
874
875#define STSI_LEVEL_MASK 0x00000000f0000000ULL
876#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
877#define STSI_LEVEL_1 0x0000000010000000ULL
878#define STSI_LEVEL_2 0x0000000020000000ULL
879#define STSI_LEVEL_3 0x0000000030000000ULL
880#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
881#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
882#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
883#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
884
885
886struct sysib_111 {
887 uint32_t res1[8];
888 uint8_t manuf[16];
889 uint8_t type[4];
890 uint8_t res2[12];
891 uint8_t model[16];
892 uint8_t sequence[16];
893 uint8_t plant[4];
894 uint8_t res3[156];
895};
896
897
898struct sysib_121 {
899 uint32_t res1[80];
900 uint8_t sequence[16];
901 uint8_t plant[4];
902 uint8_t res2[2];
903 uint16_t cpu_addr;
904 uint8_t res3[152];
905};
906
907
908struct sysib_122 {
909 uint8_t res1[32];
910 uint32_t capability;
911 uint16_t total_cpus;
912 uint16_t active_cpus;
913 uint16_t standby_cpus;
914 uint16_t reserved_cpus;
915 uint16_t adjustments[2026];
916};
917
918
919struct sysib_221 {
920 uint32_t res1[80];
921 uint8_t sequence[16];
922 uint8_t plant[4];
923 uint16_t cpu_id;
924 uint16_t cpu_addr;
925 uint8_t res3[152];
926};
927
928
929struct sysib_222 {
930 uint32_t res1[32];
931 uint16_t lpar_num;
932 uint8_t res2;
933 uint8_t lcpuc;
934 uint16_t total_cpus;
935 uint16_t conf_cpus;
936 uint16_t standby_cpus;
937 uint16_t reserved_cpus;
938 uint8_t name[8];
939 uint32_t caf;
940 uint8_t res3[16];
941 uint16_t dedicated_cpus;
942 uint16_t shared_cpus;
943 uint8_t res4[180];
944};
945
946
947struct sysib_322 {
948 uint8_t res1[31];
949 uint8_t count;
950 struct {
951 uint8_t res2[4];
952 uint16_t total_cpus;
953 uint16_t conf_cpus;
954 uint16_t standby_cpus;
955 uint16_t reserved_cpus;
956 uint8_t name[8];
957 uint32_t caf;
958 uint8_t cpi[16];
959 uint8_t res5[3];
960 uint8_t ext_name_encoding;
961 uint32_t res3;
962 uint8_t uuid[16];
963 } vm[8];
964 uint8_t res4[1504];
965 uint8_t ext_names[8][256];
966};
967
968
969#define _ASCE_ORIGIN ~0xfffULL
970#define _ASCE_SUBSPACE 0x200
971#define _ASCE_PRIVATE_SPACE 0x100
972#define _ASCE_ALT_EVENT 0x80
973#define _ASCE_SPACE_SWITCH 0x40
974#define _ASCE_REAL_SPACE 0x20
975#define _ASCE_TYPE_MASK 0x0c
976#define _ASCE_TYPE_REGION1 0x0c
977#define _ASCE_TYPE_REGION2 0x08
978#define _ASCE_TYPE_REGION3 0x04
979#define _ASCE_TYPE_SEGMENT 0x00
980#define _ASCE_TABLE_LENGTH 0x03
981
982#define _REGION_ENTRY_ORIGIN ~0xfffULL
983#define _REGION_ENTRY_RO 0x200
984#define _REGION_ENTRY_TF 0xc0
985#define _REGION_ENTRY_INV 0x20
986#define _REGION_ENTRY_TYPE_MASK 0x0c
987#define _REGION_ENTRY_TYPE_R1 0x0c
988#define _REGION_ENTRY_TYPE_R2 0x08
989#define _REGION_ENTRY_TYPE_R3 0x04
990#define _REGION_ENTRY_LENGTH 0x03
991
992#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL
993#define _SEGMENT_ENTRY_FC 0x400
994#define _SEGMENT_ENTRY_RO 0x200
995#define _SEGMENT_ENTRY_INV 0x20
996
997#define _PAGE_RO 0x200
998#define _PAGE_INVALID 0x400
999#define _PAGE_RES0 0x800
1000
1001#define SK_C (0x1 << 1)
1002#define SK_R (0x1 << 2)
1003#define SK_F (0x1 << 3)
1004#define SK_ACC_MASK (0xf << 4)
1005
1006
1007#define SIGP_SENSE 0x01
1008#define SIGP_EXTERNAL_CALL 0x02
1009#define SIGP_EMERGENCY 0x03
1010#define SIGP_START 0x04
1011#define SIGP_STOP 0x05
1012#define SIGP_RESTART 0x06
1013#define SIGP_STOP_STORE_STATUS 0x09
1014#define SIGP_INITIAL_CPU_RESET 0x0b
1015#define SIGP_CPU_RESET 0x0c
1016#define SIGP_SET_PREFIX 0x0d
1017#define SIGP_STORE_STATUS_ADDR 0x0e
1018#define SIGP_SET_ARCH 0x12
1019#define SIGP_STORE_ADTL_STATUS 0x17
1020
1021
1022#define SIGP_CC_ORDER_CODE_ACCEPTED 0
1023#define SIGP_CC_STATUS_STORED 1
1024#define SIGP_CC_BUSY 2
1025#define SIGP_CC_NOT_OPERATIONAL 3
1026
1027
1028#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1029#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1030#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1031#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1032#define SIGP_STAT_STOPPED 0x00000040UL
1033#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1034#define SIGP_STAT_CHECK_STOP 0x00000010UL
1035#define SIGP_STAT_INOPERATIVE 0x00000004UL
1036#define SIGP_STAT_INVALID_ORDER 0x00000002UL
1037#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1038
1039
1040#define SIGP_MODE_ESA_S390 0
1041#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1042#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1043
1044void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1045int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1046 target_ulong *raddr, int *flags, bool exc);
1047int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1048uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1049 uint64_t vr);
1050void s390_cpu_recompute_watchpoints(CPUState *cs);
1051
1052int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1053 int len, bool is_write);
1054
1055#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1056 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1057#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1058 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1059#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1060 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1061
1062
1063#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1064
1065
1066static inline uint64_t time2tod(uint64_t ns) {
1067 return (ns << 9) / 125;
1068}
1069
1070
1071static inline uint64_t tod2time(uint64_t t) {
1072 return (t * 125) >> 9;
1073}
1074
1075static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
1076 uint64_t param64)
1077{
1078 CPUS390XState *env = &cpu->env;
1079
1080 if (env->ext_index == MAX_EXT_QUEUE - 1) {
1081
1082 return;
1083 }
1084
1085 env->ext_index++;
1086 assert(env->ext_index < MAX_EXT_QUEUE);
1087
1088 env->ext_queue[env->ext_index].code = code;
1089 env->ext_queue[env->ext_index].param = param;
1090 env->ext_queue[env->ext_index].param64 = param64;
1091
1092 env->pending_int |= INTERRUPT_EXT;
1093 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1094}
1095
1096static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1097 uint16_t subchannel_number,
1098 uint32_t io_int_parm, uint32_t io_int_word)
1099{
1100 CPUS390XState *env = &cpu->env;
1101 int isc = IO_INT_WORD_ISC(io_int_word);
1102
1103 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1104
1105 return;
1106 }
1107
1108 env->io_index[isc]++;
1109 assert(env->io_index[isc] < MAX_IO_QUEUE);
1110
1111 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1112 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1113 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1114 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1115
1116 env->pending_int |= INTERRUPT_IO;
1117 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1118}
1119
1120static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1121{
1122 CPUS390XState *env = &cpu->env;
1123
1124 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1125
1126 return;
1127 }
1128
1129 env->mchk_index++;
1130 assert(env->mchk_index < MAX_MCHK_QUEUE);
1131
1132 env->mchk_queue[env->mchk_index].type = 1;
1133
1134 env->pending_int |= INTERRUPT_MCHK;
1135 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1136}
1137
1138
1139#define MEM_SECTION_SIZE 0x10000000UL
1140#define MAX_AVAIL_SLOTS 32
1141
1142
1143uint32_t set_cc_nz_f32(float32 v);
1144uint32_t set_cc_nz_f64(float64 v);
1145uint32_t set_cc_nz_f128(float128 v);
1146
1147
1148#ifndef CONFIG_USER_ONLY
1149int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1150void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1151#endif
1152void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1153void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1154 uintptr_t retaddr);
1155
1156#ifdef CONFIG_KVM
1157void kvm_s390_io_interrupt(uint16_t subchannel_id,
1158 uint16_t subchannel_nr, uint32_t io_int_parm,
1159 uint32_t io_int_word);
1160void kvm_s390_crw_mchk(void);
1161void kvm_s390_enable_css_support(S390CPU *cpu);
1162int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1163 int vq, bool assign);
1164int kvm_s390_cpu_restart(S390CPU *cpu);
1165int kvm_s390_get_memslot_count(KVMState *s);
1166void kvm_s390_clear_cmma_callback(void *opaque);
1167int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1168void kvm_s390_reset_vcpu(S390CPU *cpu);
1169int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1170void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1171int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1172#else
1173static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1174 uint16_t subchannel_nr,
1175 uint32_t io_int_parm,
1176 uint32_t io_int_word)
1177{
1178}
1179static inline void kvm_s390_crw_mchk(void)
1180{
1181}
1182static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1183{
1184}
1185static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1186 uint32_t sch, int vq,
1187 bool assign)
1188{
1189 return -ENOSYS;
1190}
1191static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1192{
1193 return -ENOSYS;
1194}
1195static inline void kvm_s390_clear_cmma_callback(void *opaque)
1196{
1197}
1198static inline int kvm_s390_get_memslot_count(KVMState *s)
1199{
1200 return MAX_AVAIL_SLOTS;
1201}
1202static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1203{
1204 return -ENOSYS;
1205}
1206static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1207{
1208}
1209static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1210 uint64_t *hw_limit)
1211{
1212 return 0;
1213}
1214static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1215{
1216}
1217static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1218{
1219 return 0;
1220}
1221#endif
1222
1223static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1224{
1225 if (kvm_enabled()) {
1226 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1227 }
1228 return 0;
1229}
1230
1231static inline void cmma_reset(S390CPU *cpu)
1232{
1233 if (kvm_enabled()) {
1234 CPUState *cs = CPU(cpu);
1235 kvm_s390_clear_cmma_callback(cs->kvm_state);
1236 }
1237}
1238
1239static inline int s390_cpu_restart(S390CPU *cpu)
1240{
1241 if (kvm_enabled()) {
1242 return kvm_s390_cpu_restart(cpu);
1243 }
1244 return -ENOSYS;
1245}
1246
1247static inline int s390_get_memslot_count(KVMState *s)
1248{
1249 if (kvm_enabled()) {
1250 return kvm_s390_get_memslot_count(s);
1251 } else {
1252 return MAX_AVAIL_SLOTS;
1253 }
1254}
1255
1256void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1257 uint32_t io_int_parm, uint32_t io_int_word);
1258void s390_crw_mchk(void);
1259
1260static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1261 uint32_t sch_id, int vq,
1262 bool assign)
1263{
1264 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1265}
1266
1267#ifdef CONFIG_KVM
1268static inline bool vregs_needed(void *opaque)
1269{
1270 if (kvm_enabled()) {
1271 return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1272 }
1273 return 0;
1274}
1275#else
1276static inline bool vregs_needed(void *opaque)
1277{
1278 return 0;
1279}
1280#endif
1281#endif
1282
