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19#ifndef CPU_ARM_H
20#define CPU_ARM_H
21
22#include "config.h"
23
24#include "kvm-consts.h"
25
26#if defined(TARGET_AARCH64)
27
28# define TARGET_LONG_BITS 64
29# define ELF_MACHINE EM_AARCH64
30#else
31# define TARGET_LONG_BITS 32
32# define ELF_MACHINE EM_ARM
33#endif
34
35#define TARGET_IS_BIENDIAN 1
36
37#define CPUArchState struct CPUARMState
38
39#include "qemu-common.h"
40#include "exec/cpu-defs.h"
41
42#include "fpu/softfloat.h"
43
44#define EXCP_UDEF 1
45#define EXCP_SWI 2
46#define EXCP_PREFETCH_ABORT 3
47#define EXCP_DATA_ABORT 4
48#define EXCP_IRQ 5
49#define EXCP_FIQ 6
50#define EXCP_BKPT 7
51#define EXCP_EXCEPTION_EXIT 8
52#define EXCP_KERNEL_TRAP 9
53#define EXCP_STREX 10
54#define EXCP_HVC 11
55#define EXCP_HYP_TRAP 12
56#define EXCP_SMC 13
57#define EXCP_VIRQ 14
58#define EXCP_VFIQ 15
59
60#define ARMV7M_EXCP_RESET 1
61#define ARMV7M_EXCP_NMI 2
62#define ARMV7M_EXCP_HARD 3
63#define ARMV7M_EXCP_MEM 4
64#define ARMV7M_EXCP_BUS 5
65#define ARMV7M_EXCP_USAGE 6
66#define ARMV7M_EXCP_SVC 11
67#define ARMV7M_EXCP_DEBUG 12
68#define ARMV7M_EXCP_PENDSV 14
69#define ARMV7M_EXCP_SYSTICK 15
70
71
72#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
73#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
74#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
75
76
77
78
79
80
81
82#ifdef HOST_WORDS_BIGENDIAN
83#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
84#define offsetofhigh32(S, M) offsetof(S, M)
85#else
86#define offsetoflow32(S, M) offsetof(S, M)
87#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
88#endif
89
90
91#define ARM_CPU_IRQ 0
92#define ARM_CPU_FIQ 1
93#define ARM_CPU_VIRQ 2
94#define ARM_CPU_VFIQ 3
95
96struct arm_boot_info;
97
98#define NB_MMU_MODES 7
99
100
101
102
103
104
105
106
107
108
109typedef struct ARMGenericTimer {
110 uint64_t cval;
111 uint64_t ctl;
112} ARMGenericTimer;
113
114#define GTIMER_PHYS 0
115#define GTIMER_VIRT 1
116#define NUM_GTIMERS 2
117
118typedef struct {
119 uint64_t raw_tcr;
120 uint32_t mask;
121 uint32_t base_mask;
122} TCR;
123
124typedef struct CPUARMState {
125
126 uint32_t regs[16];
127
128
129
130
131
132
133 uint64_t xregs[32];
134 uint64_t pc;
135
136
137
138
139
140
141
142
143
144
145
146 uint32_t pstate;
147 uint32_t aarch64;
148
149
150
151
152 uint32_t uncached_cpsr;
153 uint32_t spsr;
154
155
156 uint64_t banked_spsr[8];
157 uint32_t banked_r13[8];
158 uint32_t banked_r14[8];
159
160
161 uint32_t usr_regs[5];
162 uint32_t fiq_regs[5];
163
164
165 uint32_t CF;
166 uint32_t VF;
167 uint32_t NF;
168 uint32_t ZF;
169 uint32_t QF;
170 uint32_t GE;
171 uint32_t thumb;
172 uint32_t condexec_bits;
173 uint64_t daif;
174
175 uint64_t elr_el[4];
176 uint64_t sp_el[4];
177
178
179 struct {
180 uint32_t c0_cpuid;
181 union {
182 struct {
183 uint64_t _unused_csselr0;
184 uint64_t csselr_ns;
185 uint64_t _unused_csselr1;
186 uint64_t csselr_s;
187 };
188 uint64_t csselr_el[4];
189 };
190 union {
191 struct {
192 uint64_t _unused_sctlr;
193 uint64_t sctlr_ns;
194 uint64_t hsctlr;
195 uint64_t sctlr_s;
196 };
197 uint64_t sctlr_el[4];
198 };
199 uint64_t cpacr_el1;
200 uint64_t cptr_el[4];
201 uint32_t c1_xscaleauxcr;
202 uint64_t sder;
203 uint32_t nsacr;
204 union {
205 struct {
206 uint64_t _unused_ttbr0_0;
207 uint64_t ttbr0_ns;
208 uint64_t _unused_ttbr0_1;
209 uint64_t ttbr0_s;
210 };
211 uint64_t ttbr0_el[4];
212 };
213 union {
214 struct {
215 uint64_t _unused_ttbr1_0;
216 uint64_t ttbr1_ns;
217 uint64_t _unused_ttbr1_1;
218 uint64_t ttbr1_s;
219 };
220 uint64_t ttbr1_el[4];
221 };
222
223 TCR tcr_el[4];
224 uint32_t c2_data;
225 uint32_t c2_insn;
226 union {
227
228
229 struct {
230 uint64_t dacr_ns;
231 uint64_t dacr_s;
232 };
233 struct {
234 uint64_t dacr32_el2;
235 };
236 };
237 uint32_t pmsav5_data_ap;
238 uint32_t pmsav5_insn_ap;
239 uint64_t hcr_el2;
240 uint64_t scr_el3;
241 union {
242 struct {
243 uint64_t ifsr_ns;
244 uint64_t ifsr_s;
245 };
246 struct {
247 uint64_t ifsr32_el2;
248 };
249 };
250 union {
251 struct {
252 uint64_t _unused_dfsr;
253 uint64_t dfsr_ns;
254 uint64_t hsr;
255 uint64_t dfsr_s;
256 };
257 uint64_t esr_el[4];
258 };
259 uint32_t c6_region[8];
260 union {
261 struct {
262 uint64_t _unused_far0;
263#ifdef HOST_WORDS_BIGENDIAN
264 uint32_t ifar_ns;
265 uint32_t dfar_ns;
266 uint32_t ifar_s;
267 uint32_t dfar_s;
268#else
269 uint32_t dfar_ns;
270 uint32_t ifar_ns;
271 uint32_t dfar_s;
272 uint32_t ifar_s;
273#endif
274 uint64_t _unused_far3;
275 };
276 uint64_t far_el[4];
277 };
278 union {
279 struct {
280 uint64_t _unused_par_0;
281 uint64_t par_ns;
282 uint64_t _unused_par_1;
283 uint64_t par_s;
284 };
285 uint64_t par_el[4];
286 };
287
288 uint32_t c6_rgnr;
289
290 uint32_t c9_insn;
291 uint32_t c9_data;
292 uint64_t c9_pmcr;
293 uint64_t c9_pmcnten;
294 uint32_t c9_pmovsr;
295 uint32_t c9_pmxevtyper;
296 uint32_t c9_pmuserenr;
297 uint32_t c9_pminten;
298 union {
299 struct {
300#ifdef HOST_WORDS_BIGENDIAN
301 uint64_t _unused_mair_0;
302 uint32_t mair1_ns;
303 uint32_t mair0_ns;
304 uint64_t _unused_mair_1;
305 uint32_t mair1_s;
306 uint32_t mair0_s;
307#else
308 uint64_t _unused_mair_0;
309 uint32_t mair0_ns;
310 uint32_t mair1_ns;
311 uint64_t _unused_mair_1;
312 uint32_t mair0_s;
313 uint32_t mair1_s;
314#endif
315 };
316 uint64_t mair_el[4];
317 };
318 union {
319 struct {
320 uint64_t _unused_vbar;
321 uint64_t vbar_ns;
322 uint64_t hvbar;
323 uint64_t vbar_s;
324 };
325 uint64_t vbar_el[4];
326 };
327 uint32_t mvbar;
328 struct {
329 uint32_t fcseidr_ns;
330 uint32_t fcseidr_s;
331 };
332 union {
333 struct {
334 uint64_t _unused_contextidr_0;
335 uint64_t contextidr_ns;
336 uint64_t _unused_contextidr_1;
337 uint64_t contextidr_s;
338 };
339 uint64_t contextidr_el[4];
340 };
341 union {
342 struct {
343 uint64_t tpidrurw_ns;
344 uint64_t tpidrprw_ns;
345 uint64_t htpidr;
346 uint64_t _tpidr_el3;
347 };
348 uint64_t tpidr_el[4];
349 };
350
351 uint64_t tpidrurw_s;
352 uint64_t tpidrprw_s;
353 uint64_t tpidruro_s;
354
355 union {
356 uint64_t tpidruro_ns;
357 uint64_t tpidrro_el[1];
358 };
359 uint64_t c14_cntfrq;
360 uint64_t c14_cntkctl;
361 ARMGenericTimer c14_timer[NUM_GTIMERS];
362 uint32_t c15_cpar;
363 uint32_t c15_ticonfig;
364 uint32_t c15_i_max;
365 uint32_t c15_i_min;
366 uint32_t c15_threadid;
367 uint32_t c15_config_base_address;
368 uint32_t c15_diagnostic;
369 uint32_t c15_power_diagnostic;
370 uint32_t c15_power_control;
371 uint64_t dbgbvr[16];
372 uint64_t dbgbcr[16];
373 uint64_t dbgwvr[16];
374 uint64_t dbgwcr[16];
375 uint64_t mdscr_el1;
376
377
378
379 uint64_t c15_ccnt;
380 uint64_t pmccfiltr_el0;
381 } cp15;
382
383 struct {
384 uint32_t other_sp;
385 uint32_t vecbase;
386 uint32_t basepri;
387 uint32_t control;
388 int current_sp;
389 int exception;
390 } v7m;
391
392
393
394
395
396
397
398 struct {
399 uint32_t syndrome;
400 uint32_t fsr;
401 uint64_t vaddress;
402 uint32_t target_el;
403
404
405
406 } exception;
407
408
409 uint32_t teecr;
410 uint32_t teehbr;
411
412
413 struct {
414
415
416
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418
419
420
421
422
423
424
425
426
427
428
429 float64 regs[64];
430
431 uint32_t xregs[16];
432
433 int vec_len;
434 int vec_stride;
435
436
437 uint32_t scratch[8];
438
439
440
441
442
443
444
445
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447
448
449
450
451 float_status fp_status;
452 float_status standard_fp_status;
453 } vfp;
454 uint64_t exclusive_addr;
455 uint64_t exclusive_val;
456 uint64_t exclusive_high;
457#if defined(CONFIG_USER_ONLY)
458 uint64_t exclusive_test;
459 uint32_t exclusive_info;
460#endif
461
462
463 struct {
464 uint64_t regs[16];
465 uint64_t val;
466
467 uint32_t cregs[16];
468 } iwmmxt;
469
470
471 bool bswap_code;
472
473#if defined(CONFIG_USER_ONLY)
474
475 int eabi;
476#endif
477
478 struct CPUBreakpoint *cpu_breakpoint[16];
479 struct CPUWatchpoint *cpu_watchpoint[16];
480
481 CPU_COMMON
482
483
484
485
486 uint64_t features;
487
488
489 struct {
490 uint32_t *drbar;
491 uint32_t *drsr;
492 uint32_t *dracr;
493 } pmsav7;
494
495 void *nvic;
496 const struct arm_boot_info *boot_info;
497} CPUARMState;
498
499#include "cpu-qom.h"
500
501ARMCPU *cpu_arm_init(const char *cpu_model);
502int cpu_arm_exec(CPUState *cpu);
503uint32_t do_arm_semihosting(CPUARMState *env);
504void aarch64_sync_32_to_64(CPUARMState *env);
505void aarch64_sync_64_to_32(CPUARMState *env);
506
507static inline bool is_a64(CPUARMState *env)
508{
509 return env->aarch64;
510}
511
512
513
514
515int cpu_arm_signal_handler(int host_signum, void *pinfo,
516 void *puc);
517
518
519
520
521
522
523
524
525
526
527void pmccntr_sync(CPUARMState *env);
528
529
530
531
532
533
534
535#define SCTLR_M (1U << 0)
536#define SCTLR_A (1U << 1)
537#define SCTLR_C (1U << 2)
538#define SCTLR_W (1U << 3)
539#define SCTLR_SA (1U << 3)
540#define SCTLR_P (1U << 4)
541#define SCTLR_SA0 (1U << 4)
542#define SCTLR_D (1U << 5)
543#define SCTLR_CP15BEN (1U << 5)
544#define SCTLR_L (1U << 6)
545#define SCTLR_B (1U << 7)
546#define SCTLR_ITD (1U << 7)
547#define SCTLR_S (1U << 8)
548#define SCTLR_SED (1U << 8)
549#define SCTLR_R (1U << 9)
550#define SCTLR_UMA (1U << 9)
551#define SCTLR_F (1U << 10)
552#define SCTLR_SW (1U << 10)
553#define SCTLR_Z (1U << 11)
554#define SCTLR_I (1U << 12)
555#define SCTLR_V (1U << 13)
556#define SCTLR_RR (1U << 14)
557#define SCTLR_DZE (1U << 14)
558#define SCTLR_L4 (1U << 15)
559#define SCTLR_UCT (1U << 15)
560#define SCTLR_DT (1U << 16)
561#define SCTLR_nTWI (1U << 16)
562#define SCTLR_HA (1U << 17)
563#define SCTLR_BR (1U << 17)
564#define SCTLR_IT (1U << 18)
565#define SCTLR_nTWE (1U << 18)
566#define SCTLR_WXN (1U << 19)
567#define SCTLR_ST (1U << 20)
568#define SCTLR_UWXN (1U << 20)
569#define SCTLR_FI (1U << 21)
570#define SCTLR_U (1U << 22)
571#define SCTLR_XP (1U << 23)
572#define SCTLR_VE (1U << 24)
573#define SCTLR_E0E (1U << 24)
574#define SCTLR_EE (1U << 25)
575#define SCTLR_L2 (1U << 26)
576#define SCTLR_UCI (1U << 26)
577#define SCTLR_NMFI (1U << 27)
578#define SCTLR_TRE (1U << 28)
579#define SCTLR_AFE (1U << 29)
580#define SCTLR_TE (1U << 30)
581
582#define CPTR_TCPAC (1U << 31)
583#define CPTR_TTA (1U << 20)
584#define CPTR_TFP (1U << 10)
585
586#define CPSR_M (0x1fU)
587#define CPSR_T (1U << 5)
588#define CPSR_F (1U << 6)
589#define CPSR_I (1U << 7)
590#define CPSR_A (1U << 8)
591#define CPSR_E (1U << 9)
592#define CPSR_IT_2_7 (0xfc00U)
593#define CPSR_GE (0xfU << 16)
594#define CPSR_IL (1U << 20)
595
596
597
598
599
600#define CPSR_RESERVED (0x7U << 21)
601#define CPSR_J (1U << 24)
602#define CPSR_IT_0_1 (3U << 25)
603#define CPSR_Q (1U << 27)
604#define CPSR_V (1U << 28)
605#define CPSR_C (1U << 29)
606#define CPSR_Z (1U << 30)
607#define CPSR_N (1U << 31)
608#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
609#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
610
611#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
612#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
613 | CPSR_NZCV)
614
615#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
616
617#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
618
619#define CPSR_ERET_MASK (~CPSR_RESERVED)
620
621#define TTBCR_N (7U << 0)
622#define TTBCR_T0SZ (7U << 0)
623#define TTBCR_PD0 (1U << 4)
624#define TTBCR_PD1 (1U << 5)
625#define TTBCR_EPD0 (1U << 7)
626#define TTBCR_IRGN0 (3U << 8)
627#define TTBCR_ORGN0 (3U << 10)
628#define TTBCR_SH0 (3U << 12)
629#define TTBCR_T1SZ (3U << 16)
630#define TTBCR_A1 (1U << 22)
631#define TTBCR_EPD1 (1U << 23)
632#define TTBCR_IRGN1 (3U << 24)
633#define TTBCR_ORGN1 (3U << 26)
634#define TTBCR_SH1 (1U << 28)
635#define TTBCR_EAE (1U << 31)
636
637
638
639
640
641#define PSTATE_SP (1U)
642#define PSTATE_M (0xFU)
643#define PSTATE_nRW (1U << 4)
644#define PSTATE_F (1U << 6)
645#define PSTATE_I (1U << 7)
646#define PSTATE_A (1U << 8)
647#define PSTATE_D (1U << 9)
648#define PSTATE_IL (1U << 20)
649#define PSTATE_SS (1U << 21)
650#define PSTATE_V (1U << 28)
651#define PSTATE_C (1U << 29)
652#define PSTATE_Z (1U << 30)
653#define PSTATE_N (1U << 31)
654#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
655#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
656#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
657
658#define PSTATE_MODE_EL3h 13
659#define PSTATE_MODE_EL3t 12
660#define PSTATE_MODE_EL2h 9
661#define PSTATE_MODE_EL2t 8
662#define PSTATE_MODE_EL1h 5
663#define PSTATE_MODE_EL1t 4
664#define PSTATE_MODE_EL0t 0
665
666
667static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
668{
669 return (el << 2) | handler;
670}
671
672
673
674
675
676static inline uint32_t pstate_read(CPUARMState *env)
677{
678 int ZF;
679
680 ZF = (env->ZF == 0);
681 return (env->NF & 0x80000000) | (ZF << 30)
682 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
683 | env->pstate | env->daif;
684}
685
686static inline void pstate_write(CPUARMState *env, uint32_t val)
687{
688 env->ZF = (~val) & PSTATE_Z;
689 env->NF = val;
690 env->CF = (val >> 29) & 1;
691 env->VF = (val << 3) & 0x80000000;
692 env->daif = val & PSTATE_DAIF;
693 env->pstate = val & ~CACHED_PSTATE_BITS;
694}
695
696
697uint32_t cpsr_read(CPUARMState *env);
698
699void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
700
701
702static inline uint32_t xpsr_read(CPUARMState *env)
703{
704 int ZF;
705 ZF = (env->ZF == 0);
706 return (env->NF & 0x80000000) | (ZF << 30)
707 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
708 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
709 | ((env->condexec_bits & 0xfc) << 8)
710 | env->v7m.exception;
711}
712
713
714static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
715{
716 if (mask & CPSR_NZCV) {
717 env->ZF = (~val) & CPSR_Z;
718 env->NF = val;
719 env->CF = (val >> 29) & 1;
720 env->VF = (val << 3) & 0x80000000;
721 }
722 if (mask & CPSR_Q)
723 env->QF = ((val & CPSR_Q) != 0);
724 if (mask & (1 << 24))
725 env->thumb = ((val & (1 << 24)) != 0);
726 if (mask & CPSR_IT_0_1) {
727 env->condexec_bits &= ~3;
728 env->condexec_bits |= (val >> 25) & 3;
729 }
730 if (mask & CPSR_IT_2_7) {
731 env->condexec_bits &= 3;
732 env->condexec_bits |= (val >> 8) & 0xfc;
733 }
734 if (mask & 0x1ff) {
735 env->v7m.exception = val & 0x1ff;
736 }
737}
738
739#define HCR_VM (1ULL << 0)
740#define HCR_SWIO (1ULL << 1)
741#define HCR_PTW (1ULL << 2)
742#define HCR_FMO (1ULL << 3)
743#define HCR_IMO (1ULL << 4)
744#define HCR_AMO (1ULL << 5)
745#define HCR_VF (1ULL << 6)
746#define HCR_VI (1ULL << 7)
747#define HCR_VSE (1ULL << 8)
748#define HCR_FB (1ULL << 9)
749#define HCR_BSU_MASK (3ULL << 10)
750#define HCR_DC (1ULL << 12)
751#define HCR_TWI (1ULL << 13)
752#define HCR_TWE (1ULL << 14)
753#define HCR_TID0 (1ULL << 15)
754#define HCR_TID1 (1ULL << 16)
755#define HCR_TID2 (1ULL << 17)
756#define HCR_TID3 (1ULL << 18)
757#define HCR_TSC (1ULL << 19)
758#define HCR_TIDCP (1ULL << 20)
759#define HCR_TACR (1ULL << 21)
760#define HCR_TSW (1ULL << 22)
761#define HCR_TPC (1ULL << 23)
762#define HCR_TPU (1ULL << 24)
763#define HCR_TTLB (1ULL << 25)
764#define HCR_TVM (1ULL << 26)
765#define HCR_TGE (1ULL << 27)
766#define HCR_TDZ (1ULL << 28)
767#define HCR_HCD (1ULL << 29)
768#define HCR_TRVM (1ULL << 30)
769#define HCR_RW (1ULL << 31)
770#define HCR_CD (1ULL << 32)
771#define HCR_ID (1ULL << 33)
772#define HCR_MASK ((1ULL << 34) - 1)
773
774#define SCR_NS (1U << 0)
775#define SCR_IRQ (1U << 1)
776#define SCR_FIQ (1U << 2)
777#define SCR_EA (1U << 3)
778#define SCR_FW (1U << 4)
779#define SCR_AW (1U << 5)
780#define SCR_NET (1U << 6)
781#define SCR_SMD (1U << 7)
782#define SCR_HCE (1U << 8)
783#define SCR_SIF (1U << 9)
784#define SCR_RW (1U << 10)
785#define SCR_ST (1U << 11)
786#define SCR_TWI (1U << 12)
787#define SCR_TWE (1U << 13)
788#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
789#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
790
791
792uint32_t vfp_get_fpscr(CPUARMState *env);
793void vfp_set_fpscr(CPUARMState *env, uint32_t val);
794
795
796
797
798
799#define FPSR_MASK 0xf800009f
800#define FPCR_MASK 0x07f79f00
801static inline uint32_t vfp_get_fpsr(CPUARMState *env)
802{
803 return vfp_get_fpscr(env) & FPSR_MASK;
804}
805
806static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
807{
808 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
809 vfp_set_fpscr(env, new_fpscr);
810}
811
812static inline uint32_t vfp_get_fpcr(CPUARMState *env)
813{
814 return vfp_get_fpscr(env) & FPCR_MASK;
815}
816
817static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
818{
819 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
820 vfp_set_fpscr(env, new_fpscr);
821}
822
823enum arm_cpu_mode {
824 ARM_CPU_MODE_USR = 0x10,
825 ARM_CPU_MODE_FIQ = 0x11,
826 ARM_CPU_MODE_IRQ = 0x12,
827 ARM_CPU_MODE_SVC = 0x13,
828 ARM_CPU_MODE_MON = 0x16,
829 ARM_CPU_MODE_ABT = 0x17,
830 ARM_CPU_MODE_HYP = 0x1a,
831 ARM_CPU_MODE_UND = 0x1b,
832 ARM_CPU_MODE_SYS = 0x1f
833};
834
835
836#define ARM_VFP_FPSID 0
837#define ARM_VFP_FPSCR 1
838#define ARM_VFP_MVFR2 5
839#define ARM_VFP_MVFR1 6
840#define ARM_VFP_MVFR0 7
841#define ARM_VFP_FPEXC 8
842#define ARM_VFP_FPINST 9
843#define ARM_VFP_FPINST2 10
844
845
846#define ARM_IWMMXT_wCID 0
847#define ARM_IWMMXT_wCon 1
848#define ARM_IWMMXT_wCSSF 2
849#define ARM_IWMMXT_wCASF 3
850#define ARM_IWMMXT_wCGR0 8
851#define ARM_IWMMXT_wCGR1 9
852#define ARM_IWMMXT_wCGR2 10
853#define ARM_IWMMXT_wCGR3 11
854
855
856
857
858
859enum arm_features {
860 ARM_FEATURE_VFP,
861 ARM_FEATURE_AUXCR,
862 ARM_FEATURE_XSCALE,
863 ARM_FEATURE_IWMMXT,
864 ARM_FEATURE_V6,
865 ARM_FEATURE_V6K,
866 ARM_FEATURE_V7,
867 ARM_FEATURE_THUMB2,
868 ARM_FEATURE_MPU,
869 ARM_FEATURE_VFP3,
870 ARM_FEATURE_VFP_FP16,
871 ARM_FEATURE_NEON,
872 ARM_FEATURE_THUMB_DIV,
873 ARM_FEATURE_M,
874 ARM_FEATURE_OMAPCP,
875 ARM_FEATURE_THUMB2EE,
876 ARM_FEATURE_V7MP,
877 ARM_FEATURE_V4T,
878 ARM_FEATURE_V5,
879 ARM_FEATURE_STRONGARM,
880 ARM_FEATURE_VAPA,
881 ARM_FEATURE_ARM_DIV,
882 ARM_FEATURE_VFP4,
883 ARM_FEATURE_GENERIC_TIMER,
884 ARM_FEATURE_MVFR,
885 ARM_FEATURE_DUMMY_C15_REGS,
886 ARM_FEATURE_CACHE_TEST_CLEAN,
887 ARM_FEATURE_CACHE_DIRTY_REG,
888 ARM_FEATURE_CACHE_BLOCK_OPS,
889 ARM_FEATURE_MPIDR,
890 ARM_FEATURE_PXN,
891 ARM_FEATURE_LPAE,
892 ARM_FEATURE_V8,
893 ARM_FEATURE_AARCH64,
894 ARM_FEATURE_V8_AES,
895 ARM_FEATURE_CBAR,
896 ARM_FEATURE_CRC,
897 ARM_FEATURE_CBAR_RO,
898 ARM_FEATURE_EL2,
899 ARM_FEATURE_EL3,
900 ARM_FEATURE_V8_SHA1,
901 ARM_FEATURE_V8_SHA256,
902 ARM_FEATURE_V8_PMULL,
903 ARM_FEATURE_THUMB_DSP,
904};
905
906static inline int arm_feature(CPUARMState *env, int feature)
907{
908 return (env->features & (1ULL << feature)) != 0;
909}
910
911#if !defined(CONFIG_USER_ONLY)
912
913
914
915
916
917
918static inline bool arm_is_secure_below_el3(CPUARMState *env)
919{
920 if (arm_feature(env, ARM_FEATURE_EL3)) {
921 return !(env->cp15.scr_el3 & SCR_NS);
922 } else {
923
924
925
926 return false;
927 }
928}
929
930
931static inline bool arm_is_secure(CPUARMState *env)
932{
933 if (arm_feature(env, ARM_FEATURE_EL3)) {
934 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
935
936 return true;
937 } else if (!is_a64(env) &&
938 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
939
940 return true;
941 }
942 }
943 return arm_is_secure_below_el3(env);
944}
945
946#else
947static inline bool arm_is_secure_below_el3(CPUARMState *env)
948{
949 return false;
950}
951
952static inline bool arm_is_secure(CPUARMState *env)
953{
954 return false;
955}
956#endif
957
958
959static inline bool arm_el_is_aa64(CPUARMState *env, int el)
960{
961
962
963
964
965 assert(el == 1 || el == 3);
966
967
968
969
970
971
972 return arm_feature(env, ARM_FEATURE_AARCH64);
973}
974
975
976
977
978
979
980
981
982static inline bool access_secure_reg(CPUARMState *env)
983{
984 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
985 !arm_el_is_aa64(env, 3) &&
986 !(env->cp15.scr_el3 & SCR_NS));
987
988 return ret;
989}
990
991
992#define A32_BANKED_REG_GET(_env, _regname, _secure) \
993 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
994
995#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
996 do { \
997 if (_secure) { \
998 (_env)->cp15._regname##_s = (_val); \
999 } else { \
1000 (_env)->cp15._regname##_ns = (_val); \
1001 } \
1002 } while (0)
1003
1004
1005
1006
1007
1008
1009#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1010 A32_BANKED_REG_GET((_env), _regname, \
1011 ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))))
1012
1013#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1014 A32_BANKED_REG_SET((_env), _regname, \
1015 ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \
1016 (_val))
1017
1018void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1019uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1020 uint32_t cur_el, bool secure);
1021
1022
1023void armv7m_nvic_set_pending(void *opaque, int irq);
1024int armv7m_nvic_acknowledge_irq(void *opaque);
1025void armv7m_nvic_complete_irq(void *opaque, int irq);
1026
1027
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1038
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1051
1052
1053#define CP_REG_AA64_SHIFT 28
1054#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1055
1056
1057
1058
1059
1060#define CP_REG_NS_SHIFT 29
1061#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1062
1063#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1064 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1065 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1066
1067#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1068 (CP_REG_AA64_MASK | \
1069 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1070 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1071 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1072 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1073 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1074 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1075
1076
1077
1078
1079static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1080{
1081 uint32_t cpregid = kvmid;
1082 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1083 cpregid |= CP_REG_AA64_MASK;
1084 } else {
1085 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1086 cpregid |= (1 << 15);
1087 }
1088
1089
1090
1091
1092 cpregid |= 1 << CP_REG_NS_SHIFT;
1093 }
1094 return cpregid;
1095}
1096
1097
1098
1099
1100static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1101{
1102 uint64_t kvmid;
1103
1104 if (cpregid & CP_REG_AA64_MASK) {
1105 kvmid = cpregid & ~CP_REG_AA64_MASK;
1106 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1107 } else {
1108 kvmid = cpregid & ~(1 << 15);
1109 if (cpregid & (1 << 15)) {
1110 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1111 } else {
1112 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1113 }
1114 }
1115 return kvmid;
1116}
1117
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1139
1140#define ARM_CP_SPECIAL 1
1141#define ARM_CP_CONST 2
1142#define ARM_CP_64BIT 4
1143#define ARM_CP_SUPPRESS_TB_END 8
1144#define ARM_CP_OVERRIDE 16
1145#define ARM_CP_ALIAS 32
1146#define ARM_CP_IO 64
1147#define ARM_CP_NO_RAW 128
1148#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1149#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1150#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1151#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1152#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1153#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1154
1155#define ARM_CP_SENTINEL 0xffff
1156
1157#define ARM_CP_FLAG_MASK 0xff
1158
1159
1160
1161
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1164
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1166
1167
1168enum {
1169 ARM_CP_STATE_AA32 = 0,
1170 ARM_CP_STATE_AA64 = 1,
1171 ARM_CP_STATE_BOTH = 2,
1172};
1173
1174
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1177
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1181
1182
1183
1184enum {
1185 ARM_CP_SECSTATE_S = (1 << 0),
1186 ARM_CP_SECSTATE_NS = (1 << 1),
1187};
1188
1189
1190
1191
1192
1193static inline bool cptype_valid(int cptype)
1194{
1195 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1196 || ((cptype & ARM_CP_SPECIAL) &&
1197 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1198}
1199
1200
1201
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1215
1216
1217#define PL3_R 0x80
1218#define PL3_W 0x40
1219#define PL2_R (0x20 | PL3_R)
1220#define PL2_W (0x10 | PL3_W)
1221#define PL1_R (0x08 | PL2_R)
1222#define PL1_W (0x04 | PL2_W)
1223#define PL0_R (0x02 | PL1_R)
1224#define PL0_W (0x01 | PL1_W)
1225
1226#define PL3_RW (PL3_R | PL3_W)
1227#define PL2_RW (PL2_R | PL2_W)
1228#define PL1_RW (PL1_R | PL1_W)
1229#define PL0_RW (PL0_R | PL0_W)
1230
1231
1232
1233
1234static inline int arm_current_el(CPUARMState *env)
1235{
1236 if (arm_feature(env, ARM_FEATURE_M)) {
1237 return !((env->v7m.exception == 0) && (env->v7m.control & 1));
1238 }
1239
1240 if (is_a64(env)) {
1241 return extract32(env->pstate, 2, 2);
1242 }
1243
1244 switch (env->uncached_cpsr & 0x1f) {
1245 case ARM_CPU_MODE_USR:
1246 return 0;
1247 case ARM_CPU_MODE_HYP:
1248 return 2;
1249 case ARM_CPU_MODE_MON:
1250 return 3;
1251 default:
1252 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1253
1254
1255
1256 return 3;
1257 }
1258
1259 return 1;
1260 }
1261}
1262
1263typedef struct ARMCPRegInfo ARMCPRegInfo;
1264
1265typedef enum CPAccessResult {
1266
1267 CP_ACCESS_OK = 0,
1268
1269
1270
1271
1272
1273
1274 CP_ACCESS_TRAP = 1,
1275
1276
1277
1278
1279 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1280
1281 CP_ACCESS_TRAP_EL2 = 3,
1282 CP_ACCESS_TRAP_EL3 = 4,
1283} CPAccessResult;
1284
1285
1286
1287
1288typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1289typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1290 uint64_t value);
1291
1292typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1293
1294typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1295
1296#define CP_ANY 0xff
1297
1298
1299struct ARMCPRegInfo {
1300
1301 const char *name;
1302
1303
1304
1305
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1313
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1315
1316
1317
1318
1319 uint8_t cp;
1320 uint8_t crn;
1321 uint8_t crm;
1322 uint8_t opc0;
1323 uint8_t opc1;
1324 uint8_t opc2;
1325
1326 int state;
1327
1328 int type;
1329
1330 int access;
1331
1332 int secure;
1333
1334
1335
1336
1337 void *opaque;
1338
1339
1340
1341 uint64_t resetvalue;
1342
1343
1344
1345
1346
1347
1348 ptrdiff_t fieldoffset;
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361 ptrdiff_t bank_fieldoffsets[2];
1362
1363
1364
1365
1366
1367
1368 CPAccessFn *accessfn;
1369
1370
1371
1372
1373 CPReadFn *readfn;
1374
1375
1376
1377
1378 CPWriteFn *writefn;
1379
1380
1381
1382
1383
1384 CPReadFn *raw_readfn;
1385
1386
1387
1388
1389
1390
1391 CPWriteFn *raw_writefn;
1392
1393
1394
1395
1396 CPResetFn *resetfn;
1397};
1398
1399
1400
1401
1402#define CPREG_FIELD32(env, ri) \
1403 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1404#define CPREG_FIELD64(env, ri) \
1405 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1406
1407#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1408
1409void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1410 const ARMCPRegInfo *regs, void *opaque);
1411void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1412 const ARMCPRegInfo *regs, void *opaque);
1413static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1414{
1415 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1416}
1417static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1418{
1419 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1420}
1421const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1422
1423
1424void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1425 uint64_t value);
1426
1427uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1428
1429
1430
1431
1432void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1433
1434
1435
1436
1437static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1438{
1439 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1440}
1441
1442static inline bool cp_access_ok(int current_el,
1443 const ARMCPRegInfo *ri, int isread)
1444{
1445 return (ri->access >> ((current_el * 2) + isread)) & 1;
1446}
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462bool write_list_to_cpustate(ARMCPU *cpu);
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478bool write_cpustate_to_list(ARMCPU *cpu);
1479
1480
1481
1482
1483
1484#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1485
1486#define ARM_CPUID_TI915T 0x54029152
1487#define ARM_CPUID_TI925T 0x54029252
1488
1489#if defined(CONFIG_USER_ONLY)
1490#define TARGET_PAGE_BITS 12
1491#else
1492
1493
1494
1495#define TARGET_PAGE_BITS 10
1496#endif
1497
1498#if defined(TARGET_AARCH64)
1499# define TARGET_PHYS_ADDR_SPACE_BITS 48
1500# define TARGET_VIRT_ADDR_SPACE_BITS 64
1501#else
1502# define TARGET_PHYS_ADDR_SPACE_BITS 40
1503# define TARGET_VIRT_ADDR_SPACE_BITS 32
1504#endif
1505
1506static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
1507 unsigned int target_el)
1508{
1509 CPUARMState *env = cs->env_ptr;
1510 unsigned int cur_el = arm_current_el(env);
1511 bool secure = arm_is_secure(env);
1512 uint32_t scr;
1513 uint32_t hcr;
1514 bool pstate_unmasked;
1515 int8_t unmasked = 0;
1516
1517
1518
1519
1520
1521 if (cur_el > target_el) {
1522 return false;
1523 }
1524
1525 switch (excp_idx) {
1526 case EXCP_FIQ:
1527
1528
1529
1530
1531
1532 hcr = (env->cp15.hcr_el2 & HCR_FMO);
1533 scr = (env->cp15.scr_el3 & SCR_FIQ);
1534
1535
1536
1537
1538
1539
1540 scr &= !((env->cp15.scr_el3 & SCR_FW) && !hcr);
1541 pstate_unmasked = !(env->daif & PSTATE_F);
1542 break;
1543
1544 case EXCP_IRQ:
1545
1546
1547
1548
1549
1550 hcr = (env->cp15.hcr_el2 & HCR_IMO);
1551 scr = false;
1552 pstate_unmasked = !(env->daif & PSTATE_I);
1553 break;
1554
1555 case EXCP_VFIQ:
1556 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1557
1558 return false;
1559 }
1560 return !(env->daif & PSTATE_F);
1561 case EXCP_VIRQ:
1562 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1563
1564 return false;
1565 }
1566 return !(env->daif & PSTATE_I);
1567 default:
1568 g_assert_not_reached();
1569 }
1570
1571
1572
1573
1574
1575 if ((target_el > cur_el) && (target_el != 1)) {
1576 if (arm_el_is_aa64(env, 3) || ((scr || hcr) && (!secure))) {
1577 unmasked = 1;
1578 }
1579 }
1580
1581
1582
1583
1584 return unmasked || pstate_unmasked;
1585}
1586
1587#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1588
1589#define cpu_exec cpu_arm_exec
1590#define cpu_gen_code cpu_arm_gen_code
1591#define cpu_signal_handler cpu_arm_signal_handler
1592#define cpu_list arm_cpu_list
1593
1594
1595
1596
1597
1598
1599
1600
1601
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1603
1604
1605
1606
1607
1608
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1643
1644
1645typedef enum ARMMMUIdx {
1646 ARMMMUIdx_S12NSE0 = 0,
1647 ARMMMUIdx_S12NSE1 = 1,
1648 ARMMMUIdx_S1E2 = 2,
1649 ARMMMUIdx_S1E3 = 3,
1650 ARMMMUIdx_S1SE0 = 4,
1651 ARMMMUIdx_S1SE1 = 5,
1652 ARMMMUIdx_S2NS = 6,
1653
1654
1655
1656 ARMMMUIdx_S1NSE0 = 7,
1657 ARMMMUIdx_S1NSE1 = 8,
1658} ARMMMUIdx;
1659
1660#define MMU_USER_IDX 0
1661
1662
1663static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
1664{
1665 assert(mmu_idx < ARMMMUIdx_S2NS);
1666 return mmu_idx & 3;
1667}
1668
1669
1670static inline int cpu_mmu_index(CPUARMState *env)
1671{
1672 int el = arm_current_el(env);
1673
1674 if (el < 2 && arm_is_secure_below_el3(env)) {
1675 return ARMMMUIdx_S1SE0 + el;
1676 }
1677 return el;
1678}
1679
1680
1681
1682
1683static inline int arm_debug_target_el(CPUARMState *env)
1684{
1685 return 1;
1686}
1687
1688static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
1689{
1690 if (arm_current_el(env) == arm_debug_target_el(env)) {
1691 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
1692 || (env->daif & PSTATE_D)) {
1693 return false;
1694 }
1695 }
1696 return true;
1697}
1698
1699static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
1700{
1701 if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
1702 return aa64_generate_debug_exceptions(env);
1703 }
1704 return arm_current_el(env) != 2;
1705}
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721static inline bool arm_generate_debug_exceptions(CPUARMState *env)
1722{
1723 if (env->aarch64) {
1724 return aa64_generate_debug_exceptions(env);
1725 } else {
1726 return aa32_generate_debug_exceptions(env);
1727 }
1728}
1729
1730
1731
1732
1733static inline bool arm_singlestep_active(CPUARMState *env)
1734{
1735 return extract32(env->cp15.mdscr_el1, 0, 1)
1736 && arm_el_is_aa64(env, arm_debug_target_el(env))
1737 && arm_generate_debug_exceptions(env);
1738}
1739
1740#include "exec/cpu-all.h"
1741
1742
1743
1744
1745
1746
1747#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1748#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1749#define ARM_TBFLAG_MMUIDX_SHIFT 28
1750#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
1751#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
1752#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1753#define ARM_TBFLAG_PSTATE_SS_SHIFT 26
1754#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1755
1756#define ARM_TBFLAG_FPEXC_EL_SHIFT 24
1757#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
1758
1759
1760#define ARM_TBFLAG_THUMB_SHIFT 0
1761#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1762#define ARM_TBFLAG_VECLEN_SHIFT 1
1763#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1764#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1765#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1766#define ARM_TBFLAG_VFPEN_SHIFT 7
1767#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1768#define ARM_TBFLAG_CONDEXEC_SHIFT 8
1769#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1770#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1771#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1772
1773
1774
1775#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
1776#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1777
1778
1779
1780
1781#define ARM_TBFLAG_NS_SHIFT 19
1782#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
1783
1784
1785
1786
1787#define ARM_TBFLAG_AARCH64_STATE(F) \
1788 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1789#define ARM_TBFLAG_MMUIDX(F) \
1790 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
1791#define ARM_TBFLAG_SS_ACTIVE(F) \
1792 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1793#define ARM_TBFLAG_PSTATE_SS(F) \
1794 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
1795#define ARM_TBFLAG_FPEXC_EL(F) \
1796 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
1797#define ARM_TBFLAG_THUMB(F) \
1798 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1799#define ARM_TBFLAG_VECLEN(F) \
1800 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1801#define ARM_TBFLAG_VECSTRIDE(F) \
1802 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1803#define ARM_TBFLAG_VFPEN(F) \
1804 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1805#define ARM_TBFLAG_CONDEXEC(F) \
1806 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1807#define ARM_TBFLAG_BSWAP_CODE(F) \
1808 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1809#define ARM_TBFLAG_XSCALE_CPAR(F) \
1810 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1811#define ARM_TBFLAG_NS(F) \
1812 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
1813
1814
1815
1816
1817static inline int fp_exception_el(CPUARMState *env)
1818{
1819 int fpen;
1820 int cur_el = arm_current_el(env);
1821
1822
1823
1824
1825 if (!arm_feature(env, ARM_FEATURE_V6)) {
1826 return 0;
1827 }
1828
1829
1830
1831
1832
1833
1834 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
1835 switch (fpen) {
1836 case 0:
1837 case 2:
1838 if (cur_el == 0 || cur_el == 1) {
1839
1840 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1841 return 3;
1842 }
1843 return 1;
1844 }
1845 if (cur_el == 3 && !is_a64(env)) {
1846
1847 return 3;
1848 }
1849 break;
1850 case 1:
1851 if (cur_el == 0) {
1852 return 1;
1853 }
1854 break;
1855 case 3:
1856 break;
1857 }
1858
1859
1860
1861
1862
1863
1864 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
1865 && !arm_is_secure_below_el3(env)) {
1866
1867 return 2;
1868 }
1869
1870
1871 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
1872
1873 return 3;
1874 }
1875
1876 return 0;
1877}
1878
1879static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
1880 target_ulong *cs_base, int *flags)
1881{
1882 if (is_a64(env)) {
1883 *pc = env->pc;
1884 *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
1885 } else {
1886 *pc = env->regs[15];
1887 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
1888 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
1889 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
1890 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
1891 | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
1892 if (!(access_secure_reg(env))) {
1893 *flags |= ARM_TBFLAG_NS_MASK;
1894 }
1895 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
1896 || arm_el_is_aa64(env, 1)) {
1897 *flags |= ARM_TBFLAG_VFPEN_MASK;
1898 }
1899 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
1900 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
1901 }
1902
1903 *flags |= (cpu_mmu_index(env) << ARM_TBFLAG_MMUIDX_SHIFT);
1904
1905
1906
1907
1908
1909
1910
1911 if (arm_singlestep_active(env)) {
1912 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
1913 if (is_a64(env)) {
1914 if (env->pstate & PSTATE_SS) {
1915 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1916 }
1917 } else {
1918 if (env->uncached_cpsr & PSTATE_SS) {
1919 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1920 }
1921 }
1922 }
1923 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
1924
1925 *cs_base = 0;
1926}
1927
1928#include "exec/exec-all.h"
1929
1930enum {
1931 QEMU_PSCI_CONDUIT_DISABLED = 0,
1932 QEMU_PSCI_CONDUIT_SMC = 1,
1933 QEMU_PSCI_CONDUIT_HVC = 2,
1934};
1935
1936#endif
1937