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19#include "config.h"
20#include "cpu.h"
21#include "trace.h"
22#include "disas/disas.h"
23#include "tcg.h"
24#include "qemu/atomic.h"
25#include "sysemu/qtest.h"
26#include "qemu/timer.h"
27#include "exec/address-spaces.h"
28#include "qemu/rcu.h"
29#include "exec/tb-hash.h"
30#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
31#include "hw/i386/apic.h"
32#endif
33#include "sysemu/replay.h"
34
35
36
37typedef struct SyncClocks {
38 int64_t diff_clk;
39 int64_t last_cpu_icount;
40 int64_t realtime_clock;
41} SyncClocks;
42
43#if !defined(CONFIG_USER_ONLY)
44
45
46
47
48#define VM_CLOCK_ADVANCE 3000000
49#define THRESHOLD_REDUCE 1.5
50#define MAX_DELAY_PRINT_RATE 2000000000LL
51#define MAX_NB_PRINTS 100
52
53static void align_clocks(SyncClocks *sc, const CPUState *cpu)
54{
55 int64_t cpu_icount;
56
57 if (!icount_align_option) {
58 return;
59 }
60
61 cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
62 sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
63 sc->last_cpu_icount = cpu_icount;
64
65 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
66#ifndef _WIN32
67 struct timespec sleep_delay, rem_delay;
68 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
69 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
70 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
71 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
72 } else {
73 sc->diff_clk = 0;
74 }
75#else
76 Sleep(sc->diff_clk / SCALE_MS);
77 sc->diff_clk = 0;
78#endif
79 }
80}
81
82static void print_delay(const SyncClocks *sc)
83{
84 static float threshold_delay;
85 static int64_t last_realtime_clock;
86 static int nb_prints;
87
88 if (icount_align_option &&
89 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
90 nb_prints < MAX_NB_PRINTS) {
91 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
92 (-sc->diff_clk / (float)1000000000LL <
93 (threshold_delay - THRESHOLD_REDUCE))) {
94 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
95 printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
96 threshold_delay - 1,
97 threshold_delay);
98 nb_prints++;
99 last_realtime_clock = sc->realtime_clock;
100 }
101 }
102}
103
104static void init_delay_params(SyncClocks *sc,
105 const CPUState *cpu)
106{
107 if (!icount_align_option) {
108 return;
109 }
110 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
111 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
112 sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
113 if (sc->diff_clk < max_delay) {
114 max_delay = sc->diff_clk;
115 }
116 if (sc->diff_clk > max_advance) {
117 max_advance = sc->diff_clk;
118 }
119
120
121
122 print_delay(sc);
123}
124#else
125static void align_clocks(SyncClocks *sc, const CPUState *cpu)
126{
127}
128
129static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
130{
131}
132#endif
133
134
135static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
136{
137 CPUArchState *env = cpu->env_ptr;
138 uintptr_t next_tb;
139
140#if defined(DEBUG_DISAS)
141 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
142#if defined(TARGET_I386)
143 log_cpu_state(cpu, CPU_DUMP_CCOP);
144#elif defined(TARGET_M68K)
145
146 cpu_m68k_flush_flags(env, env->cc_op);
147 env->cc_op = CC_OP_FLAGS;
148 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
149 log_cpu_state(cpu, 0);
150#else
151 log_cpu_state(cpu, 0);
152#endif
153 }
154#endif
155
156 cpu->can_do_io = !use_icount;
157 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
158 cpu->can_do_io = 1;
159 trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),
160 next_tb & TB_EXIT_MASK);
161
162 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
163
164
165
166
167 CPUClass *cc = CPU_GET_CLASS(cpu);
168 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
169 if (cc->synchronize_from_tb) {
170 cc->synchronize_from_tb(cpu, tb);
171 } else {
172 assert(cc->set_pc);
173 cc->set_pc(cpu, tb->pc);
174 }
175 }
176 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
177
178
179
180 cpu->tcg_exit_req = 0;
181 }
182 return next_tb;
183}
184
185
186
187static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
188 TranslationBlock *orig_tb, bool ignore_icount)
189{
190 TranslationBlock *tb;
191
192
193
194 if (max_cycles > CF_COUNT_MASK)
195 max_cycles = CF_COUNT_MASK;
196
197 tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
198 max_cycles | CF_NOCACHE
199 | (ignore_icount ? CF_IGNORE_ICOUNT : 0));
200 tb->orig_tb = tcg_ctx.tb_ctx.tb_invalidated_flag ? NULL : orig_tb;
201 cpu->current_tb = tb;
202
203 trace_exec_tb_nocache(tb, tb->pc);
204 cpu_tb_exec(cpu, tb->tc_ptr);
205 cpu->current_tb = NULL;
206 tb_phys_invalidate(tb, -1);
207 tb_free(tb);
208}
209
210static TranslationBlock *tb_find_physical(CPUState *cpu,
211 target_ulong pc,
212 target_ulong cs_base,
213 uint64_t flags)
214{
215 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
216 TranslationBlock *tb, **ptb1;
217 unsigned int h;
218 tb_page_addr_t phys_pc, phys_page1;
219 target_ulong virt_page2;
220
221 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
222
223
224 phys_pc = get_page_addr_code(env, pc);
225 phys_page1 = phys_pc & TARGET_PAGE_MASK;
226 h = tb_phys_hash_func(phys_pc);
227 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
228 for(;;) {
229 tb = *ptb1;
230 if (!tb) {
231 return NULL;
232 }
233 if (tb->pc == pc &&
234 tb->page_addr[0] == phys_page1 &&
235 tb->cs_base == cs_base &&
236 tb->flags == flags) {
237
238 if (tb->page_addr[1] != -1) {
239 tb_page_addr_t phys_page2;
240
241 virt_page2 = (pc & TARGET_PAGE_MASK) +
242 TARGET_PAGE_SIZE;
243 phys_page2 = get_page_addr_code(env, virt_page2);
244 if (tb->page_addr[1] == phys_page2) {
245 break;
246 }
247 } else {
248 break;
249 }
250 }
251 ptb1 = &tb->phys_hash_next;
252 }
253
254
255 *ptb1 = tb->phys_hash_next;
256 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
257 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
258 return tb;
259}
260
261static TranslationBlock *tb_find_slow(CPUState *cpu,
262 target_ulong pc,
263 target_ulong cs_base,
264 uint64_t flags)
265{
266 TranslationBlock *tb;
267
268 tb = tb_find_physical(cpu, pc, cs_base, flags);
269 if (tb) {
270 goto found;
271 }
272
273#ifdef CONFIG_USER_ONLY
274
275
276
277
278
279 tb_unlock();
280 mmap_lock();
281 tb_lock();
282 tb = tb_find_physical(cpu, pc, cs_base, flags);
283 if (tb) {
284 mmap_unlock();
285 goto found;
286 }
287#endif
288
289
290 tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
291
292#ifdef CONFIG_USER_ONLY
293 mmap_unlock();
294#endif
295
296found:
297
298 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
299 return tb;
300}
301
302static inline TranslationBlock *tb_find_fast(CPUState *cpu)
303{
304 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
305 TranslationBlock *tb;
306 target_ulong cs_base, pc;
307 int flags;
308
309
310
311
312 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
313 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
314 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
315 tb->flags != flags)) {
316 tb = tb_find_slow(cpu, pc, cs_base, flags);
317 }
318 return tb;
319}
320
321static void cpu_handle_debug_exception(CPUState *cpu)
322{
323 CPUClass *cc = CPU_GET_CLASS(cpu);
324 CPUWatchpoint *wp;
325
326 if (!cpu->watchpoint_hit) {
327 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
328 wp->flags &= ~BP_WATCHPOINT_HIT;
329 }
330 }
331
332 cc->debug_excp_handler(cpu);
333}
334
335
336
337int cpu_exec(CPUState *cpu)
338{
339 CPUClass *cc = CPU_GET_CLASS(cpu);
340#ifdef TARGET_I386
341 X86CPU *x86_cpu = X86_CPU(cpu);
342 CPUArchState *env = &x86_cpu->env;
343#endif
344 int ret, interrupt_request;
345 TranslationBlock *tb;
346 uint8_t *tc_ptr;
347 uintptr_t next_tb;
348 SyncClocks sc;
349
350
351 current_cpu = cpu;
352
353 if (cpu->halted) {
354#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
355 if ((cpu->interrupt_request & CPU_INTERRUPT_POLL)
356 && replay_interrupt()) {
357 apic_poll_irq(x86_cpu->apic_state);
358 cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
359 }
360#endif
361 if (!cpu_has_work(cpu)) {
362 current_cpu = NULL;
363 return EXCP_HALTED;
364 }
365
366 cpu->halted = 0;
367 }
368
369 atomic_mb_set(&tcg_current_cpu, cpu);
370 rcu_read_lock();
371
372 if (unlikely(atomic_mb_read(&exit_request))) {
373 cpu->exit_request = 1;
374 }
375
376 cc->cpu_exec_enter(cpu);
377
378
379
380
381
382
383 init_delay_params(&sc, cpu);
384
385
386 for(;;) {
387 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
388
389 if (cpu->exception_index >= 0) {
390 if (cpu->exception_index >= EXCP_INTERRUPT) {
391
392 ret = cpu->exception_index;
393 if (ret == EXCP_DEBUG) {
394 cpu_handle_debug_exception(cpu);
395 }
396 cpu->exception_index = -1;
397 break;
398 } else {
399#if defined(CONFIG_USER_ONLY)
400
401
402
403#if defined(TARGET_I386)
404 cc->do_interrupt(cpu);
405#endif
406 ret = cpu->exception_index;
407 cpu->exception_index = -1;
408 break;
409#else
410 if (replay_exception()) {
411 cc->do_interrupt(cpu);
412 cpu->exception_index = -1;
413 } else if (!replay_has_interrupt()) {
414
415 ret = EXCP_INTERRUPT;
416 break;
417 }
418#endif
419 }
420 } else if (replay_has_exception()
421 && cpu->icount_decr.u16.low + cpu->icount_extra == 0) {
422
423 cpu_exec_nocache(cpu, 1, tb_find_fast(cpu), true);
424 ret = -1;
425 break;
426 }
427
428 next_tb = 0;
429 for(;;) {
430 interrupt_request = cpu->interrupt_request;
431 if (unlikely(interrupt_request)) {
432 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
433
434 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
435 }
436 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
437 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
438 cpu->exception_index = EXCP_DEBUG;
439 cpu_loop_exit(cpu);
440 }
441 if (replay_mode == REPLAY_MODE_PLAY
442 && !replay_has_interrupt()) {
443
444 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
445 replay_interrupt();
446 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
447 cpu->halted = 1;
448 cpu->exception_index = EXCP_HLT;
449 cpu_loop_exit(cpu);
450 }
451#if defined(TARGET_I386)
452 else if (interrupt_request & CPU_INTERRUPT_INIT) {
453 replay_interrupt();
454 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0);
455 do_cpu_init(x86_cpu);
456 cpu->exception_index = EXCP_HALTED;
457 cpu_loop_exit(cpu);
458 }
459#else
460 else if (interrupt_request & CPU_INTERRUPT_RESET) {
461 replay_interrupt();
462 cpu_reset(cpu);
463 cpu_loop_exit(cpu);
464 }
465#endif
466
467
468
469
470 else {
471 replay_interrupt();
472 if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
473 next_tb = 0;
474 }
475 }
476
477
478 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
479 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
480
481
482 next_tb = 0;
483 }
484 }
485 if (unlikely(cpu->exit_request
486 || replay_has_interrupt())) {
487 cpu->exit_request = 0;
488 cpu->exception_index = EXCP_INTERRUPT;
489 cpu_loop_exit(cpu);
490 }
491 tb_lock();
492 tb = tb_find_fast(cpu);
493
494
495 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
496
497
498
499 next_tb = 0;
500 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
501 }
502 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
503 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
504 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
505 }
506
507
508
509 if (next_tb != 0 && tb->page_addr[1] == -1
510 && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
511 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
512 next_tb & TB_EXIT_MASK, tb);
513 }
514 tb_unlock();
515 if (likely(!cpu->exit_request)) {
516 trace_exec_tb(tb, tb->pc);
517 tc_ptr = tb->tc_ptr;
518
519 cpu->current_tb = tb;
520 next_tb = cpu_tb_exec(cpu, tc_ptr);
521 cpu->current_tb = NULL;
522 switch (next_tb & TB_EXIT_MASK) {
523 case TB_EXIT_REQUESTED:
524
525
526
527
528
529
530
531
532
533
534 smp_rmb();
535 next_tb = 0;
536 break;
537 case TB_EXIT_ICOUNT_EXPIRED:
538 {
539
540 int insns_left = cpu->icount_decr.u32;
541 if (cpu->icount_extra && insns_left >= 0) {
542
543 cpu->icount_extra += insns_left;
544 insns_left = MIN(0xffff, cpu->icount_extra);
545 cpu->icount_extra -= insns_left;
546 cpu->icount_decr.u16.low = insns_left;
547 } else {
548 if (insns_left > 0) {
549
550 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
551 cpu_exec_nocache(cpu, insns_left, tb, false);
552 align_clocks(&sc, cpu);
553 }
554 cpu->exception_index = EXCP_INTERRUPT;
555 next_tb = 0;
556 cpu_loop_exit(cpu);
557 }
558 break;
559 }
560 default:
561 break;
562 }
563 }
564
565
566 align_clocks(&sc, cpu);
567
568
569 }
570 } else {
571#if defined(__clang__) || !QEMU_GNUC_PREREQ(4, 6)
572
573
574
575
576 cpu = current_cpu;
577 cc = CPU_GET_CLASS(cpu);
578#ifdef TARGET_I386
579 x86_cpu = X86_CPU(cpu);
580 env = &x86_cpu->env;
581#endif
582#else
583
584 g_assert(cpu == current_cpu);
585 g_assert(cc == CPU_GET_CLASS(cpu));
586#ifdef TARGET_I386
587 g_assert(x86_cpu == X86_CPU(cpu));
588 g_assert(env == &x86_cpu->env);
589#endif
590#endif
591 cpu->can_do_io = 1;
592 tb_lock_reset();
593 }
594 }
595
596 cc->cpu_exec_exit(cpu);
597 rcu_read_unlock();
598
599
600 current_cpu = NULL;
601
602
603 atomic_set(&tcg_current_cpu, NULL);
604 return ret;
605}
606