qemu/hw/ide/ich.c
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   1/*
   2 * QEMU ICH Emulation
   3 *
   4 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
   5 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 *
  20 *
  21 * lspci dump of a ICH-9 real device
  22 *
  23 * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
  24 *         Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
  25 *         Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
  26 *         Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
  27 *         Latency: 0
  28 *         Interrupt: pin B routed to IRQ 222
  29 *         Region 0: I/O ports at d000 [size=8]
  30 *         Region 1: I/O ports at cc00 [size=4]
  31 *         Region 2: I/O ports at c880 [size=8]
  32 *         Region 3: I/O ports at c800 [size=4]
  33 *         Region 4: I/O ports at c480 [size=32]
  34 *         Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
  35 *         Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
  36 *                 Address: fee0f00c  Data: 41d9
  37 *         Capabilities: [70] Power Management version 3
  38 *                 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
  39 *                 Status: D0 PME-Enable- DSel=0 DScale=0 PME-
  40 *         Capabilities: [a8] SATA HBA <?>
  41 *         Capabilities: [b0] Vendor Specific Information <?>
  42 *         Kernel driver in use: ahci
  43 *         Kernel modules: ahci
  44 * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
  45 * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
  46 * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
  47 * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
  48 * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
  49 * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  50 * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  51 * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
  52 * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
  53 * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
  54 * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
  55 * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
  56 * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  57 * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  58 * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  59 * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
  60 *
  61 */
  62
  63#include <hw/hw.h>
  64#include <hw/pci/msi.h>
  65#include <hw/i386/pc.h>
  66#include <hw/pci/pci.h>
  67#include <hw/isa/isa.h>
  68#include "sysemu/block-backend.h"
  69#include "sysemu/dma.h"
  70
  71#include <hw/ide/pci.h>
  72#include <hw/ide/ahci.h>
  73
  74#define ICH9_MSI_CAP_OFFSET     0x80
  75#define ICH9_SATA_CAP_OFFSET    0xA8
  76
  77#define ICH9_IDP_BAR            4
  78#define ICH9_MEM_BAR            5
  79
  80#define ICH9_IDP_INDEX          0x10
  81#define ICH9_IDP_INDEX_LOG2     0x04
  82
  83static const VMStateDescription vmstate_ich9_ahci = {
  84    .name = "ich9_ahci",
  85    .version_id = 1,
  86    .fields = (VMStateField[]) {
  87        VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
  88        VMSTATE_AHCI(ahci, AHCIPCIState),
  89        VMSTATE_END_OF_LIST()
  90    },
  91};
  92
  93static void pci_ich9_reset(DeviceState *dev)
  94{
  95    AHCIPCIState *d = ICH_AHCI(dev);
  96
  97    ahci_reset(&d->ahci);
  98}
  99
 100static void pci_ich9_ahci_init(Object *obj)
 101{
 102    struct AHCIPCIState *d = ICH_AHCI(obj);
 103
 104    ahci_init(&d->ahci, DEVICE(obj));
 105}
 106
 107static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
 108{
 109    struct AHCIPCIState *d;
 110    int sata_cap_offset;
 111    uint8_t *sata_cap;
 112    d = ICH_AHCI(dev);
 113
 114    ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
 115
 116    pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
 117
 118    dev->config[PCI_CACHE_LINE_SIZE] = 0x08;  /* Cache line size */
 119    dev->config[PCI_LATENCY_TIMER]   = 0x00;  /* Latency timer */
 120    pci_config_set_interrupt_pin(dev->config, 1);
 121
 122    /* XXX Software should program this register */
 123    dev->config[0x90]   = 1 << 6; /* Address Map Register - AHCI mode */
 124
 125    d->ahci.irq = pci_allocate_irq(dev);
 126
 127    pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
 128                     &d->ahci.idp);
 129    pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
 130                     &d->ahci.mem);
 131
 132    sata_cap_offset = pci_add_capability2(dev, PCI_CAP_ID_SATA,
 133                                          ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
 134                                          errp);
 135    if (sata_cap_offset < 0) {
 136        return;
 137    }
 138
 139    sata_cap = dev->config + sata_cap_offset;
 140    pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
 141    pci_set_long(sata_cap + SATA_CAP_BAR,
 142                 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
 143    d->ahci.idp_offset = ICH9_IDP_INDEX;
 144
 145    /* Although the AHCI 1.3 specification states that the first capability
 146     * should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9
 147     * AHCI device puts the MSI capability first, pointing to 0x80. */
 148    msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false);
 149}
 150
 151static void pci_ich9_uninit(PCIDevice *dev)
 152{
 153    struct AHCIPCIState *d;
 154    d = ICH_AHCI(dev);
 155
 156    msi_uninit(dev);
 157    ahci_uninit(&d->ahci);
 158    qemu_free_irq(d->ahci.irq);
 159}
 160
 161static void ich_ahci_class_init(ObjectClass *klass, void *data)
 162{
 163    DeviceClass *dc = DEVICE_CLASS(klass);
 164    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 165
 166    k->realize = pci_ich9_ahci_realize;
 167    k->exit = pci_ich9_uninit;
 168    k->vendor_id = PCI_VENDOR_ID_INTEL;
 169    k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
 170    k->revision = 0x02;
 171    k->class_id = PCI_CLASS_STORAGE_SATA;
 172    dc->vmsd = &vmstate_ich9_ahci;
 173    dc->reset = pci_ich9_reset;
 174    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 175}
 176
 177static const TypeInfo ich_ahci_info = {
 178    .name          = TYPE_ICH9_AHCI,
 179    .parent        = TYPE_PCI_DEVICE,
 180    .instance_size = sizeof(AHCIPCIState),
 181    .instance_init = pci_ich9_ahci_init,
 182    .class_init    = ich_ahci_class_init,
 183};
 184
 185static void ich_ahci_register_types(void)
 186{
 187    type_register_static(&ich_ahci_info);
 188}
 189
 190type_init(ich_ahci_register_types)
 191