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40#include <assert.h>
41
42#include "hw/hw.h"
43#include "hw/pci/pci.h"
44#include "hw/i386/pc.h"
45#include "hw/mips/mips.h"
46#include "hw/pci/pci_host.h"
47#include "sysemu/sysemu.h"
48#include "exec/address-spaces.h"
49
50
51
52#ifdef DEBUG_BONITO
53#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
54#else
55#define DPRINTF(fmt, ...)
56#endif
57
58
59#define BONITO_BOOT_BASE 0x1fc00000
60#define BONITO_BOOT_SIZE 0x00100000
61#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
62#define BONITO_FLASH_BASE 0x1c000000
63#define BONITO_FLASH_SIZE 0x03000000
64#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
65#define BONITO_SOCKET_BASE 0x1f800000
66#define BONITO_SOCKET_SIZE 0x00400000
67#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
68#define BONITO_REG_BASE 0x1fe00000
69#define BONITO_REG_SIZE 0x00040000
70#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
71#define BONITO_DEV_BASE 0x1ff00000
72#define BONITO_DEV_SIZE 0x00100000
73#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
74#define BONITO_PCILO_BASE 0x10000000
75#define BONITO_PCILO_BASE_VA 0xb0000000
76#define BONITO_PCILO_SIZE 0x0c000000
77#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
78#define BONITO_PCILO0_BASE 0x10000000
79#define BONITO_PCILO1_BASE 0x14000000
80#define BONITO_PCILO2_BASE 0x18000000
81#define BONITO_PCIHI_BASE 0x20000000
82#define BONITO_PCIHI_SIZE 0x20000000
83#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
84#define BONITO_PCIIO_BASE 0x1fd00000
85#define BONITO_PCIIO_BASE_VA 0xbfd00000
86#define BONITO_PCIIO_SIZE 0x00010000
87#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
88#define BONITO_PCICFG_BASE 0x1fe80000
89#define BONITO_PCICFG_SIZE 0x00080000
90#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
91
92
93#define BONITO_PCICONFIGBASE 0x00
94#define BONITO_REGBASE 0x100
95
96#define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
97#define BONITO_PCICONFIG_SIZE (0x100)
98
99#define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE)
100#define BONITO_INTERNAL_REG_SIZE (0x70)
101
102#define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
103#define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
104
105
106
107
108
109
110#define BONITO_BONPONCFG (0x00 >> 2)
111#define BONITO_BONGENCFG_OFFSET 0x4
112#define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2)
113
114
115#define BONITO_IODEVCFG (0x08 >> 2)
116
117
118#define BONITO_SDCFG (0x0c >> 2)
119
120
121#define BONITO_PCIMAP (0x10 >> 2)
122#define BONITO_PCIMEMBASECFG (0x14 >> 2)
123#define BONITO_PCIMAP_CFG (0x18 >> 2)
124
125
126
127#define BONITO_GPIODATA_OFFSET 0x1c
128#define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2)
129#define BONITO_GPIOIE (0x20 >> 2)
130
131
132#define BONITO_INTEDGE (0x24 >> 2)
133#define BONITO_INTSTEER (0x28 >> 2)
134#define BONITO_INTPOL (0x2c >> 2)
135
136
137#define BONITO_INTENSET (0x30 >> 2)
138#define BONITO_INTENCLR (0x34 >> 2)
139#define BONITO_INTEN (0x38 >> 2)
140#define BONITO_INTISR (0x3c >> 2)
141
142
143#define BONITO_PCIMAIL0_OFFSET 0x40
144#define BONITO_PCIMAIL1_OFFSET 0x44
145#define BONITO_PCIMAIL2_OFFSET 0x48
146#define BONITO_PCIMAIL3_OFFSET 0x4c
147#define BONITO_PCIMAIL0 (0x40 >> 2)
148#define BONITO_PCIMAIL1 (0x44 >> 2)
149#define BONITO_PCIMAIL2 (0x48 >> 2)
150#define BONITO_PCIMAIL3 (0x4c >> 2)
151
152
153#define BONITO_PCICACHECTRL (0x50 >> 2)
154#define BONITO_PCICACHETAG (0x54 >> 2)
155#define BONITO_PCIBADADDR (0x58 >> 2)
156#define BONITO_PCIMSTAT (0x5c >> 2)
157
158
159#define BONITO_TIMECFG (0x60 >> 2)
160#define BONITO_CPUCFG (0x64 >> 2)
161#define BONITO_DQCFG (0x68 >> 2)
162#define BONITO_MEMSIZE (0x6C >> 2)
163
164#define BONITO_REGS (0x70 >> 2)
165
166
167#define BONITO_PCICONF_IDSEL_MASK 0xfffff800
168#define BONITO_PCICONF_IDSEL_OFFSET 11
169#define BONITO_PCICONF_FUN_MASK 0x700
170#define BONITO_PCICONF_FUN_OFFSET 8
171#define BONITO_PCICONF_REG_MASK 0xFC
172#define BONITO_PCICONF_REG_OFFSET 0
173
174
175
176#define PCI_SLOT_BASE 12
177#define PCI_IDSEL_VIA686B_BIT (17)
178#define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT)
179
180#define PCI_ADDR(busno,devno,funno,regno) \
181 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
182
183#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
184
185typedef struct BonitoState BonitoState;
186
187typedef struct PCIBonitoState
188{
189 PCIDevice dev;
190
191 BonitoState *pcihost;
192 uint32_t regs[BONITO_REGS];
193
194 struct bonldma {
195 uint32_t ldmactrl;
196 uint32_t ldmastat;
197 uint32_t ldmaaddr;
198 uint32_t ldmago;
199 } bonldma;
200
201
202 struct boncop {
203 uint32_t copctrl;
204 uint32_t copstat;
205 uint32_t coppaddr;
206 uint32_t copgo;
207 } boncop;
208
209
210 MemoryRegion iomem;
211 MemoryRegion iomem_ldma;
212 MemoryRegion iomem_cop;
213 MemoryRegion bonito_pciio;
214 MemoryRegion bonito_localio;
215
216} PCIBonitoState;
217
218#define BONITO_PCI_HOST_BRIDGE(obj) \
219 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE)
220
221struct BonitoState {
222 PCIHostState parent_obj;
223
224 qemu_irq *pic;
225
226 PCIBonitoState *pci_dev;
227};
228
229static void bonito_writel(void *opaque, hwaddr addr,
230 uint64_t val, unsigned size)
231{
232 PCIBonitoState *s = opaque;
233 uint32_t saddr;
234 int reset = 0;
235
236 saddr = addr >> 2;
237
238 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
239 switch (saddr) {
240 case BONITO_BONPONCFG:
241 case BONITO_IODEVCFG:
242 case BONITO_SDCFG:
243 case BONITO_PCIMAP:
244 case BONITO_PCIMEMBASECFG:
245 case BONITO_PCIMAP_CFG:
246 case BONITO_GPIODATA:
247 case BONITO_GPIOIE:
248 case BONITO_INTEDGE:
249 case BONITO_INTSTEER:
250 case BONITO_INTPOL:
251 case BONITO_PCIMAIL0:
252 case BONITO_PCIMAIL1:
253 case BONITO_PCIMAIL2:
254 case BONITO_PCIMAIL3:
255 case BONITO_PCICACHECTRL:
256 case BONITO_PCICACHETAG:
257 case BONITO_PCIBADADDR:
258 case BONITO_PCIMSTAT:
259 case BONITO_TIMECFG:
260 case BONITO_CPUCFG:
261 case BONITO_DQCFG:
262 case BONITO_MEMSIZE:
263 s->regs[saddr] = val;
264 break;
265 case BONITO_BONGENCFG:
266 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
267 reset = 1;
268 }
269 s->regs[saddr] = val;
270 if (reset) {
271 qemu_system_reset_request();
272 }
273 break;
274 case BONITO_INTENSET:
275 s->regs[BONITO_INTENSET] = val;
276 s->regs[BONITO_INTEN] |= val;
277 break;
278 case BONITO_INTENCLR:
279 s->regs[BONITO_INTENCLR] = val;
280 s->regs[BONITO_INTEN] &= ~val;
281 break;
282 case BONITO_INTEN:
283 case BONITO_INTISR:
284 DPRINTF("write to readonly bonito register %x\n", saddr);
285 break;
286 default:
287 DPRINTF("write to unknown bonito register %x\n", saddr);
288 break;
289 }
290}
291
292static uint64_t bonito_readl(void *opaque, hwaddr addr,
293 unsigned size)
294{
295 PCIBonitoState *s = opaque;
296 uint32_t saddr;
297
298 saddr = addr >> 2;
299
300 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
301 switch (saddr) {
302 case BONITO_INTISR:
303 return s->regs[saddr];
304 default:
305 return s->regs[saddr];
306 }
307}
308
309static const MemoryRegionOps bonito_ops = {
310 .read = bonito_readl,
311 .write = bonito_writel,
312 .endianness = DEVICE_NATIVE_ENDIAN,
313 .valid = {
314 .min_access_size = 4,
315 .max_access_size = 4,
316 },
317};
318
319static void bonito_pciconf_writel(void *opaque, hwaddr addr,
320 uint64_t val, unsigned size)
321{
322 PCIBonitoState *s = opaque;
323 PCIDevice *d = PCI_DEVICE(s);
324
325 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
326 d->config_write(d, addr, val, 4);
327}
328
329static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
330 unsigned size)
331{
332
333 PCIBonitoState *s = opaque;
334 PCIDevice *d = PCI_DEVICE(s);
335
336 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
337 return d->config_read(d, addr, 4);
338}
339
340
341
342static const MemoryRegionOps bonito_pciconf_ops = {
343 .read = bonito_pciconf_readl,
344 .write = bonito_pciconf_writel,
345 .endianness = DEVICE_NATIVE_ENDIAN,
346 .valid = {
347 .min_access_size = 4,
348 .max_access_size = 4,
349 },
350};
351
352static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
353 unsigned size)
354{
355 uint32_t val;
356 PCIBonitoState *s = opaque;
357
358 if (addr >= sizeof(s->bonldma)) {
359 return 0;
360 }
361
362 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
363
364 return val;
365}
366
367static void bonito_ldma_writel(void *opaque, hwaddr addr,
368 uint64_t val, unsigned size)
369{
370 PCIBonitoState *s = opaque;
371
372 if (addr >= sizeof(s->bonldma)) {
373 return;
374 }
375
376 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
377}
378
379static const MemoryRegionOps bonito_ldma_ops = {
380 .read = bonito_ldma_readl,
381 .write = bonito_ldma_writel,
382 .endianness = DEVICE_NATIVE_ENDIAN,
383 .valid = {
384 .min_access_size = 4,
385 .max_access_size = 4,
386 },
387};
388
389static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
390 unsigned size)
391{
392 uint32_t val;
393 PCIBonitoState *s = opaque;
394
395 if (addr >= sizeof(s->boncop)) {
396 return 0;
397 }
398
399 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
400
401 return val;
402}
403
404static void bonito_cop_writel(void *opaque, hwaddr addr,
405 uint64_t val, unsigned size)
406{
407 PCIBonitoState *s = opaque;
408
409 if (addr >= sizeof(s->boncop)) {
410 return;
411 }
412
413 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
414}
415
416static const MemoryRegionOps bonito_cop_ops = {
417 .read = bonito_cop_readl,
418 .write = bonito_cop_writel,
419 .endianness = DEVICE_NATIVE_ENDIAN,
420 .valid = {
421 .min_access_size = 4,
422 .max_access_size = 4,
423 },
424};
425
426static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
427{
428 PCIBonitoState *s = opaque;
429 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
430 uint32_t cfgaddr;
431 uint32_t idsel;
432 uint32_t devno;
433 uint32_t funno;
434 uint32_t regno;
435 uint32_t pciaddr;
436
437
438 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
439 return 0xffffffff;
440 }
441
442 cfgaddr = addr & 0xffff;
443 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
444
445 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
446 devno = ctz32(idsel);
447 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
448 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
449
450 if (idsel == 0) {
451 fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx
452 ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]);
453 exit(1);
454 }
455 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
456 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
457 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
458
459 return pciaddr;
460}
461
462static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
463 uint32_t val)
464{
465 PCIBonitoState *s = opaque;
466 PCIDevice *d = PCI_DEVICE(s);
467 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
468 uint32_t pciaddr;
469 uint16_t status;
470
471 DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
472 pciaddr = bonito_sbridge_pciaddr(s, addr);
473
474 if (pciaddr == 0xffffffff) {
475 return;
476 }
477
478
479 phb->config_reg = (pciaddr) | (1u << 31);
480 pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1);
481
482
483 status = pci_get_word(d->config + PCI_STATUS);
484 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
485 pci_set_word(d->config + PCI_STATUS, status);
486}
487
488static void bonito_spciconf_writew(void *opaque, hwaddr addr,
489 uint32_t val)
490{
491 PCIBonitoState *s = opaque;
492 PCIDevice *d = PCI_DEVICE(s);
493 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
494 uint32_t pciaddr;
495 uint16_t status;
496
497 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
498 assert((addr & 0x1) == 0);
499
500 pciaddr = bonito_sbridge_pciaddr(s, addr);
501
502 if (pciaddr == 0xffffffff) {
503 return;
504 }
505
506
507 phb->config_reg = (pciaddr) | (1u << 31);
508 pci_data_write(phb->bus, phb->config_reg, val, 2);
509
510
511 status = pci_get_word(d->config + PCI_STATUS);
512 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
513 pci_set_word(d->config + PCI_STATUS, status);
514}
515
516static void bonito_spciconf_writel(void *opaque, hwaddr addr,
517 uint32_t val)
518{
519 PCIBonitoState *s = opaque;
520 PCIDevice *d = PCI_DEVICE(s);
521 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
522 uint32_t pciaddr;
523 uint16_t status;
524
525 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
526 assert((addr & 0x3) == 0);
527
528 pciaddr = bonito_sbridge_pciaddr(s, addr);
529
530 if (pciaddr == 0xffffffff) {
531 return;
532 }
533
534
535 phb->config_reg = (pciaddr) | (1u << 31);
536 pci_data_write(phb->bus, phb->config_reg, val, 4);
537
538
539 status = pci_get_word(d->config + PCI_STATUS);
540 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
541 pci_set_word(d->config + PCI_STATUS, status);
542}
543
544static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
545{
546 PCIBonitoState *s = opaque;
547 PCIDevice *d = PCI_DEVICE(s);
548 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
549 uint32_t pciaddr;
550 uint16_t status;
551
552 DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
553 pciaddr = bonito_sbridge_pciaddr(s, addr);
554
555 if (pciaddr == 0xffffffff) {
556 return 0xff;
557 }
558
559
560 phb->config_reg = (pciaddr) | (1u << 31);
561
562
563 status = pci_get_word(d->config + PCI_STATUS);
564 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
565 pci_set_word(d->config + PCI_STATUS, status);
566
567 return pci_data_read(phb->bus, phb->config_reg, 1);
568}
569
570static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
571{
572 PCIBonitoState *s = opaque;
573 PCIDevice *d = PCI_DEVICE(s);
574 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
575 uint32_t pciaddr;
576 uint16_t status;
577
578 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
579 assert((addr & 0x1) == 0);
580
581 pciaddr = bonito_sbridge_pciaddr(s, addr);
582
583 if (pciaddr == 0xffffffff) {
584 return 0xffff;
585 }
586
587
588 phb->config_reg = (pciaddr) | (1u << 31);
589
590
591 status = pci_get_word(d->config + PCI_STATUS);
592 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
593 pci_set_word(d->config + PCI_STATUS, status);
594
595 return pci_data_read(phb->bus, phb->config_reg, 2);
596}
597
598static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
599{
600 PCIBonitoState *s = opaque;
601 PCIDevice *d = PCI_DEVICE(s);
602 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
603 uint32_t pciaddr;
604 uint16_t status;
605
606 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
607 assert((addr & 0x3) == 0);
608
609 pciaddr = bonito_sbridge_pciaddr(s, addr);
610
611 if (pciaddr == 0xffffffff) {
612 return 0xffffffff;
613 }
614
615
616 phb->config_reg = (pciaddr) | (1u << 31);
617
618
619 status = pci_get_word(d->config + PCI_STATUS);
620 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
621 pci_set_word(d->config + PCI_STATUS, status);
622
623 return pci_data_read(phb->bus, phb->config_reg, 4);
624}
625
626
627static const MemoryRegionOps bonito_spciconf_ops = {
628 .old_mmio = {
629 .read = {
630 bonito_spciconf_readb,
631 bonito_spciconf_readw,
632 bonito_spciconf_readl,
633 },
634 .write = {
635 bonito_spciconf_writeb,
636 bonito_spciconf_writew,
637 bonito_spciconf_writel,
638 },
639 },
640 .endianness = DEVICE_NATIVE_ENDIAN,
641};
642
643#define BONITO_IRQ_BASE 32
644
645static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
646{
647 BonitoState *s = opaque;
648 qemu_irq *pic = s->pic;
649 PCIBonitoState *bonito_state = s->pci_dev;
650 int internal_irq = irq_num - BONITO_IRQ_BASE;
651
652 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
653 qemu_irq_pulse(*pic);
654 } else {
655 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
656 qemu_irq_raise(*pic);
657 } else {
658 qemu_irq_lower(*pic);
659 }
660 }
661}
662
663
664static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
665{
666 int slot;
667
668 slot = (pci_dev->devfn >> 3);
669
670 switch (slot) {
671 case 5:
672 return irq_num % 4 + BONITO_IRQ_BASE;
673 case 6:
674 return 4 + BONITO_IRQ_BASE;
675 case 7:
676 return 5 + BONITO_IRQ_BASE;
677 case 8 ... 12:
678 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
679 default:
680 return irq_num;
681 }
682}
683
684static void bonito_reset(void *opaque)
685{
686 PCIBonitoState *s = opaque;
687
688
689
690 s->regs[BONITO_BONPONCFG] = 0xc40;
691 s->regs[BONITO_BONGENCFG] = 0x1384;
692 s->regs[BONITO_IODEVCFG] = 0x2bff8010;
693 s->regs[BONITO_SDCFG] = 0x255e0091;
694
695 s->regs[BONITO_GPIODATA] = 0x1ff;
696 s->regs[BONITO_GPIOIE] = 0x1ff;
697 s->regs[BONITO_DQCFG] = 0x8;
698 s->regs[BONITO_MEMSIZE] = 0x10000000;
699 s->regs[BONITO_PCIMAP] = 0x6140;
700}
701
702static const VMStateDescription vmstate_bonito = {
703 .name = "Bonito",
704 .version_id = 1,
705 .minimum_version_id = 1,
706 .fields = (VMStateField[]) {
707 VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
708 VMSTATE_END_OF_LIST()
709 }
710};
711
712static int bonito_pcihost_initfn(SysBusDevice *dev)
713{
714 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
715
716 phb->bus = pci_register_bus(DEVICE(dev), "pci",
717 pci_bonito_set_irq, pci_bonito_map_irq, dev,
718 get_system_memory(), get_system_io(),
719 0x28, 32, TYPE_PCI_BUS);
720
721 return 0;
722}
723
724static void bonito_realize(PCIDevice *dev, Error **errp)
725{
726 PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
727 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
728 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
729
730
731 pci_config_set_prog_interface(dev->config, 0x00);
732
733
734 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
735 "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
736 sysbus_init_mmio(sysbus, &s->iomem);
737 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
738
739
740 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
741 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
742 sysbus_init_mmio(sysbus, &phb->conf_mem);
743 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
744
745
746 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
747 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
748 sysbus_init_mmio(sysbus, &phb->data_mem);
749 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
750
751 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
752 "ldma", 0x100);
753 sysbus_init_mmio(sysbus, &s->iomem_ldma);
754 sysbus_mmio_map(sysbus, 3, 0xbfe00200);
755
756 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
757 "cop", 0x100);
758 sysbus_init_mmio(sysbus, &s->iomem_cop);
759 sysbus_mmio_map(sysbus, 4, 0xbfe00300);
760
761
762 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
763 get_system_io(), 0, BONITO_PCIIO_SIZE);
764 sysbus_init_mmio(sysbus, &s->bonito_pciio);
765 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
766
767
768 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio",
769 get_system_io(), 0, BONITO_DEV_SIZE);
770 sysbus_init_mmio(sysbus, &s->bonito_localio);
771 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
772
773
774 pci_set_word(dev->config + PCI_COMMAND, 0x0000);
775 pci_set_word(dev->config + PCI_STATUS, 0x0000);
776 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
777 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
778
779 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
780 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
781 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
782 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
783
784 qemu_register_reset(bonito_reset, s);
785}
786
787PCIBus *bonito_init(qemu_irq *pic)
788{
789 DeviceState *dev;
790 BonitoState *pcihost;
791 PCIHostState *phb;
792 PCIBonitoState *s;
793 PCIDevice *d;
794
795 dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE);
796 phb = PCI_HOST_BRIDGE(dev);
797 pcihost = BONITO_PCI_HOST_BRIDGE(dev);
798 pcihost->pic = pic;
799 qdev_init_nofail(dev);
800
801
802 d = pci_create(phb->bus, PCI_DEVFN(0, 0), "Bonito");
803 s = DO_UPCAST(PCIBonitoState, dev, d);
804 s->pcihost = pcihost;
805 pcihost->pci_dev = s;
806 qdev_init_nofail(DEVICE(d));
807
808 return phb->bus;
809}
810
811static void bonito_class_init(ObjectClass *klass, void *data)
812{
813 DeviceClass *dc = DEVICE_CLASS(klass);
814 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
815
816 k->realize = bonito_realize;
817 k->vendor_id = 0xdf53;
818 k->device_id = 0x00d5;
819 k->revision = 0x01;
820 k->class_id = PCI_CLASS_BRIDGE_HOST;
821 dc->desc = "Host bridge";
822 dc->vmsd = &vmstate_bonito;
823
824
825
826
827 dc->cannot_instantiate_with_device_add_yet = true;
828}
829
830static const TypeInfo bonito_info = {
831 .name = "Bonito",
832 .parent = TYPE_PCI_DEVICE,
833 .instance_size = sizeof(PCIBonitoState),
834 .class_init = bonito_class_init,
835};
836
837static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
838{
839 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
840
841 k->init = bonito_pcihost_initfn;
842}
843
844static const TypeInfo bonito_pcihost_info = {
845 .name = TYPE_BONITO_PCI_HOST_BRIDGE,
846 .parent = TYPE_PCI_HOST_BRIDGE,
847 .instance_size = sizeof(BonitoState),
848 .class_init = bonito_pcihost_class_init,
849};
850
851static void bonito_register_types(void)
852{
853 type_register_static(&bonito_pcihost_info);
854 type_register_static(&bonito_info);
855}
856
857type_init(bonito_register_types)
858