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25#include "hw/hw.h"
26#include "hw/i386/pc.h"
27#include "hw/pci/pci.h"
28#include "hw/pci/pci_host.h"
29#include "hw/isa/isa.h"
30#include "hw/sysbus.h"
31#include "qemu/range.h"
32#include "hw/xen/xen.h"
33#include "hw/pci-host/pam.h"
34#include "sysemu/sysemu.h"
35#include "hw/i386/ioapic.h"
36#include "qapi/visitor.h"
37#include "qemu/error-report.h"
38
39
40
41
42
43
44#define I440FX_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
46
47typedef struct I440FXState {
48 PCIHostState parent_obj;
49 PcPciInfo pci_info;
50 uint64_t pci_hole64_size;
51 uint32_t short_root_bus;
52} I440FXState;
53
54#define PIIX_NUM_PIC_IRQS 16
55#define PIIX_NUM_PIRQS 4ULL
56#define XEN_PIIX_NUM_PIRQS 128ULL
57#define PIIX_PIRQC 0x60
58
59
60
61
62
63#define RCR_IOPORT 0xcf9
64
65typedef struct PIIX3State {
66 PCIDevice dev;
67
68
69
70
71
72
73
74
75
76
77#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
78#error "unable to encode pic state in 64bit in pic_levels."
79#endif
80 uint64_t pic_levels;
81
82 qemu_irq *pic;
83
84
85 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
86
87
88 uint8_t rcr;
89
90
91 MemoryRegion rcr_mem;
92} PIIX3State;
93
94#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
95#define PIIX3_PCI_DEVICE(obj) \
96 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
97
98#define I440FX_PCI_DEVICE(obj) \
99 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
100
101struct PCII440FXState {
102
103 PCIDevice parent_obj;
104
105
106 MemoryRegion *system_memory;
107 MemoryRegion *pci_address_space;
108 MemoryRegion *ram_memory;
109 PAMMemoryRegion pam_regions[13];
110 MemoryRegion smram_region;
111 MemoryRegion smram, low_smram;
112};
113
114
115#define I440FX_PAM 0x59
116#define I440FX_PAM_SIZE 7
117#define I440FX_SMRAM 0x72
118
119
120
121
122#define I440FX_COREBOOT_RAM_SIZE 0x57
123
124static void piix3_set_irq(void *opaque, int pirq, int level);
125static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
126static void piix3_write_config_xen(PCIDevice *dev,
127 uint32_t address, uint32_t val, int len);
128
129
130
131
132static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
133{
134 int slot_addend;
135 slot_addend = (pci_dev->devfn >> 3) - 1;
136 return (pci_intx + slot_addend) & 3;
137}
138
139static void i440fx_update_memory_mappings(PCII440FXState *d)
140{
141 int i;
142 PCIDevice *pd = PCI_DEVICE(d);
143
144 memory_region_transaction_begin();
145 for (i = 0; i < 13; i++) {
146 pam_update(&d->pam_regions[i], i,
147 pd->config[I440FX_PAM + ((i + 1) / 2)]);
148 }
149 memory_region_set_enabled(&d->smram_region,
150 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
151 memory_region_set_enabled(&d->smram,
152 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
153 memory_region_transaction_commit();
154}
155
156
157static void i440fx_write_config(PCIDevice *dev,
158 uint32_t address, uint32_t val, int len)
159{
160 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
161
162
163 pci_default_write_config(dev, address, val, len);
164 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
165 range_covers_byte(address, len, I440FX_SMRAM)) {
166 i440fx_update_memory_mappings(d);
167 }
168}
169
170static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
171{
172 PCII440FXState *d = opaque;
173 PCIDevice *pd = PCI_DEVICE(d);
174 int ret, i;
175 uint8_t smm_enabled;
176
177 ret = pci_device_load(pd, f);
178 if (ret < 0)
179 return ret;
180 i440fx_update_memory_mappings(d);
181 qemu_get_8s(f, &smm_enabled);
182
183 if (version_id == 2) {
184 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
185 qemu_get_be32(f);
186 }
187 }
188
189 return 0;
190}
191
192static int i440fx_post_load(void *opaque, int version_id)
193{
194 PCII440FXState *d = opaque;
195
196 i440fx_update_memory_mappings(d);
197 return 0;
198}
199
200static const VMStateDescription vmstate_i440fx = {
201 .name = "I440FX",
202 .version_id = 3,
203 .minimum_version_id = 3,
204 .minimum_version_id_old = 1,
205 .load_state_old = i440fx_load_old,
206 .post_load = i440fx_post_load,
207 .fields = (VMStateField[]) {
208 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
209
210
211
212 VMSTATE_UNUSED(1),
213 VMSTATE_END_OF_LIST()
214 }
215};
216
217static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
218 void *opaque, const char *name,
219 Error **errp)
220{
221 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
222 uint32_t value = s->pci_info.w32.begin;
223
224 visit_type_uint32(v, &value, name, errp);
225}
226
227static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
228 void *opaque, const char *name,
229 Error **errp)
230{
231 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
232 uint32_t value = s->pci_info.w32.end;
233
234 visit_type_uint32(v, &value, name, errp);
235}
236
237static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
238 void *opaque, const char *name,
239 Error **errp)
240{
241 PCIHostState *h = PCI_HOST_BRIDGE(obj);
242 Range w64;
243
244 pci_bus_get_w64_range(h->bus, &w64);
245
246 visit_type_uint64(v, &w64.begin, name, errp);
247}
248
249static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
250 void *opaque, const char *name,
251 Error **errp)
252{
253 PCIHostState *h = PCI_HOST_BRIDGE(obj);
254 Range w64;
255
256 pci_bus_get_w64_range(h->bus, &w64);
257
258 visit_type_uint64(v, &w64.end, name, errp);
259}
260
261static void i440fx_pcihost_initfn(Object *obj)
262{
263 PCIHostState *s = PCI_HOST_BRIDGE(obj);
264 I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
265
266 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
267 "pci-conf-idx", 4);
268 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
269 "pci-conf-data", 4);
270
271 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
272 i440fx_pcihost_get_pci_hole_start,
273 NULL, NULL, NULL, NULL);
274
275 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
276 i440fx_pcihost_get_pci_hole_end,
277 NULL, NULL, NULL, NULL);
278
279 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
280 i440fx_pcihost_get_pci_hole64_start,
281 NULL, NULL, NULL, NULL);
282
283 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
284 i440fx_pcihost_get_pci_hole64_end,
285 NULL, NULL, NULL, NULL);
286
287 d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
288}
289
290static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
291{
292 PCIHostState *s = PCI_HOST_BRIDGE(dev);
293 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
294
295 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
296 sysbus_init_ioports(sbd, 0xcf8, 4);
297
298 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
299 sysbus_init_ioports(sbd, 0xcfc, 4);
300}
301
302static void i440fx_realize(PCIDevice *dev, Error **errp)
303{
304 dev->config[I440FX_SMRAM] = 0x02;
305
306 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
307 error_report("warning: i440fx doesn't support emulated iommu");
308 }
309}
310
311PCIBus *i440fx_init(const char *host_type, const char *pci_type,
312 PCII440FXState **pi440fx_state,
313 int *piix3_devfn,
314 ISABus **isa_bus, qemu_irq *pic,
315 MemoryRegion *address_space_mem,
316 MemoryRegion *address_space_io,
317 ram_addr_t ram_size,
318 ram_addr_t below_4g_mem_size,
319 ram_addr_t above_4g_mem_size,
320 MemoryRegion *pci_address_space,
321 MemoryRegion *ram_memory)
322{
323 DeviceState *dev;
324 PCIBus *b;
325 PCIDevice *d;
326 PCIHostState *s;
327 PIIX3State *piix3;
328 PCII440FXState *f;
329 unsigned i;
330 I440FXState *i440fx;
331
332 dev = qdev_create(NULL, host_type);
333 s = PCI_HOST_BRIDGE(dev);
334 b = pci_bus_new(dev, NULL, pci_address_space,
335 address_space_io, 0, TYPE_PCI_BUS);
336 s->bus = b;
337 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
338 qdev_init_nofail(dev);
339
340 d = pci_create_simple(b, 0, pci_type);
341 *pi440fx_state = I440FX_PCI_DEVICE(d);
342 f = *pi440fx_state;
343 f->system_memory = address_space_mem;
344 f->pci_address_space = pci_address_space;
345 f->ram_memory = ram_memory;
346
347 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
348 i440fx->pci_info.w32.begin = below_4g_mem_size;
349
350
351 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
352 f->pci_address_space);
353
354
355 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
356 f->pci_address_space, 0xa0000, 0x20000);
357 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
358 &f->smram_region, 1);
359 memory_region_set_enabled(&f->smram_region, true);
360
361
362 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
363 memory_region_set_enabled(&f->smram, true);
364 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
365 f->ram_memory, 0xa0000, 0x20000);
366 memory_region_set_enabled(&f->low_smram, true);
367 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
368 object_property_add_const_link(qdev_get_machine(), "smram",
369 OBJECT(&f->smram), &error_abort);
370
371 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
372 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
373 for (i = 0; i < 12; ++i) {
374 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
375 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
376 PAM_EXPAN_SIZE);
377 }
378
379
380
381
382
383 if (xen_enabled()) {
384 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
385 -1, true, "PIIX3-xen");
386 piix3 = PIIX3_PCI_DEVICE(pci_dev);
387 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
388 piix3, XEN_PIIX_NUM_PIRQS);
389 } else {
390 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
391 -1, true, "PIIX3");
392 piix3 = PIIX3_PCI_DEVICE(pci_dev);
393 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
394 PIIX_NUM_PIRQS);
395 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
396 }
397 piix3->pic = pic;
398 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
399
400 *piix3_devfn = piix3->dev.devfn;
401
402 ram_size = ram_size / 8 / 1024 / 1024;
403 if (ram_size > 255) {
404 ram_size = 255;
405 }
406 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
407
408 i440fx_update_memory_mappings(f);
409
410 return b;
411}
412
413PCIBus *find_i440fx(void)
414{
415 PCIHostState *s = OBJECT_CHECK(PCIHostState,
416 object_resolve_path("/machine/i440fx", NULL),
417 TYPE_PCI_HOST_BRIDGE);
418 return s ? s->bus : NULL;
419}
420
421
422static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
423{
424 qemu_set_irq(piix3->pic[pic_irq],
425 !!(piix3->pic_levels &
426 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
427 (pic_irq * PIIX_NUM_PIRQS))));
428}
429
430static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
431{
432 int pic_irq;
433 uint64_t mask;
434
435 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
436 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
437 return;
438 }
439
440 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
441 piix3->pic_levels &= ~mask;
442 piix3->pic_levels |= mask * !!level;
443}
444
445static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
446{
447 int pic_irq;
448
449 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
450 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
451 return;
452 }
453
454 piix3_set_irq_level_internal(piix3, pirq, level);
455
456 piix3_set_irq_pic(piix3, pic_irq);
457}
458
459static void piix3_set_irq(void *opaque, int pirq, int level)
460{
461 PIIX3State *piix3 = opaque;
462 piix3_set_irq_level(piix3, pirq, level);
463}
464
465static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
466{
467 PIIX3State *piix3 = opaque;
468 int irq = piix3->dev.config[PIIX_PIRQC + pin];
469 PCIINTxRoute route;
470
471 if (irq < PIIX_NUM_PIC_IRQS) {
472 route.mode = PCI_INTX_ENABLED;
473 route.irq = irq;
474 } else {
475 route.mode = PCI_INTX_DISABLED;
476 route.irq = -1;
477 }
478 return route;
479}
480
481
482static void piix3_update_irq_levels(PIIX3State *piix3)
483{
484 int pirq;
485
486 piix3->pic_levels = 0;
487 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
488 piix3_set_irq_level(piix3, pirq,
489 pci_bus_get_irq_level(piix3->dev.bus, pirq));
490 }
491}
492
493static void piix3_write_config(PCIDevice *dev,
494 uint32_t address, uint32_t val, int len)
495{
496 pci_default_write_config(dev, address, val, len);
497 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
498 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
499 int pic_irq;
500
501 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
502 piix3_update_irq_levels(piix3);
503 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
504 piix3_set_irq_pic(piix3, pic_irq);
505 }
506 }
507}
508
509static void piix3_write_config_xen(PCIDevice *dev,
510 uint32_t address, uint32_t val, int len)
511{
512 xen_piix_pci_write_config_client(address, val, len);
513 piix3_write_config(dev, address, val, len);
514}
515
516static void piix3_reset(void *opaque)
517{
518 PIIX3State *d = opaque;
519 uint8_t *pci_conf = d->dev.config;
520
521 pci_conf[0x04] = 0x07;
522 pci_conf[0x05] = 0x00;
523 pci_conf[0x06] = 0x00;
524 pci_conf[0x07] = 0x02;
525 pci_conf[0x4c] = 0x4d;
526 pci_conf[0x4e] = 0x03;
527 pci_conf[0x4f] = 0x00;
528 pci_conf[0x60] = 0x80;
529 pci_conf[0x61] = 0x80;
530 pci_conf[0x62] = 0x80;
531 pci_conf[0x63] = 0x80;
532 pci_conf[0x69] = 0x02;
533 pci_conf[0x70] = 0x80;
534 pci_conf[0x76] = 0x0c;
535 pci_conf[0x77] = 0x0c;
536 pci_conf[0x78] = 0x02;
537 pci_conf[0x79] = 0x00;
538 pci_conf[0x80] = 0x00;
539 pci_conf[0x82] = 0x00;
540 pci_conf[0xa0] = 0x08;
541 pci_conf[0xa2] = 0x00;
542 pci_conf[0xa3] = 0x00;
543 pci_conf[0xa4] = 0x00;
544 pci_conf[0xa5] = 0x00;
545 pci_conf[0xa6] = 0x00;
546 pci_conf[0xa7] = 0x00;
547 pci_conf[0xa8] = 0x0f;
548 pci_conf[0xaa] = 0x00;
549 pci_conf[0xab] = 0x00;
550 pci_conf[0xac] = 0x00;
551 pci_conf[0xae] = 0x00;
552
553 d->pic_levels = 0;
554 d->rcr = 0;
555}
556
557static int piix3_post_load(void *opaque, int version_id)
558{
559 PIIX3State *piix3 = opaque;
560 int pirq;
561
562
563
564
565
566
567
568
569
570 piix3->pic_levels = 0;
571 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
572 piix3_set_irq_level_internal(piix3, pirq,
573 pci_bus_get_irq_level(piix3->dev.bus, pirq));
574 }
575 return 0;
576}
577
578static void piix3_pre_save(void *opaque)
579{
580 int i;
581 PIIX3State *piix3 = opaque;
582
583 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
584 piix3->pci_irq_levels_vmstate[i] =
585 pci_bus_get_irq_level(piix3->dev.bus, i);
586 }
587}
588
589static bool piix3_rcr_needed(void *opaque)
590{
591 PIIX3State *piix3 = opaque;
592
593 return (piix3->rcr != 0);
594}
595
596static const VMStateDescription vmstate_piix3_rcr = {
597 .name = "PIIX3/rcr",
598 .version_id = 1,
599 .minimum_version_id = 1,
600 .needed = piix3_rcr_needed,
601 .fields = (VMStateField[]) {
602 VMSTATE_UINT8(rcr, PIIX3State),
603 VMSTATE_END_OF_LIST()
604 }
605};
606
607static const VMStateDescription vmstate_piix3 = {
608 .name = "PIIX3",
609 .version_id = 3,
610 .minimum_version_id = 2,
611 .post_load = piix3_post_load,
612 .pre_save = piix3_pre_save,
613 .fields = (VMStateField[]) {
614 VMSTATE_PCI_DEVICE(dev, PIIX3State),
615 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
616 PIIX_NUM_PIRQS, 3),
617 VMSTATE_END_OF_LIST()
618 },
619 .subsections = (const VMStateDescription*[]) {
620 &vmstate_piix3_rcr,
621 NULL
622 }
623};
624
625
626static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
627{
628 PIIX3State *d = opaque;
629
630 if (val & 4) {
631 qemu_system_reset_request();
632 return;
633 }
634 d->rcr = val & 2;
635}
636
637static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
638{
639 PIIX3State *d = opaque;
640
641 return d->rcr;
642}
643
644static const MemoryRegionOps rcr_ops = {
645 .read = rcr_read,
646 .write = rcr_write,
647 .endianness = DEVICE_LITTLE_ENDIAN
648};
649
650static void piix3_realize(PCIDevice *dev, Error **errp)
651{
652 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
653
654 isa_bus_new(DEVICE(d), get_system_memory(),
655 pci_address_space_io(dev));
656
657 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
658 "piix3-reset-control", 1);
659 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
660 &d->rcr_mem, 1);
661
662 qemu_register_reset(piix3_reset, d);
663}
664
665static void pci_piix3_class_init(ObjectClass *klass, void *data)
666{
667 DeviceClass *dc = DEVICE_CLASS(klass);
668 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
669
670 dc->desc = "ISA bridge";
671 dc->vmsd = &vmstate_piix3;
672 dc->hotpluggable = false;
673 k->realize = piix3_realize;
674 k->vendor_id = PCI_VENDOR_ID_INTEL;
675
676 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
677 k->class_id = PCI_CLASS_BRIDGE_ISA;
678
679
680
681
682 dc->cannot_instantiate_with_device_add_yet = true;
683}
684
685static const TypeInfo piix3_pci_type_info = {
686 .name = TYPE_PIIX3_PCI_DEVICE,
687 .parent = TYPE_PCI_DEVICE,
688 .instance_size = sizeof(PIIX3State),
689 .abstract = true,
690 .class_init = pci_piix3_class_init,
691};
692
693static void piix3_class_init(ObjectClass *klass, void *data)
694{
695 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
696
697 k->config_write = piix3_write_config;
698}
699
700static const TypeInfo piix3_info = {
701 .name = "PIIX3",
702 .parent = TYPE_PIIX3_PCI_DEVICE,
703 .class_init = piix3_class_init,
704};
705
706static void piix3_xen_class_init(ObjectClass *klass, void *data)
707{
708 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
709
710 k->config_write = piix3_write_config_xen;
711};
712
713static const TypeInfo piix3_xen_info = {
714 .name = "PIIX3-xen",
715 .parent = TYPE_PIIX3_PCI_DEVICE,
716 .class_init = piix3_xen_class_init,
717};
718
719static void i440fx_class_init(ObjectClass *klass, void *data)
720{
721 DeviceClass *dc = DEVICE_CLASS(klass);
722 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
723
724 k->realize = i440fx_realize;
725 k->config_write = i440fx_write_config;
726 k->vendor_id = PCI_VENDOR_ID_INTEL;
727 k->device_id = PCI_DEVICE_ID_INTEL_82441;
728 k->revision = 0x02;
729 k->class_id = PCI_CLASS_BRIDGE_HOST;
730 dc->desc = "Host bridge";
731 dc->vmsd = &vmstate_i440fx;
732
733
734
735
736 dc->cannot_instantiate_with_device_add_yet = true;
737 dc->hotpluggable = false;
738}
739
740static const TypeInfo i440fx_info = {
741 .name = TYPE_I440FX_PCI_DEVICE,
742 .parent = TYPE_PCI_DEVICE,
743 .instance_size = sizeof(PCII440FXState),
744 .class_init = i440fx_class_init,
745};
746
747
748typedef struct {
749 uint8_t offset;
750 uint8_t len;
751} IGDHostInfo;
752
753
754static const IGDHostInfo igd_host_bridge_infos[] = {
755 {0x08, 2},
756 {0x2c, 2},
757 {0x2e, 2},
758 {0x50, 2},
759 {0x52, 2},
760 {0xa4, 4},
761 {0xa8, 4},
762};
763
764static int host_pci_config_read(int pos, int len, uint32_t val)
765{
766 char path[PATH_MAX];
767 int config_fd;
768 ssize_t size = sizeof(path);
769
770 int rc = snprintf(path, size, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
771 0, 0, 0, 0, "config");
772 int ret = 0;
773
774 if (rc >= size || rc < 0) {
775 return -ENODEV;
776 }
777
778 config_fd = open(path, O_RDWR);
779 if (config_fd < 0) {
780 return -ENODEV;
781 }
782
783 if (lseek(config_fd, pos, SEEK_SET) != pos) {
784 ret = -errno;
785 goto out;
786 }
787 do {
788 rc = read(config_fd, (uint8_t *)&val, len);
789 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
790 if (rc != len) {
791 ret = -errno;
792 }
793out:
794 close(config_fd);
795 return ret;
796}
797
798static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev)
799{
800 uint32_t val = 0;
801 int rc, i, num;
802 int pos, len;
803
804 num = ARRAY_SIZE(igd_host_bridge_infos);
805 for (i = 0; i < num; i++) {
806 pos = igd_host_bridge_infos[i].offset;
807 len = igd_host_bridge_infos[i].len;
808 rc = host_pci_config_read(pos, len, val);
809 if (rc) {
810 return -ENODEV;
811 }
812 pci_default_write_config(pci_dev, pos, val, len);
813 }
814
815 return 0;
816}
817
818static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
819{
820 DeviceClass *dc = DEVICE_CLASS(klass);
821 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
822
823 k->init = igd_pt_i440fx_initfn;
824 dc->desc = "IGD Passthrough Host bridge";
825}
826
827static const TypeInfo igd_passthrough_i440fx_info = {
828 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
829 .parent = TYPE_I440FX_PCI_DEVICE,
830 .instance_size = sizeof(PCII440FXState),
831 .class_init = igd_passthrough_i440fx_class_init,
832};
833
834static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
835 PCIBus *rootbus)
836{
837 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
838
839
840 if (s->short_root_bus) {
841 return "0000";
842 }
843 return "0000:00";
844}
845
846static Property i440fx_props[] = {
847 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
848 pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
849 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
850 DEFINE_PROP_END_OF_LIST(),
851};
852
853static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
854{
855 DeviceClass *dc = DEVICE_CLASS(klass);
856 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
857
858 hc->root_bus_path = i440fx_pcihost_root_bus_path;
859 dc->realize = i440fx_pcihost_realize;
860 dc->fw_name = "pci";
861 dc->props = i440fx_props;
862}
863
864static const TypeInfo i440fx_pcihost_info = {
865 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
866 .parent = TYPE_PCI_HOST_BRIDGE,
867 .instance_size = sizeof(I440FXState),
868 .instance_init = i440fx_pcihost_initfn,
869 .class_init = i440fx_pcihost_class_init,
870};
871
872static void i440fx_register_types(void)
873{
874 type_register_static(&i440fx_info);
875 type_register_static(&igd_passthrough_i440fx_info);
876 type_register_static(&piix3_pci_type_info);
877 type_register_static(&piix3_info);
878 type_register_static(&piix3_xen_info);
879 type_register_static(&i440fx_pcihost_info);
880}
881
882type_init(i440fx_register_types)
883