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19#ifndef CPU_ARM_H
20#define CPU_ARM_H
21
22#include "config.h"
23
24#include "kvm-consts.h"
25
26#if defined(TARGET_AARCH64)
27
28# define TARGET_LONG_BITS 64
29#else
30# define TARGET_LONG_BITS 32
31#endif
32
33#define TARGET_IS_BIENDIAN 1
34
35#define CPUArchState struct CPUARMState
36
37#include "qemu-common.h"
38#include "exec/cpu-defs.h"
39
40#include "fpu/softfloat.h"
41
42#define EXCP_UDEF 1
43#define EXCP_SWI 2
44#define EXCP_PREFETCH_ABORT 3
45#define EXCP_DATA_ABORT 4
46#define EXCP_IRQ 5
47#define EXCP_FIQ 6
48#define EXCP_BKPT 7
49#define EXCP_EXCEPTION_EXIT 8
50#define EXCP_KERNEL_TRAP 9
51#define EXCP_STREX 10
52#define EXCP_HVC 11
53#define EXCP_HYP_TRAP 12
54#define EXCP_SMC 13
55#define EXCP_VIRQ 14
56#define EXCP_VFIQ 15
57#define EXCP_SEMIHOST 16
58
59#define ARMV7M_EXCP_RESET 1
60#define ARMV7M_EXCP_NMI 2
61#define ARMV7M_EXCP_HARD 3
62#define ARMV7M_EXCP_MEM 4
63#define ARMV7M_EXCP_BUS 5
64#define ARMV7M_EXCP_USAGE 6
65#define ARMV7M_EXCP_SVC 11
66#define ARMV7M_EXCP_DEBUG 12
67#define ARMV7M_EXCP_PENDSV 14
68#define ARMV7M_EXCP_SYSTICK 15
69
70
71#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
72#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
73#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
74
75
76
77
78
79
80
81#ifdef HOST_WORDS_BIGENDIAN
82#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
83#define offsetofhigh32(S, M) offsetof(S, M)
84#else
85#define offsetoflow32(S, M) offsetof(S, M)
86#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
87#endif
88
89
90#define ARM_CPU_IRQ 0
91#define ARM_CPU_FIQ 1
92#define ARM_CPU_VIRQ 2
93#define ARM_CPU_VFIQ 3
94
95struct arm_boot_info;
96
97#define NB_MMU_MODES 7
98#define TARGET_INSN_START_EXTRA_WORDS 1
99
100
101
102
103
104
105
106
107
108
109typedef struct ARMGenericTimer {
110 uint64_t cval;
111 uint64_t ctl;
112} ARMGenericTimer;
113
114#define GTIMER_PHYS 0
115#define GTIMER_VIRT 1
116#define GTIMER_HYP 2
117#define GTIMER_SEC 3
118#define NUM_GTIMERS 4
119
120typedef struct {
121 uint64_t raw_tcr;
122 uint32_t mask;
123 uint32_t base_mask;
124} TCR;
125
126typedef struct CPUARMState {
127
128 uint32_t regs[16];
129
130
131
132
133
134
135 uint64_t xregs[32];
136 uint64_t pc;
137
138
139
140
141
142
143
144
145
146
147
148 uint32_t pstate;
149 uint32_t aarch64;
150
151
152
153
154 uint32_t uncached_cpsr;
155 uint32_t spsr;
156
157
158 uint64_t banked_spsr[8];
159 uint32_t banked_r13[8];
160 uint32_t banked_r14[8];
161
162
163 uint32_t usr_regs[5];
164 uint32_t fiq_regs[5];
165
166
167 uint32_t CF;
168 uint32_t VF;
169 uint32_t NF;
170 uint32_t ZF;
171 uint32_t QF;
172 uint32_t GE;
173 uint32_t thumb;
174 uint32_t condexec_bits;
175 uint64_t daif;
176
177 uint64_t elr_el[4];
178 uint64_t sp_el[4];
179
180
181 struct {
182 uint32_t c0_cpuid;
183 union {
184 struct {
185 uint64_t _unused_csselr0;
186 uint64_t csselr_ns;
187 uint64_t _unused_csselr1;
188 uint64_t csselr_s;
189 };
190 uint64_t csselr_el[4];
191 };
192 union {
193 struct {
194 uint64_t _unused_sctlr;
195 uint64_t sctlr_ns;
196 uint64_t hsctlr;
197 uint64_t sctlr_s;
198 };
199 uint64_t sctlr_el[4];
200 };
201 uint64_t cpacr_el1;
202 uint64_t cptr_el[4];
203 uint32_t c1_xscaleauxcr;
204 uint64_t sder;
205 uint32_t nsacr;
206 union {
207 struct {
208 uint64_t _unused_ttbr0_0;
209 uint64_t ttbr0_ns;
210 uint64_t _unused_ttbr0_1;
211 uint64_t ttbr0_s;
212 };
213 uint64_t ttbr0_el[4];
214 };
215 union {
216 struct {
217 uint64_t _unused_ttbr1_0;
218 uint64_t ttbr1_ns;
219 uint64_t _unused_ttbr1_1;
220 uint64_t ttbr1_s;
221 };
222 uint64_t ttbr1_el[4];
223 };
224 uint64_t vttbr_el2;
225
226 TCR tcr_el[4];
227 TCR vtcr_el2;
228 uint32_t c2_data;
229 uint32_t c2_insn;
230 union {
231
232
233 struct {
234 uint64_t dacr_ns;
235 uint64_t dacr_s;
236 };
237 struct {
238 uint64_t dacr32_el2;
239 };
240 };
241 uint32_t pmsav5_data_ap;
242 uint32_t pmsav5_insn_ap;
243 uint64_t hcr_el2;
244 uint64_t scr_el3;
245 union {
246 struct {
247 uint64_t ifsr_ns;
248 uint64_t ifsr_s;
249 };
250 struct {
251 uint64_t ifsr32_el2;
252 };
253 };
254 union {
255 struct {
256 uint64_t _unused_dfsr;
257 uint64_t dfsr_ns;
258 uint64_t hsr;
259 uint64_t dfsr_s;
260 };
261 uint64_t esr_el[4];
262 };
263 uint32_t c6_region[8];
264 union {
265 struct {
266 uint64_t _unused_far0;
267#ifdef HOST_WORDS_BIGENDIAN
268 uint32_t ifar_ns;
269 uint32_t dfar_ns;
270 uint32_t ifar_s;
271 uint32_t dfar_s;
272#else
273 uint32_t dfar_ns;
274 uint32_t ifar_ns;
275 uint32_t dfar_s;
276 uint32_t ifar_s;
277#endif
278 uint64_t _unused_far3;
279 };
280 uint64_t far_el[4];
281 };
282 uint64_t hpfar_el2;
283 union {
284 struct {
285 uint64_t _unused_par_0;
286 uint64_t par_ns;
287 uint64_t _unused_par_1;
288 uint64_t par_s;
289 };
290 uint64_t par_el[4];
291 };
292
293 uint32_t c6_rgnr;
294
295 uint32_t c9_insn;
296 uint32_t c9_data;
297 uint64_t c9_pmcr;
298 uint64_t c9_pmcnten;
299 uint32_t c9_pmovsr;
300 uint32_t c9_pmxevtyper;
301 uint32_t c9_pmuserenr;
302 uint32_t c9_pminten;
303 union {
304 struct {
305#ifdef HOST_WORDS_BIGENDIAN
306 uint64_t _unused_mair_0;
307 uint32_t mair1_ns;
308 uint32_t mair0_ns;
309 uint64_t _unused_mair_1;
310 uint32_t mair1_s;
311 uint32_t mair0_s;
312#else
313 uint64_t _unused_mair_0;
314 uint32_t mair0_ns;
315 uint32_t mair1_ns;
316 uint64_t _unused_mair_1;
317 uint32_t mair0_s;
318 uint32_t mair1_s;
319#endif
320 };
321 uint64_t mair_el[4];
322 };
323 union {
324 struct {
325 uint64_t _unused_vbar;
326 uint64_t vbar_ns;
327 uint64_t hvbar;
328 uint64_t vbar_s;
329 };
330 uint64_t vbar_el[4];
331 };
332 uint32_t mvbar;
333 struct {
334 uint32_t fcseidr_ns;
335 uint32_t fcseidr_s;
336 };
337 union {
338 struct {
339 uint64_t _unused_contextidr_0;
340 uint64_t contextidr_ns;
341 uint64_t _unused_contextidr_1;
342 uint64_t contextidr_s;
343 };
344 uint64_t contextidr_el[4];
345 };
346 union {
347 struct {
348 uint64_t tpidrurw_ns;
349 uint64_t tpidrprw_ns;
350 uint64_t htpidr;
351 uint64_t _tpidr_el3;
352 };
353 uint64_t tpidr_el[4];
354 };
355
356 uint64_t tpidrurw_s;
357 uint64_t tpidrprw_s;
358 uint64_t tpidruro_s;
359
360 union {
361 uint64_t tpidruro_ns;
362 uint64_t tpidrro_el[1];
363 };
364 uint64_t c14_cntfrq;
365 uint64_t c14_cntkctl;
366 uint32_t cnthctl_el2;
367 uint64_t cntvoff_el2;
368 ARMGenericTimer c14_timer[NUM_GTIMERS];
369 uint32_t c15_cpar;
370 uint32_t c15_ticonfig;
371 uint32_t c15_i_max;
372 uint32_t c15_i_min;
373 uint32_t c15_threadid;
374 uint32_t c15_config_base_address;
375 uint32_t c15_diagnostic;
376 uint32_t c15_power_diagnostic;
377 uint32_t c15_power_control;
378 uint64_t dbgbvr[16];
379 uint64_t dbgbcr[16];
380 uint64_t dbgwvr[16];
381 uint64_t dbgwcr[16];
382 uint64_t mdscr_el1;
383 uint64_t oslsr_el1;
384 uint64_t mdcr_el2;
385
386
387
388 uint64_t c15_ccnt;
389 uint64_t pmccfiltr_el0;
390 uint64_t vpidr_el2;
391 uint64_t vmpidr_el2;
392 } cp15;
393
394 struct {
395 uint32_t other_sp;
396 uint32_t vecbase;
397 uint32_t basepri;
398 uint32_t control;
399 int current_sp;
400 int exception;
401 } v7m;
402
403
404
405
406
407
408
409 struct {
410 uint32_t syndrome;
411 uint32_t fsr;
412 uint64_t vaddress;
413 uint32_t target_el;
414
415
416
417 } exception;
418
419
420 uint32_t teecr;
421 uint32_t teehbr;
422
423
424 struct {
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440 float64 regs[64];
441
442 uint32_t xregs[16];
443
444 int vec_len;
445 int vec_stride;
446
447
448 uint32_t scratch[8];
449
450
451
452
453
454
455
456
457
458
459
460
461
462 float_status fp_status;
463 float_status standard_fp_status;
464 } vfp;
465 uint64_t exclusive_addr;
466 uint64_t exclusive_val;
467 uint64_t exclusive_high;
468#if defined(CONFIG_USER_ONLY)
469 uint64_t exclusive_test;
470 uint32_t exclusive_info;
471#endif
472
473
474 struct {
475 uint64_t regs[16];
476 uint64_t val;
477
478 uint32_t cregs[16];
479 } iwmmxt;
480
481
482 bool bswap_code;
483
484#if defined(CONFIG_USER_ONLY)
485
486 int eabi;
487#endif
488
489 struct CPUBreakpoint *cpu_breakpoint[16];
490 struct CPUWatchpoint *cpu_watchpoint[16];
491
492 CPU_COMMON
493
494
495
496
497 uint64_t features;
498
499
500 struct {
501 uint32_t *drbar;
502 uint32_t *drsr;
503 uint32_t *dracr;
504 } pmsav7;
505
506 void *nvic;
507 const struct arm_boot_info *boot_info;
508} CPUARMState;
509
510#include "cpu-qom.h"
511
512ARMCPU *cpu_arm_init(const char *cpu_model);
513int cpu_arm_exec(CPUState *cpu);
514target_ulong do_arm_semihosting(CPUARMState *env);
515void aarch64_sync_32_to_64(CPUARMState *env);
516void aarch64_sync_64_to_32(CPUARMState *env);
517
518static inline bool is_a64(CPUARMState *env)
519{
520 return env->aarch64;
521}
522
523
524
525
526int cpu_arm_signal_handler(int host_signum, void *pinfo,
527 void *puc);
528
529
530
531
532
533
534
535
536
537
538void pmccntr_sync(CPUARMState *env);
539
540
541
542
543
544
545
546#define SCTLR_M (1U << 0)
547#define SCTLR_A (1U << 1)
548#define SCTLR_C (1U << 2)
549#define SCTLR_W (1U << 3)
550#define SCTLR_SA (1U << 3)
551#define SCTLR_P (1U << 4)
552#define SCTLR_SA0 (1U << 4)
553#define SCTLR_D (1U << 5)
554#define SCTLR_CP15BEN (1U << 5)
555#define SCTLR_L (1U << 6)
556#define SCTLR_B (1U << 7)
557#define SCTLR_ITD (1U << 7)
558#define SCTLR_S (1U << 8)
559#define SCTLR_SED (1U << 8)
560#define SCTLR_R (1U << 9)
561#define SCTLR_UMA (1U << 9)
562#define SCTLR_F (1U << 10)
563#define SCTLR_SW (1U << 10)
564#define SCTLR_Z (1U << 11)
565#define SCTLR_I (1U << 12)
566#define SCTLR_V (1U << 13)
567#define SCTLR_RR (1U << 14)
568#define SCTLR_DZE (1U << 14)
569#define SCTLR_L4 (1U << 15)
570#define SCTLR_UCT (1U << 15)
571#define SCTLR_DT (1U << 16)
572#define SCTLR_nTWI (1U << 16)
573#define SCTLR_HA (1U << 17)
574#define SCTLR_BR (1U << 17)
575#define SCTLR_IT (1U << 18)
576#define SCTLR_nTWE (1U << 18)
577#define SCTLR_WXN (1U << 19)
578#define SCTLR_ST (1U << 20)
579#define SCTLR_UWXN (1U << 20)
580#define SCTLR_FI (1U << 21)
581#define SCTLR_U (1U << 22)
582#define SCTLR_XP (1U << 23)
583#define SCTLR_VE (1U << 24)
584#define SCTLR_E0E (1U << 24)
585#define SCTLR_EE (1U << 25)
586#define SCTLR_L2 (1U << 26)
587#define SCTLR_UCI (1U << 26)
588#define SCTLR_NMFI (1U << 27)
589#define SCTLR_TRE (1U << 28)
590#define SCTLR_AFE (1U << 29)
591#define SCTLR_TE (1U << 30)
592
593#define CPTR_TCPAC (1U << 31)
594#define CPTR_TTA (1U << 20)
595#define CPTR_TFP (1U << 10)
596
597#define CPSR_M (0x1fU)
598#define CPSR_T (1U << 5)
599#define CPSR_F (1U << 6)
600#define CPSR_I (1U << 7)
601#define CPSR_A (1U << 8)
602#define CPSR_E (1U << 9)
603#define CPSR_IT_2_7 (0xfc00U)
604#define CPSR_GE (0xfU << 16)
605#define CPSR_IL (1U << 20)
606
607
608
609
610
611#define CPSR_RESERVED (0x7U << 21)
612#define CPSR_J (1U << 24)
613#define CPSR_IT_0_1 (3U << 25)
614#define CPSR_Q (1U << 27)
615#define CPSR_V (1U << 28)
616#define CPSR_C (1U << 29)
617#define CPSR_Z (1U << 30)
618#define CPSR_N (1U << 31)
619#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
620#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
621
622#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
623#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
624 | CPSR_NZCV)
625
626#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
627
628#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
629
630#define CPSR_ERET_MASK (~CPSR_RESERVED)
631
632#define TTBCR_N (7U << 0)
633#define TTBCR_T0SZ (7U << 0)
634#define TTBCR_PD0 (1U << 4)
635#define TTBCR_PD1 (1U << 5)
636#define TTBCR_EPD0 (1U << 7)
637#define TTBCR_IRGN0 (3U << 8)
638#define TTBCR_ORGN0 (3U << 10)
639#define TTBCR_SH0 (3U << 12)
640#define TTBCR_T1SZ (3U << 16)
641#define TTBCR_A1 (1U << 22)
642#define TTBCR_EPD1 (1U << 23)
643#define TTBCR_IRGN1 (3U << 24)
644#define TTBCR_ORGN1 (3U << 26)
645#define TTBCR_SH1 (1U << 28)
646#define TTBCR_EAE (1U << 31)
647
648
649
650
651
652#define PSTATE_SP (1U)
653#define PSTATE_M (0xFU)
654#define PSTATE_nRW (1U << 4)
655#define PSTATE_F (1U << 6)
656#define PSTATE_I (1U << 7)
657#define PSTATE_A (1U << 8)
658#define PSTATE_D (1U << 9)
659#define PSTATE_IL (1U << 20)
660#define PSTATE_SS (1U << 21)
661#define PSTATE_V (1U << 28)
662#define PSTATE_C (1U << 29)
663#define PSTATE_Z (1U << 30)
664#define PSTATE_N (1U << 31)
665#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
666#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
667#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
668
669#define PSTATE_MODE_EL3h 13
670#define PSTATE_MODE_EL3t 12
671#define PSTATE_MODE_EL2h 9
672#define PSTATE_MODE_EL2t 8
673#define PSTATE_MODE_EL1h 5
674#define PSTATE_MODE_EL1t 4
675#define PSTATE_MODE_EL0t 0
676
677
678static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
679{
680 return (el << 2) | handler;
681}
682
683
684
685
686
687static inline uint32_t pstate_read(CPUARMState *env)
688{
689 int ZF;
690
691 ZF = (env->ZF == 0);
692 return (env->NF & 0x80000000) | (ZF << 30)
693 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
694 | env->pstate | env->daif;
695}
696
697static inline void pstate_write(CPUARMState *env, uint32_t val)
698{
699 env->ZF = (~val) & PSTATE_Z;
700 env->NF = val;
701 env->CF = (val >> 29) & 1;
702 env->VF = (val << 3) & 0x80000000;
703 env->daif = val & PSTATE_DAIF;
704 env->pstate = val & ~CACHED_PSTATE_BITS;
705}
706
707
708uint32_t cpsr_read(CPUARMState *env);
709
710void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
711
712
713static inline uint32_t xpsr_read(CPUARMState *env)
714{
715 int ZF;
716 ZF = (env->ZF == 0);
717 return (env->NF & 0x80000000) | (ZF << 30)
718 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
719 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
720 | ((env->condexec_bits & 0xfc) << 8)
721 | env->v7m.exception;
722}
723
724
725static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
726{
727 if (mask & CPSR_NZCV) {
728 env->ZF = (~val) & CPSR_Z;
729 env->NF = val;
730 env->CF = (val >> 29) & 1;
731 env->VF = (val << 3) & 0x80000000;
732 }
733 if (mask & CPSR_Q)
734 env->QF = ((val & CPSR_Q) != 0);
735 if (mask & (1 << 24))
736 env->thumb = ((val & (1 << 24)) != 0);
737 if (mask & CPSR_IT_0_1) {
738 env->condexec_bits &= ~3;
739 env->condexec_bits |= (val >> 25) & 3;
740 }
741 if (mask & CPSR_IT_2_7) {
742 env->condexec_bits &= 3;
743 env->condexec_bits |= (val >> 8) & 0xfc;
744 }
745 if (mask & 0x1ff) {
746 env->v7m.exception = val & 0x1ff;
747 }
748}
749
750#define HCR_VM (1ULL << 0)
751#define HCR_SWIO (1ULL << 1)
752#define HCR_PTW (1ULL << 2)
753#define HCR_FMO (1ULL << 3)
754#define HCR_IMO (1ULL << 4)
755#define HCR_AMO (1ULL << 5)
756#define HCR_VF (1ULL << 6)
757#define HCR_VI (1ULL << 7)
758#define HCR_VSE (1ULL << 8)
759#define HCR_FB (1ULL << 9)
760#define HCR_BSU_MASK (3ULL << 10)
761#define HCR_DC (1ULL << 12)
762#define HCR_TWI (1ULL << 13)
763#define HCR_TWE (1ULL << 14)
764#define HCR_TID0 (1ULL << 15)
765#define HCR_TID1 (1ULL << 16)
766#define HCR_TID2 (1ULL << 17)
767#define HCR_TID3 (1ULL << 18)
768#define HCR_TSC (1ULL << 19)
769#define HCR_TIDCP (1ULL << 20)
770#define HCR_TACR (1ULL << 21)
771#define HCR_TSW (1ULL << 22)
772#define HCR_TPC (1ULL << 23)
773#define HCR_TPU (1ULL << 24)
774#define HCR_TTLB (1ULL << 25)
775#define HCR_TVM (1ULL << 26)
776#define HCR_TGE (1ULL << 27)
777#define HCR_TDZ (1ULL << 28)
778#define HCR_HCD (1ULL << 29)
779#define HCR_TRVM (1ULL << 30)
780#define HCR_RW (1ULL << 31)
781#define HCR_CD (1ULL << 32)
782#define HCR_ID (1ULL << 33)
783#define HCR_MASK ((1ULL << 34) - 1)
784
785#define SCR_NS (1U << 0)
786#define SCR_IRQ (1U << 1)
787#define SCR_FIQ (1U << 2)
788#define SCR_EA (1U << 3)
789#define SCR_FW (1U << 4)
790#define SCR_AW (1U << 5)
791#define SCR_NET (1U << 6)
792#define SCR_SMD (1U << 7)
793#define SCR_HCE (1U << 8)
794#define SCR_SIF (1U << 9)
795#define SCR_RW (1U << 10)
796#define SCR_ST (1U << 11)
797#define SCR_TWI (1U << 12)
798#define SCR_TWE (1U << 13)
799#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
800#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
801
802
803uint32_t vfp_get_fpscr(CPUARMState *env);
804void vfp_set_fpscr(CPUARMState *env, uint32_t val);
805
806
807
808
809
810#define FPSR_MASK 0xf800009f
811#define FPCR_MASK 0x07f79f00
812static inline uint32_t vfp_get_fpsr(CPUARMState *env)
813{
814 return vfp_get_fpscr(env) & FPSR_MASK;
815}
816
817static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
818{
819 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
820 vfp_set_fpscr(env, new_fpscr);
821}
822
823static inline uint32_t vfp_get_fpcr(CPUARMState *env)
824{
825 return vfp_get_fpscr(env) & FPCR_MASK;
826}
827
828static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
829{
830 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
831 vfp_set_fpscr(env, new_fpscr);
832}
833
834enum arm_cpu_mode {
835 ARM_CPU_MODE_USR = 0x10,
836 ARM_CPU_MODE_FIQ = 0x11,
837 ARM_CPU_MODE_IRQ = 0x12,
838 ARM_CPU_MODE_SVC = 0x13,
839 ARM_CPU_MODE_MON = 0x16,
840 ARM_CPU_MODE_ABT = 0x17,
841 ARM_CPU_MODE_HYP = 0x1a,
842 ARM_CPU_MODE_UND = 0x1b,
843 ARM_CPU_MODE_SYS = 0x1f
844};
845
846
847#define ARM_VFP_FPSID 0
848#define ARM_VFP_FPSCR 1
849#define ARM_VFP_MVFR2 5
850#define ARM_VFP_MVFR1 6
851#define ARM_VFP_MVFR0 7
852#define ARM_VFP_FPEXC 8
853#define ARM_VFP_FPINST 9
854#define ARM_VFP_FPINST2 10
855
856
857#define ARM_IWMMXT_wCID 0
858#define ARM_IWMMXT_wCon 1
859#define ARM_IWMMXT_wCSSF 2
860#define ARM_IWMMXT_wCASF 3
861#define ARM_IWMMXT_wCGR0 8
862#define ARM_IWMMXT_wCGR1 9
863#define ARM_IWMMXT_wCGR2 10
864#define ARM_IWMMXT_wCGR3 11
865
866
867
868
869
870enum arm_features {
871 ARM_FEATURE_VFP,
872 ARM_FEATURE_AUXCR,
873 ARM_FEATURE_XSCALE,
874 ARM_FEATURE_IWMMXT,
875 ARM_FEATURE_V6,
876 ARM_FEATURE_V6K,
877 ARM_FEATURE_V7,
878 ARM_FEATURE_THUMB2,
879 ARM_FEATURE_MPU,
880 ARM_FEATURE_VFP3,
881 ARM_FEATURE_VFP_FP16,
882 ARM_FEATURE_NEON,
883 ARM_FEATURE_THUMB_DIV,
884 ARM_FEATURE_M,
885 ARM_FEATURE_OMAPCP,
886 ARM_FEATURE_THUMB2EE,
887 ARM_FEATURE_V7MP,
888 ARM_FEATURE_V4T,
889 ARM_FEATURE_V5,
890 ARM_FEATURE_STRONGARM,
891 ARM_FEATURE_VAPA,
892 ARM_FEATURE_ARM_DIV,
893 ARM_FEATURE_VFP4,
894 ARM_FEATURE_GENERIC_TIMER,
895 ARM_FEATURE_MVFR,
896 ARM_FEATURE_DUMMY_C15_REGS,
897 ARM_FEATURE_CACHE_TEST_CLEAN,
898 ARM_FEATURE_CACHE_DIRTY_REG,
899 ARM_FEATURE_CACHE_BLOCK_OPS,
900 ARM_FEATURE_MPIDR,
901 ARM_FEATURE_PXN,
902 ARM_FEATURE_LPAE,
903 ARM_FEATURE_V8,
904 ARM_FEATURE_AARCH64,
905 ARM_FEATURE_V8_AES,
906 ARM_FEATURE_CBAR,
907 ARM_FEATURE_CRC,
908 ARM_FEATURE_CBAR_RO,
909 ARM_FEATURE_EL2,
910 ARM_FEATURE_EL3,
911 ARM_FEATURE_V8_SHA1,
912 ARM_FEATURE_V8_SHA256,
913 ARM_FEATURE_V8_PMULL,
914 ARM_FEATURE_THUMB_DSP,
915};
916
917static inline int arm_feature(CPUARMState *env, int feature)
918{
919 return (env->features & (1ULL << feature)) != 0;
920}
921
922#if !defined(CONFIG_USER_ONLY)
923
924
925
926
927
928
929static inline bool arm_is_secure_below_el3(CPUARMState *env)
930{
931 if (arm_feature(env, ARM_FEATURE_EL3)) {
932 return !(env->cp15.scr_el3 & SCR_NS);
933 } else {
934
935
936
937 return false;
938 }
939}
940
941
942static inline bool arm_is_secure(CPUARMState *env)
943{
944 if (arm_feature(env, ARM_FEATURE_EL3)) {
945 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
946
947 return true;
948 } else if (!is_a64(env) &&
949 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
950
951 return true;
952 }
953 }
954 return arm_is_secure_below_el3(env);
955}
956
957#else
958static inline bool arm_is_secure_below_el3(CPUARMState *env)
959{
960 return false;
961}
962
963static inline bool arm_is_secure(CPUARMState *env)
964{
965 return false;
966}
967#endif
968
969
970static inline bool arm_el_is_aa64(CPUARMState *env, int el)
971{
972
973
974
975
976 assert(el == 1 || el == 3);
977
978
979
980
981
982
983 return arm_feature(env, ARM_FEATURE_AARCH64);
984}
985
986
987
988
989
990
991
992
993static inline bool access_secure_reg(CPUARMState *env)
994{
995 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
996 !arm_el_is_aa64(env, 3) &&
997 !(env->cp15.scr_el3 & SCR_NS));
998
999 return ret;
1000}
1001
1002
1003#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1004 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1005
1006#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1007 do { \
1008 if (_secure) { \
1009 (_env)->cp15._regname##_s = (_val); \
1010 } else { \
1011 (_env)->cp15._regname##_ns = (_val); \
1012 } \
1013 } while (0)
1014
1015
1016
1017
1018
1019
1020#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1021 A32_BANKED_REG_GET((_env), _regname, \
1022 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1023
1024#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1025 A32_BANKED_REG_SET((_env), _regname, \
1026 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1027 (_val))
1028
1029void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1030uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1031 uint32_t cur_el, bool secure);
1032
1033
1034void armv7m_nvic_set_pending(void *opaque, int irq);
1035int armv7m_nvic_acknowledge_irq(void *opaque);
1036void armv7m_nvic_complete_irq(void *opaque, int irq);
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064#define CP_REG_AA64_SHIFT 28
1065#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1066
1067
1068
1069
1070
1071#define CP_REG_NS_SHIFT 29
1072#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1073
1074#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1075 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1076 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1077
1078#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1079 (CP_REG_AA64_MASK | \
1080 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1081 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1082 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1083 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1084 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1085 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1086
1087
1088
1089
1090static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1091{
1092 uint32_t cpregid = kvmid;
1093 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1094 cpregid |= CP_REG_AA64_MASK;
1095 } else {
1096 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1097 cpregid |= (1 << 15);
1098 }
1099
1100
1101
1102
1103 cpregid |= 1 << CP_REG_NS_SHIFT;
1104 }
1105 return cpregid;
1106}
1107
1108
1109
1110
1111static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1112{
1113 uint64_t kvmid;
1114
1115 if (cpregid & CP_REG_AA64_MASK) {
1116 kvmid = cpregid & ~CP_REG_AA64_MASK;
1117 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1118 } else {
1119 kvmid = cpregid & ~(1 << 15);
1120 if (cpregid & (1 << 15)) {
1121 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1122 } else {
1123 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1124 }
1125 }
1126 return kvmid;
1127}
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151#define ARM_CP_SPECIAL 1
1152#define ARM_CP_CONST 2
1153#define ARM_CP_64BIT 4
1154#define ARM_CP_SUPPRESS_TB_END 8
1155#define ARM_CP_OVERRIDE 16
1156#define ARM_CP_ALIAS 32
1157#define ARM_CP_IO 64
1158#define ARM_CP_NO_RAW 128
1159#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1160#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1161#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1162#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1163#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1164#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1165
1166#define ARM_CP_SENTINEL 0xffff
1167
1168#define ARM_CP_FLAG_MASK 0xff
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179enum {
1180 ARM_CP_STATE_AA32 = 0,
1181 ARM_CP_STATE_AA64 = 1,
1182 ARM_CP_STATE_BOTH = 2,
1183};
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195enum {
1196 ARM_CP_SECSTATE_S = (1 << 0),
1197 ARM_CP_SECSTATE_NS = (1 << 1),
1198};
1199
1200
1201
1202
1203
1204static inline bool cptype_valid(int cptype)
1205{
1206 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1207 || ((cptype & ARM_CP_SPECIAL) &&
1208 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1209}
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228#define PL3_R 0x80
1229#define PL3_W 0x40
1230#define PL2_R (0x20 | PL3_R)
1231#define PL2_W (0x10 | PL3_W)
1232#define PL1_R (0x08 | PL2_R)
1233#define PL1_W (0x04 | PL2_W)
1234#define PL0_R (0x02 | PL1_R)
1235#define PL0_W (0x01 | PL1_W)
1236
1237#define PL3_RW (PL3_R | PL3_W)
1238#define PL2_RW (PL2_R | PL2_W)
1239#define PL1_RW (PL1_R | PL1_W)
1240#define PL0_RW (PL0_R | PL0_W)
1241
1242
1243
1244
1245static inline int arm_current_el(CPUARMState *env)
1246{
1247 if (arm_feature(env, ARM_FEATURE_M)) {
1248 return !((env->v7m.exception == 0) && (env->v7m.control & 1));
1249 }
1250
1251 if (is_a64(env)) {
1252 return extract32(env->pstate, 2, 2);
1253 }
1254
1255 switch (env->uncached_cpsr & 0x1f) {
1256 case ARM_CPU_MODE_USR:
1257 return 0;
1258 case ARM_CPU_MODE_HYP:
1259 return 2;
1260 case ARM_CPU_MODE_MON:
1261 return 3;
1262 default:
1263 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1264
1265
1266
1267 return 3;
1268 }
1269
1270 return 1;
1271 }
1272}
1273
1274typedef struct ARMCPRegInfo ARMCPRegInfo;
1275
1276typedef enum CPAccessResult {
1277
1278 CP_ACCESS_OK = 0,
1279
1280
1281
1282
1283
1284
1285 CP_ACCESS_TRAP = 1,
1286
1287
1288
1289
1290 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1291
1292 CP_ACCESS_TRAP_EL2 = 3,
1293 CP_ACCESS_TRAP_EL3 = 4,
1294
1295 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
1296 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
1297} CPAccessResult;
1298
1299
1300
1301
1302typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1303typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1304 uint64_t value);
1305
1306typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1307
1308typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1309
1310#define CP_ANY 0xff
1311
1312
1313struct ARMCPRegInfo {
1314
1315 const char *name;
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333 uint8_t cp;
1334 uint8_t crn;
1335 uint8_t crm;
1336 uint8_t opc0;
1337 uint8_t opc1;
1338 uint8_t opc2;
1339
1340 int state;
1341
1342 int type;
1343
1344 int access;
1345
1346 int secure;
1347
1348
1349
1350
1351 void *opaque;
1352
1353
1354
1355 uint64_t resetvalue;
1356
1357
1358
1359
1360
1361
1362 ptrdiff_t fieldoffset;
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375 ptrdiff_t bank_fieldoffsets[2];
1376
1377
1378
1379
1380
1381
1382 CPAccessFn *accessfn;
1383
1384
1385
1386
1387 CPReadFn *readfn;
1388
1389
1390
1391
1392 CPWriteFn *writefn;
1393
1394
1395
1396
1397
1398 CPReadFn *raw_readfn;
1399
1400
1401
1402
1403
1404
1405 CPWriteFn *raw_writefn;
1406
1407
1408
1409
1410 CPResetFn *resetfn;
1411};
1412
1413
1414
1415
1416#define CPREG_FIELD32(env, ri) \
1417 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1418#define CPREG_FIELD64(env, ri) \
1419 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1420
1421#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1422
1423void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1424 const ARMCPRegInfo *regs, void *opaque);
1425void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1426 const ARMCPRegInfo *regs, void *opaque);
1427static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1428{
1429 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1430}
1431static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1432{
1433 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1434}
1435const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1436
1437
1438void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1439 uint64_t value);
1440
1441uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1442
1443
1444
1445
1446void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1447
1448
1449
1450
1451static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1452{
1453 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1454}
1455
1456static inline bool cp_access_ok(int current_el,
1457 const ARMCPRegInfo *ri, int isread)
1458{
1459 return (ri->access >> ((current_el * 2) + isread)) & 1;
1460}
1461
1462
1463uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479bool write_list_to_cpustate(ARMCPU *cpu);
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495bool write_cpustate_to_list(ARMCPU *cpu);
1496
1497
1498
1499
1500
1501#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1502
1503#define ARM_CPUID_TI915T 0x54029152
1504#define ARM_CPUID_TI925T 0x54029252
1505
1506#if defined(CONFIG_USER_ONLY)
1507#define TARGET_PAGE_BITS 12
1508#else
1509
1510
1511
1512#define TARGET_PAGE_BITS 10
1513#endif
1514
1515#if defined(TARGET_AARCH64)
1516# define TARGET_PHYS_ADDR_SPACE_BITS 48
1517# define TARGET_VIRT_ADDR_SPACE_BITS 64
1518#else
1519# define TARGET_PHYS_ADDR_SPACE_BITS 40
1520# define TARGET_VIRT_ADDR_SPACE_BITS 32
1521#endif
1522
1523static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
1524 unsigned int target_el)
1525{
1526 CPUARMState *env = cs->env_ptr;
1527 unsigned int cur_el = arm_current_el(env);
1528 bool secure = arm_is_secure(env);
1529 bool pstate_unmasked;
1530 int8_t unmasked = 0;
1531
1532
1533
1534
1535
1536 if (cur_el > target_el) {
1537 return false;
1538 }
1539
1540 switch (excp_idx) {
1541 case EXCP_FIQ:
1542 pstate_unmasked = !(env->daif & PSTATE_F);
1543 break;
1544
1545 case EXCP_IRQ:
1546 pstate_unmasked = !(env->daif & PSTATE_I);
1547 break;
1548
1549 case EXCP_VFIQ:
1550 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1551
1552 return false;
1553 }
1554 return !(env->daif & PSTATE_F);
1555 case EXCP_VIRQ:
1556 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1557
1558 return false;
1559 }
1560 return !(env->daif & PSTATE_I);
1561 default:
1562 g_assert_not_reached();
1563 }
1564
1565
1566
1567
1568
1569 if ((target_el > cur_el) && (target_el != 1)) {
1570
1571 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1572
1573
1574
1575
1576
1577 if (target_el == 3 || !secure) {
1578 unmasked = 1;
1579 }
1580 } else {
1581
1582
1583
1584
1585 bool hcr, scr;
1586
1587 switch (excp_idx) {
1588 case EXCP_FIQ:
1589
1590
1591
1592
1593
1594
1595 hcr = (env->cp15.hcr_el2 & HCR_FMO);
1596 scr = (env->cp15.scr_el3 & SCR_FIQ);
1597
1598
1599
1600
1601
1602
1603 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
1604 break;
1605 case EXCP_IRQ:
1606
1607
1608
1609
1610
1611
1612 hcr = (env->cp15.hcr_el2 & HCR_IMO);
1613 scr = false;
1614 break;
1615 default:
1616 g_assert_not_reached();
1617 }
1618
1619 if ((scr || hcr) && !secure) {
1620 unmasked = 1;
1621 }
1622 }
1623 }
1624
1625
1626
1627
1628 return unmasked || pstate_unmasked;
1629}
1630
1631#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1632
1633#define cpu_exec cpu_arm_exec
1634#define cpu_signal_handler cpu_arm_signal_handler
1635#define cpu_list arm_cpu_list
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1688typedef enum ARMMMUIdx {
1689 ARMMMUIdx_S12NSE0 = 0,
1690 ARMMMUIdx_S12NSE1 = 1,
1691 ARMMMUIdx_S1E2 = 2,
1692 ARMMMUIdx_S1E3 = 3,
1693 ARMMMUIdx_S1SE0 = 4,
1694 ARMMMUIdx_S1SE1 = 5,
1695 ARMMMUIdx_S2NS = 6,
1696
1697
1698
1699 ARMMMUIdx_S1NSE0 = 7,
1700 ARMMMUIdx_S1NSE1 = 8,
1701} ARMMMUIdx;
1702
1703#define MMU_USER_IDX 0
1704
1705
1706static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
1707{
1708 assert(mmu_idx < ARMMMUIdx_S2NS);
1709 return mmu_idx & 3;
1710}
1711
1712
1713static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
1714{
1715 int el = arm_current_el(env);
1716
1717 if (el < 2 && arm_is_secure_below_el3(env)) {
1718 return ARMMMUIdx_S1SE0 + el;
1719 }
1720 return el;
1721}
1722
1723
1724
1725
1726static inline int arm_debug_target_el(CPUARMState *env)
1727{
1728 bool secure = arm_is_secure(env);
1729 bool route_to_el2 = false;
1730
1731 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
1732 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
1733 env->cp15.mdcr_el2 & (1 << 8);
1734 }
1735
1736 if (route_to_el2) {
1737 return 2;
1738 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
1739 !arm_el_is_aa64(env, 3) && secure) {
1740 return 3;
1741 } else {
1742 return 1;
1743 }
1744}
1745
1746static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
1747{
1748 if (arm_current_el(env) == arm_debug_target_el(env)) {
1749 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
1750 || (env->daif & PSTATE_D)) {
1751 return false;
1752 }
1753 }
1754 return true;
1755}
1756
1757static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
1758{
1759 if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
1760 return aa64_generate_debug_exceptions(env);
1761 }
1762 return arm_current_el(env) != 2;
1763}
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1779static inline bool arm_generate_debug_exceptions(CPUARMState *env)
1780{
1781 if (env->aarch64) {
1782 return aa64_generate_debug_exceptions(env);
1783 } else {
1784 return aa32_generate_debug_exceptions(env);
1785 }
1786}
1787
1788
1789
1790
1791static inline bool arm_singlestep_active(CPUARMState *env)
1792{
1793 return extract32(env->cp15.mdscr_el1, 0, 1)
1794 && arm_el_is_aa64(env, arm_debug_target_el(env))
1795 && arm_generate_debug_exceptions(env);
1796}
1797
1798#include "exec/cpu-all.h"
1799
1800
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1804
1805#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1806#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1807#define ARM_TBFLAG_MMUIDX_SHIFT 28
1808#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
1809#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
1810#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1811#define ARM_TBFLAG_PSTATE_SS_SHIFT 26
1812#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1813
1814#define ARM_TBFLAG_FPEXC_EL_SHIFT 24
1815#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
1816
1817
1818#define ARM_TBFLAG_THUMB_SHIFT 0
1819#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1820#define ARM_TBFLAG_VECLEN_SHIFT 1
1821#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1822#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1823#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1824#define ARM_TBFLAG_VFPEN_SHIFT 7
1825#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1826#define ARM_TBFLAG_CONDEXEC_SHIFT 8
1827#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1828#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1829#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1830
1831
1832
1833#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
1834#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1835
1836
1837
1838
1839#define ARM_TBFLAG_NS_SHIFT 19
1840#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
1841
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1844
1845#define ARM_TBFLAG_AARCH64_STATE(F) \
1846 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1847#define ARM_TBFLAG_MMUIDX(F) \
1848 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
1849#define ARM_TBFLAG_SS_ACTIVE(F) \
1850 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1851#define ARM_TBFLAG_PSTATE_SS(F) \
1852 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
1853#define ARM_TBFLAG_FPEXC_EL(F) \
1854 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
1855#define ARM_TBFLAG_THUMB(F) \
1856 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1857#define ARM_TBFLAG_VECLEN(F) \
1858 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1859#define ARM_TBFLAG_VECSTRIDE(F) \
1860 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1861#define ARM_TBFLAG_VFPEN(F) \
1862 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1863#define ARM_TBFLAG_CONDEXEC(F) \
1864 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1865#define ARM_TBFLAG_BSWAP_CODE(F) \
1866 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1867#define ARM_TBFLAG_XSCALE_CPAR(F) \
1868 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1869#define ARM_TBFLAG_NS(F) \
1870 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
1871
1872
1873
1874
1875static inline int fp_exception_el(CPUARMState *env)
1876{
1877 int fpen;
1878 int cur_el = arm_current_el(env);
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1880
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1882
1883 if (!arm_feature(env, ARM_FEATURE_V6)) {
1884 return 0;
1885 }
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1890
1891
1892 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
1893 switch (fpen) {
1894 case 0:
1895 case 2:
1896 if (cur_el == 0 || cur_el == 1) {
1897
1898 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1899 return 3;
1900 }
1901 return 1;
1902 }
1903 if (cur_el == 3 && !is_a64(env)) {
1904
1905 return 3;
1906 }
1907 break;
1908 case 1:
1909 if (cur_el == 0) {
1910 return 1;
1911 }
1912 break;
1913 case 3:
1914 break;
1915 }
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1920
1921
1922 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
1923 && !arm_is_secure_below_el3(env)) {
1924
1925 return 2;
1926 }
1927
1928
1929 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
1930
1931 return 3;
1932 }
1933
1934 return 0;
1935}
1936
1937static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
1938 target_ulong *cs_base, int *flags)
1939{
1940 if (is_a64(env)) {
1941 *pc = env->pc;
1942 *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
1943 } else {
1944 *pc = env->regs[15];
1945 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
1946 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
1947 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
1948 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
1949 | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
1950 if (!(access_secure_reg(env))) {
1951 *flags |= ARM_TBFLAG_NS_MASK;
1952 }
1953 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
1954 || arm_el_is_aa64(env, 1)) {
1955 *flags |= ARM_TBFLAG_VFPEN_MASK;
1956 }
1957 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
1958 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
1959 }
1960
1961 *flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT);
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1969 if (arm_singlestep_active(env)) {
1970 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
1971 if (is_a64(env)) {
1972 if (env->pstate & PSTATE_SS) {
1973 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1974 }
1975 } else {
1976 if (env->uncached_cpsr & PSTATE_SS) {
1977 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1978 }
1979 }
1980 }
1981 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
1982
1983 *cs_base = 0;
1984}
1985
1986#include "exec/exec-all.h"
1987
1988enum {
1989 QEMU_PSCI_CONDUIT_DISABLED = 0,
1990 QEMU_PSCI_CONDUIT_SMC = 1,
1991 QEMU_PSCI_CONDUIT_HVC = 2,
1992};
1993
1994#endif
1995